JPH0322706B2 - - Google Patents
Info
- Publication number
- JPH0322706B2 JPH0322706B2 JP60081827A JP8182785A JPH0322706B2 JP H0322706 B2 JPH0322706 B2 JP H0322706B2 JP 60081827 A JP60081827 A JP 60081827A JP 8182785 A JP8182785 A JP 8182785A JP H0322706 B2 JPH0322706 B2 JP H0322706B2
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- thermal expansion
- semiconductor element
- coefficient
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/20—Arrangements for cooling
- H10W40/25—Arrangements for cooling characterised by their materials
- H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
(イ) 産業上の利用分野
本発明は半導体装置、特にパワー半導体素子を
組み込んだ半導体装置の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improvements in semiconductor devices, particularly semiconductor devices incorporating power semiconductor elements.
(ロ) 従来の技術
従来の半導体装置は第２図に示す如く、アルミ
基板１０上の導電路上に銅で形成したヒートシン
ク１１を介してシリコンパワー半導体素子１２を
固着していた。上述した技術によると銅の熱膨張
率が16.7×10-6／℃、シリコンの熱膨張率が2.4×
10-6／℃となる為両者の熱膨張率が著しく異なり
温度サイクルによつて半導体素子１２を固着する
ろう材にラツクが発生する欠点があつた。他の従
来例として銅とシリコンの熱膨張率を緩和する為
に第３図に示す如く、アルミ基板１０上に銅のヒ
ートシンク１１およびシリコンと熱膨張率のほぼ
等しいモリブデン板１３を介してシリコンパワー
半導体素子１２を固着することによりクラツクの
発生を防止していた。(B) Prior Art As shown in FIG. 2, in a conventional semiconductor device, a silicon power semiconductor element 12 is fixed on a conductive path on an aluminum substrate 10 via a heat sink 11 made of copper. According to the above technology, the coefficient of thermal expansion of copper is 16.7×10 -6 /℃, and that of silicon is 2.4×
10 -6 /°C, the thermal expansion coefficients of the two are significantly different, and there is a drawback that cracks occur in the brazing material for fixing the semiconductor element 12 due to temperature cycles. As another conventional example, in order to reduce the coefficient of thermal expansion of copper and silicon, as shown in FIG. By fixing the semiconductor element 12, cracks are prevented from occurring.
斯る従来技術として例えば特開昭51−6672号公
報等が知られる。 As such a conventional technique, for example, Japanese Patent Laid-Open No. 51-6672 is known.
(ハ) 発明が解決しようとする問題点
上述した従来の構造ではクラツクの発生は低減
できるが、モリブデン板が高価である為コスト高
になる欠点がある。またモリブテン板の介在によ
り半導体素子からアルミ基板までの熱抵抗が増加
する欠点もある。更にモリブデン板を使用しない
場合は半導体素子を固着するろう材にクラツクが
発生する欠点があつた。(c) Problems to be Solved by the Invention Although the above-described conventional structure can reduce the occurrence of cracks, it has the drawback of increasing costs because the molybdenum plates are expensive. Another disadvantage is that the presence of the molybdenum plate increases the thermal resistance from the semiconductor element to the aluminum substrate. Furthermore, when a molybdenum plate is not used, there is a drawback that cracks occur in the brazing material that fixes the semiconductor element.
(ニ) 問題点を解決するための手段
本発明は上述した点に鑑みてなされたものであ
り、第１図に示す如く金属基板１上に銅４、イン
バー５、銅４の３層に積層したヒートシンク２を
使用し、その上面に半導体素子３を固着するもの
である。(d) Means for solving the problems The present invention has been made in view of the above-mentioned points, and as shown in FIG. A heat sink 2 is used, and a semiconductor element 3 is fixed on the upper surface of the heat sink 2.
(ホ) 作 用
本発明に依ればヒートシンクを３層に積層する
ことによりヒートシンクの熱膨張率と半導体素子
の熱膨張率とを緩和することができる。(e) Effects According to the present invention, by stacking the heat sink in three layers, the coefficient of thermal expansion of the heat sink and the coefficient of thermal expansion of the semiconductor element can be reduced.
(ヘ) 実施例
本発明に依る半導体装置は第１図に示す如く、
金属基板１上に３層に積層したヒートシンク２を
介してパワー半導体素子３を固着するものであ
る。(F) Embodiment The semiconductor device according to the present invention is as shown in FIG.
A power semiconductor element 3 is fixed on a metal substrate 1 via a heat sink 2 laminated in three layers.
金属基板１は良熱伝導性のアルミニウムで形成
されその表面は酸化アルミニウム膜で被覆しても
よい。 The metal substrate 1 is made of aluminum having good thermal conductivity, and its surface may be coated with an aluminum oxide film.
ヒートシンク２は銅４、インバー５、銅４の
夫々の板を１対１対１の割合で圧力10〜30ton／
cmのローラでクラツドし圧延工程で所定の厚にな
るまで伸し、プレスで所定の大きさに打抜き、半
導体素子３を固着できる様に銀又はニツケル等で
メツキを行なう。 Heat sink 2 is made of copper 4, invar 5, and copper 4 plates at a 1:1:1 ratio of 10 to 30 tons/pressure.
It is clad with a 1/4 inch roller, stretched to a predetermined thickness in a rolling process, punched out to a predetermined size using a press, and plated with silver or nickel so that the semiconductor element 3 can be fixed.
インバー５はニツケル36％、鉄64％の合金であ
る。インバー５の熱膨張率は1.5×10-6／℃に対
しモリブデンの熱膨張率は5.5×10-6／℃であり、
インバー５はモリブデン約1/3の熱膨張率である。
熱膨張率はモリブデンより好結果を得られる。 Invar 5 is an alloy of 36% nickel and 64% iron. The thermal expansion coefficient of Invar 5 is 1.5×10 -6 /℃, while that of molybdenum is 5.5×10 -6 /℃.
Invar 5 has a thermal expansion coefficient of about 1/3 that of molybdenum.
Better thermal expansion coefficient than molybdenum can be obtained.
前記ヒートシンク２上に半導体素子３をろう付
し、次に金属基板１上にヒートシンク２をろう付
する。 The semiconductor element 3 is brazed onto the heat sink 2, and then the heat sink 2 is brazed onto the metal substrate 1.
斯る本発明の構造に依ればヒートシンク２の３
層の積層の割合を１対１対１にすることに依り熱
膨張率が11×10-6／℃となり銅４の熱膨張率より
小さくなる。又前記積層の割合を１対３対１にす
れば熱膨張率は６×10-6／℃となりシリコンの熱
膨張率に近くなる。 According to the structure of the present invention, heat sinks 2 and 3
By setting the stacking ratio of the layers to 1:1:1, the coefficient of thermal expansion becomes 11×10 −6 /° C., which is smaller than the coefficient of thermal expansion of copper 4. If the stacking ratio is 1:3:1, the thermal expansion coefficient will be 6×10 -6 /°C, which is close to that of silicon.
(ト) 発明の効果
本発明に依ればヒートシンクを銅、インバー、
銅の３層に積層することによりシリコンパワー半
導体素子を固着するろう材の劣化を防止でき且つ
モリブデン板を使用する場合よりも熱伝導度がよ
くなり放熱性に優れる。又、本発明に依るヒート
シンクは銅、インバー等の安価な材料ででき、極
めて量産に適するヒートシンクを実現できる。(g) Effects of the invention According to the invention, the heat sink can be made of copper, invar or
By laminating three layers of copper, it is possible to prevent the deterioration of the brazing material that fixes the silicon power semiconductor element, and the thermal conductivity is better than when using a molybdenum plate, resulting in excellent heat dissipation. Further, the heat sink according to the present invention is made of inexpensive materials such as copper and invar, and can realize a heat sink that is extremely suitable for mass production.
第１図は本発明による実施例を示す断面図、第
２図および第３図は従来例を示す断面図である。
１……金属基板、２……ヒートシンク、３……
半導体素子、４……銅、５……インバー。
FIG. 1 is a sectional view showing an embodiment of the present invention, and FIGS. 2 and 3 are sectional views showing a conventional example. 1... Metal substrate, 2... Heat sink, 3...
Semiconductor element, 4...Copper, 5...Invar.
Claims (1)
介してパワー半導体素子を固着する半導体装置に
於いて、前記ヒートシンクは両主面を銅板で形成
し、該銅板間に熱膨張係数の低い金属を挿入し、
前記パワー半導体素子との熱膨張係数の差を縮少
させることを特徴とする半導体装置。 ２ 特許請求の範囲第１項に於いて、前記熱膨張
係数の低い金属としてインバーを用いることを特
徴とした半導体装置。[Claims] 1. In a semiconductor device in which a power semiconductor element is fixed on a metal substrate via a heat sink with good thermal conductivity, both main surfaces of the heat sink are formed of copper plates, and thermal expansion between the copper plates is provided. Insert metal with low coefficient,
A semiconductor device characterized in that a difference in thermal expansion coefficient between the power semiconductor element and the power semiconductor element is reduced. 2. A semiconductor device according to claim 1, characterized in that invar is used as the metal with a low coefficient of thermal expansion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60081827A JPS61240665A (en) | 1985-04-17 | 1985-04-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60081827A JPS61240665A (en) | 1985-04-17 | 1985-04-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61240665A JPS61240665A (en) | 1986-10-25 |
| JPH0322706B2 true JPH0322706B2 (en) | 1991-03-27 |
Family
ID=13757304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60081827A Granted JPS61240665A (en) | 1985-04-17 | 1985-04-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61240665A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02104641U (en) * | 1989-02-06 | 1990-08-20 | ||
| JP2777464B2 (en) * | 1990-07-18 | 1998-07-16 | 株式会社日立製作所 | Electronic device and engine ignition device using the same |
| JP2546342Y2 (en) * | 1991-07-22 | 1997-08-27 | 三洋電機株式会社 | Hybrid integrated circuit |
| JPH0515440U (en) * | 1991-07-31 | 1993-02-26 | 京セラ株式会社 | Package for storing optical semiconductor devices |
| JPH06188324A (en) * | 1992-12-16 | 1994-07-08 | Kyocera Corp | Semiconductor device |
| JPH08330507A (en) * | 1995-05-30 | 1996-12-13 | Motorola Inc | Hybrid multi-chip module and manufacturing method thereof |
| US20040216864A1 (en) * | 2003-04-30 | 2004-11-04 | Wong Marvin Glenn | CTE matched application specific heat sink assembly |
| JP2006013368A (en) * | 2004-06-29 | 2006-01-12 | Sanyo Electric Co Ltd | Circuit device and manufacturing method thereof |
| JP4450230B2 (en) | 2005-12-26 | 2010-04-14 | 株式会社デンソー | Semiconductor device |
-
1985
- 1985-04-17 JP JP60081827A patent/JPS61240665A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61240665A (en) | 1986-10-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |