JPH0322707B2 - - Google Patents
Info
- Publication number
- JPH0322707B2 JPH0322707B2 JP60081828A JP8182885A JPH0322707B2 JP H0322707 B2 JPH0322707 B2 JP H0322707B2 JP 60081828 A JP60081828 A JP 60081828A JP 8182885 A JP8182885 A JP 8182885A JP H0322707 B2 JPH0322707 B2 JP H0322707B2
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- thermal expansion
- metal substrate
- copper
- coefficient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/20—Arrangements for cooling
- H10W40/25—Arrangements for cooling characterised by their materials
- H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
Landscapes
- Die Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
(イ) 産業上の利用分野
本発明は半導体装置、特にパワー半導体素子を
組み込んだ半導体装置の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improvements in semiconductor devices, particularly semiconductor devices incorporating power semiconductor elements.
(ロ) 従来の技術
従来の半導体装置は第２図に示す如く、アルミ
ニウム基板１０上の導電路上に銅で形成したヒー
トシンク１１を介してシリコンパワー半導体素子
１２を固着していた。上述した技術によると銅の
熱膨張率が16.7×10-6／℃、シリコンの熱膨張率
が2.4×10-6／℃となる為両者の熱膨張率が著し
く異なり温度サイクルによつて半導体素子１２を
固着するろう材にクラツクが発生する欠点があつ
た。地の従来例として銅とシリコンの熱膨張率を
緩和する為に第３図に示す如く、アルミニウム基
板１０上に銅のヒートシンク１１およびシリコン
と熱膨張率のほぼ等しいモリブデン板１３を介し
てシリコンパワー半導体素子１２を固着すること
によりクラツクの発生を防止していた。(B) Prior Art As shown in FIG. 2, in a conventional semiconductor device, a silicon power semiconductor element 12 is fixed on a conductive path on an aluminum substrate 10 via a heat sink 11 made of copper. According to the above-mentioned technology, the coefficient of thermal expansion of copper is 16.7×10 -6 /°C and that of silicon is 2.4×10 -6 /°C, so the thermal expansion coefficients of the two are significantly different and the temperature cycle will cause the semiconductor device to There was a drawback that cracks occurred in the brazing material that fixed No. 12. As a conventional example, silicon power is applied to an aluminum substrate 10 via a copper heat sink 11 and a molybdenum plate 13 whose thermal expansion coefficient is almost equal to that of silicon, as shown in FIG. By fixing the semiconductor element 12, cracks are prevented from occurring.
斯る従来技術として例えば特開昭51−6672号公
報等が知られる。 As such a conventional technique, for example, Japanese Patent Laid-Open No. 51-6672 is known.
又、従来はアルミニウム基板１０の熱膨張率23
×10-6／℃に対し銅で形成されたヒートシンク１
１の熱膨張率が16.7×10-6／℃と異つていた。 Furthermore, conventionally, the coefficient of thermal expansion of the aluminum substrate 10 is 23
Heat sink 1 made of copper for ×10 -6 /℃
The coefficient of thermal expansion of No. 1 was different from that of 16.7×10 -6 /°C.
(ハ) 発明が解決しようとする問題点
上述した従来の構造ではクラツクの発生は低減
できるが、モリブデン板が高価である為コスト高
になる欠点がある。またモリブデン板の介在によ
り半導体素子からアルミ基板までの熱抵抗が増加
する欠点もあつた。更にアルミニウム基板とヒー
トシンクの熱膨張率が著しく異なる為ろう材にク
ラツクが発生する欠点もあつた。(c) Problems to be Solved by the Invention Although the above-described conventional structure can reduce the occurrence of cracks, it has the drawback of increasing costs because the molybdenum plates are expensive. Another drawback was that the presence of the molybdenum plate increased the thermal resistance from the semiconductor element to the aluminum substrate. Furthermore, since the thermal expansion coefficients of the aluminum substrate and the heat sink are significantly different, there is also the drawback that cracks occur in the brazing filler metal.
(ニ) 問題点を解決するための手段
本発明は上述した点に鑑みてなされたものであ
り、第１図に示す如く、銅４、インバー５、銅４
と３層に積層した金属基板１上に更に銅４、イン
バー５、銅４と３層に積層したヒートシンク２を
介して、その上面に半導体素子３を固着するもの
である。(d) Means for solving the problems The present invention has been made in view of the above-mentioned points, and as shown in FIG.
A semiconductor element 3 is fixed to the upper surface of the metal substrate 1, which is further laminated in three layers, through a heat sink 2, which is further laminated in three layers: copper 4, invar 5, and copper 4.
(ホ) 作 用
本発明に依れば金属基板およびヒートシンクを
３層に積層することにより、金属基板とヒートシ
ンクの熱膨張率を等しく且つヒートシンクと半導
体素子の熱膨張を緩和することができる。(E) Function According to the present invention, by stacking the metal substrate and the heat sink in three layers, it is possible to equalize the thermal expansion coefficients of the metal substrate and the heat sink and to moderate the thermal expansion of the heat sink and the semiconductor element.
(ヘ) 実施例
本発明に依る半導体装置は第１図に示す如く、
３層に積層した金属基板１上に更に３層に積層し
たヒートシンク２を介してパワー半導体素子３を
固着するものである。(F) Embodiment The semiconductor device according to the present invention is as shown in FIG.
A power semiconductor element 3 is fixed on a metal substrate 1 which is laminated in three layers via a heat sink 2 which is further laminated in three layers.
金属基板１は銅４、インバー５、銅４の夫々の
板を１対１対１の割合で圧力10〜30ton／cmのロ
ーラでクラツドを行ない、圧延工程で所定の厚に
なるまで伸しプレスで所定の大きさに打抜き、そ
の表面をニツケルメツキ等を行なつてもよい。 The metal substrate 1 is made by cladding each plate of copper 4, invar 5, and copper 4 in a 1:1:1 ratio with rollers at a pressure of 10 to 30 ton/cm, and stretching and pressing until a predetermined thickness is achieved in a rolling process. It may be punched out to a predetermined size, and the surface may be nickel plated or the like.
ヒートシンク２も前記金属基板同様に銅４、イ
ンバー５、銅４の夫々の板を１対１対１の割合で
圧力10〜30ton／cmのローラでクラツドし圧延工
程で所定の厚になるまで伸しプレスで所定の大き
さに打抜き半導体素子３を固着できるように銀又
はニツケル等のメツキを行なう本実施例では銀メ
ツキを用いる。 Heat sink 2 is also made by cladding copper 4, invar 5, and copper 4 plates in a 1:1:1 ratio with rollers at a pressure of 10 to 30 tons/cm, and stretching them to a predetermined thickness in a rolling process, in the same way as the metal substrate. In this embodiment, silver plating is used, in which silver, nickel, or the like is plated so that the semiconductor element 3 punched to a predetermined size can be fixed using a press.
インバー５はニツケル36％、鉄64％の合金であ
る。インバー５の熱膨張率は1.5×10-6／℃に対
しモリブデンの熱膨張率は5.5×10-6／℃であり、
インバー５はモリブデンの約1/3の熱膨張率であ
る。熱膨張率はモリブデンより好結果を得られ
る。 Invar 5 is an alloy of 36% nickel and 64% iron. The thermal expansion coefficient of Invar 5 is 1.5×10 -6 /℃, while that of molybdenum is 5.5×10 -6 /℃.
Invar 5 has a coefficient of thermal expansion that is approximately 1/3 that of molybdenum. Better thermal expansion coefficient than molybdenum can be obtained.
前記ヒートシンク２上に半導体素子３をろう付
し、次に金属基板１上にヒートシンク２をろう付
する。 The semiconductor element 3 is brazed onto the heat sink 2, and then the heat sink 2 is brazed onto the metal substrate 1.
斯る本発明に依ればヒートシンク２の３層の積
層の割合を１対１対１にすることに依り、熱膨張
率が11×10-6／℃と銅４の熱膨張率より小なりシ
リコンパワー半導体素子３の熱膨張率との差を縮
めることができる。又金属基板１の積層の割合も
１対１対１にすることに依り前記ヒートシンクの
熱膨張率11×10-6／℃と差が全く無くなるので金
属基板１とヒートシンク２を固着するろう材にク
ラツクが発生しなくなる。 According to the present invention, by setting the stacking ratio of the three layers of the heat sink 2 to 1:1:1, the coefficient of thermal expansion is 11×10 -6 /°C, which is smaller than the coefficient of thermal expansion of the copper 4. The difference between the coefficient of thermal expansion and the silicon power semiconductor element 3 can be reduced. Also, by setting the lamination ratio of the metal substrate 1 to 1:1:1, there is no difference between the thermal expansion coefficient of the heat sink, which is 11×10 -6 /°C, so that the brazing material for fixing the metal substrate 1 and the heat sink 2 is Cracks no longer occur.
更に他の実施例として金属基板１およびヒート
シンク２の積層の割合を１対0.5対１にすれば熱
膨張率14×10-6／℃、１対２対１にすれば熱膨張
率８×10-6／℃、１対３対１にすれば熱膨張率６
×10-6／℃となり、１対0.5対１、１対２対１、
１対３対１のいずれの組合せでも可能である。 As another example, if the lamination ratio of the metal substrate 1 and the heat sink 2 is 1:0.5:1, the thermal expansion coefficient is 14×10 -6 /°C, and if the ratio is 1:2:1, the thermal expansion coefficient is 8×10. -6 /℃, if the ratio is 1:3:1, the coefficient of thermal expansion is 6
×10 -6 /℃, 1:0.5:1, 1:2:1,
Any combination of 1:3:1 is possible.
(ト) 発明の効果
本発明に依れば金属基板およびヒートシンクを
銅、インバー、銅と３層に積層することに依りヒ
ートシンクと金属基板を固着するろう材の劣化の
防止が且つシリコンパワー半導体素子を固着する
ろう材の劣化を防止することができる。又、本発
明のヒートシンクは銅、インバー等の安価な材料
ででき極めて量産に適するヒートシンクを実現で
きる。(G) Effects of the Invention According to the present invention, by laminating the metal substrate and the heat sink in three layers of copper, invar, and copper, deterioration of the brazing material that fixes the heat sink and the metal substrate can be prevented, and silicon power semiconductor devices can be manufactured. It is possible to prevent the deterioration of the brazing filler metal that fixes the Furthermore, the heat sink of the present invention can be made of inexpensive materials such as copper and invar, making it possible to realize a heat sink that is extremely suitable for mass production.
第１図は本発明による実施例を示す断面図、第
２図および第３図は従来例を示す断面図である。
１……金属基板、２……ヒートシンク、３……
半導体素子、４……銅、５……インバー。
FIG. 1 is a sectional view showing an embodiment of the present invention, and FIGS. 2 and 3 are sectional views showing a conventional example. 1... Metal substrate, 2... Heat sink, 3...
Semiconductor element, 4...Copper, 5...Invar.
Claims (1)
介してパワー半導体素子を固着する半導体装置に
於いて、前記金属基板及びヒートシンクの夫々の
両主面を銅板で形成し、該銅板間に熱膨張係数の
低い金属を挿入し、前記金属基板とヒートシンク
との熱膨張係数を等しくし、且つ前記ヒートシン
クとパワー半導体素子との熱膨張係数の差を縮少
させることを特徴とする半導体装置。 ２ 特許請求の範囲第１項に於いて、前記熱膨張
係数の低い金属としてインバーを用いることを特
徴とした半導体装置。[Scope of Claims] 1. In a semiconductor device in which a power semiconductor element is fixed on a metal substrate via a heat sink with good thermal conductivity, both main surfaces of the metal substrate and the heat sink are formed of copper plates, and A metal with a low coefficient of thermal expansion is inserted between the copper plates to equalize the coefficients of thermal expansion of the metal substrate and the heat sink, and to reduce the difference in coefficient of thermal expansion between the heat sink and the power semiconductor element. Semiconductor equipment. 2. A semiconductor device according to claim 1, characterized in that invar is used as the metal with a low coefficient of thermal expansion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60081828A JPS61240666A (en) | 1985-04-17 | 1985-04-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60081828A JPS61240666A (en) | 1985-04-17 | 1985-04-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61240666A JPS61240666A (en) | 1986-10-25 |
| JPH0322707B2 true JPH0322707B2 (en) | 1991-03-27 |
Family
ID=13757332
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60081828A Granted JPS61240666A (en) | 1985-04-17 | 1985-04-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61240666A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5015803A (en) * | 1989-05-31 | 1991-05-14 | Olin Corporation | Thermal performance package for integrated circuit chip |
| EP1557932A1 (en) | 2002-10-28 | 2005-07-27 | Toyota Jidosha Kabushiki Kaisha | Generator-motor |
| EP1557931A4 (en) | 2002-10-28 | 2010-11-17 | Toyota Motor Co Ltd | GENERATOR / MOTOR |
| JP4239723B2 (en) | 2003-07-24 | 2009-03-18 | トヨタ自動車株式会社 | A drive system including a generator motor and a computer-readable recording medium storing a program for causing a computer to control the generator motor |
| JP4768024B2 (en) * | 2006-07-28 | 2011-09-07 | 京セラ株式会社 | Electronic component storage package and electronic device |
-
1985
- 1985-04-17 JP JP60081828A patent/JPS61240666A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61240666A (en) | 1986-10-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |