JPH0327128B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention is a method for detecting multiplexed signals obtained by time-division multiplexing a plurality of digital or analog information signals having different sampling frequencies or clock signal frequencies. This invention relates to a time division multiplex signal separation method for separating original information signals.

BACKGROUND OF THE INVENTION One of the applicants has proposed that, for example, when receiving television waves from a broadcast satellite and retransmitting the received signal to a wired system, such as a communal viewing facility, a particularly encoded audio signal is used. Multiple channels are transmitted in the form of encoded signals without demodulation (channels here mean the number of satellite broadcasting channels corresponding to the number of video channels).
We have filed an application for a time division multiplex transmission system suitable for time division multiplexing and retransmitting the signals on one channel of shared viewing equipment.
No. 254220).

This time-division multiplexing transmission system combines N frames of channels that have different sampling frequencies or clock signal frequencies and are transmitted as frames into multiplexed frames (hereinafter referred to as units of multiplexed frames). In order to time-division multiplex and transmit through one transmission path, the highest frequency among the sampling frequencies or clock signal frequencies of the information signals of the N channels or a frequency equal to or higher than the highest frequency The information signals of the N channels are time-division multiplexed using a reference clock signal which is multiplied by N, and a dummy signal and a dummy flag bit are inserted in pairs in channels where the information signal is insufficient to constitute a frame of the channel. In this way, continuous time division multiplexed signals are obtained.

(Object of the Invention) The present invention provides a method for controlling write and read operations of a memory unit in response to a read clock signal whose frequency is changed when a time division multiplexed signal that has been time division multiplexed by the above method is separated into the original signal. Easy control and stable against clock signal frequency fluctuations of signals before multiplexing caused by Doppler shifts due to temperature and hygiene, clock signal frequency fluctuations of time division multiplexed signals, and drifts of readout clock signal frequency control circuits in demultiplexing decoders. It is an object of the present invention to provide a time division multiplexed signal separation method that can perform a separation operation based on the following characteristics.

(Summary of the Invention) In the above-mentioned time division multiplex transmission system, if the dummy data generation period is Z frame intervals after multiplexing, the true information is transmitted between the dummy data (Z-
1) It is a frame. Therefore, when separating a time division multiplexed signal into the original signal, the true information (Z-
1) It is necessary to control the readout clock signal frequency to be lower than 1/N of the transmission clock signal frequency after time division multiplexing in order to read out data with an extended frame interval.

Therefore, according to the method of the present invention, the write frame and read frame of the buffer memory are monitored, and the read clock signal frequency is controlled based on the difference between them.

(Structure of the Invention) In the time division multiplex signal separation method of the present invention for separating the original signal from the above-described time division multiplex signal,
The amount of delay between writing and reading is expressed as (α+βx) frames (a real number with α≧0, β is a value whose unit is the data transmission amount of one frame, and a real number with β>0, x
After detecting the dummy flag bit, the read clock signal frequency is controlled as described below to obtain a continuous bit stream.

In the initial state, the frame buffer memory is set so that the delay between the write frame and the read frame is (α+βx) frames, and the read clock signal frequency _f1 is set to 1/N of the write clock signal frequency fw. I will make it happen. When this relationship exists between both frequencies, it will also be referred to as a non-clock controlled state in the following description.

When a dummy flag bit is detected, writing for β frames is temporarily stopped every time a dummy flag bit is detected. Next, the readout clock signal frequency is lowered, and when the difference between the write frame and the readout frame returns to β frame or more, control is performed to return the readout clock frequency to the original fw/N frequency. Restore to original data.

Therefore, the shortest period in which dummy data appears is
When Tim is set, the frequency control period T during which the read clock signal frequency is controlled is x×Tmin
>T, and the smaller the change in the read clock signal frequency during frequency control, the smaller the clock frequency fluctuation of the demodulated information signal will be.

(Embodiment of the invention) Prior to detailed explanation of the embodiment, the audio subcarrier of satellite broadcasting was demodulated to QPSK, and the obtained
The frame structure when a 2048 Mbit/s bit stream is multiplexed into 4 channels using the above-described method is as shown in FIG. i.e. 16
8-bit frame synchronization data, 8-bit dummy information, 2032-bit A channel information signal, 8
dummy information of 2032 bits, B channel information signal of 2032 bits, 8 bits of dummy information, 2032 bits of C channel information signal, 8 bits of dummy information, 2032 bits of D channel information signal, and 16 bits of remainder bits. A unit frame sequence is formed at . The dummy information before the information signal of each channel includes a dummy flag bit indicating whether the information signal of the following channel is dummy data or not. By checking this dummy flag bit, it is determined whether the information signal of the following channel is dummy data or not.

The present invention will be explained below with reference to Examples.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. One embodiment of the invention is α=0, β=1
The case where x=1 is illustrated.

A time division multiplexed signal obtained by the above-described time division multiplexing method is input to the input terminal 10. In this embodiment, it is assumed that, for example, the bit streams of 4.times.2048 Mbit/s shown in FIG. 5 a-1 and a-2 are input. Note that although parts a-1 and a-2 of FIG. 5 are shown partially overlapping, they are continuous in terms of time.

This bit stream is transmitted to the frame synchronization signal detection circuit 11 and the write clock signal regeneration circuit 1.
The frame synchronization signal detection circuit 11 detects the frame synchronization signal, and the clock signal regeneration circuit 12 reproduces the write clock signal _WCK . Further, the bit stream and write clock signal _WCK are supplied to a dummy flag bit detection circuit 13, which detects the dummy flag bit in the dummy information and determines whether the information signal of the following channel is dummy data or not. When it is determined that this is the case, a prohibition instruction signal is issued to prohibit counting by the write address counter 16, which will be described later.
Output W _INH .

Frame synchronization signal, write clock signal
W _CK , the output of the channel selection instruction switch 14 for selecting a reception channel, and a read clock signal R _CK to be described later are supplied to the system timing generation circuit 15 .
A timing signal necessary for a decoding operation by a time division multiplex signal demultiplexing device (hereinafter also referred to as a decoder) main body M is generated from the time division multiplex signal demultiplexing device (hereinafter also referred to as a decoder).

On the other hand, in this embodiment, 4 frame memory
Frame buffer memory 17 with MF ₁ to MF ₄ configuration
-1, frame memory changeover switches 17-2 and 17-4, and an input selection switch that supplies the information signal of the channel selected by the channel selection instruction switch 14 from the bit stream to the frame memory changeover switch 17-2. 17-3
A memory block 17 is provided. Here, the one frame memory is set to have a capacity that can store the amount of data sent for one frame (2032 bits in this example).

The write clock signal _WCK is supplied to the write address counter 16 to generate the write address signal.
A frame memory number signal WF corresponding to WA and the write frame memory number is generated. The write address signal WA is supplied to the memory block 17 to designate a write address, and the frame memory number signal WF controls the changeover switch 17-2 to select a write frame. On the other hand, the inhibition instruction signal W _INH is also output to the write address counter 16.
The write operation for one frame memory in the memory block 17 is inhibited by stopping the progress of the address signal in response to the inhibition instruction signal W _INH .

The write clock signal _WCK is also passed through the frequency divider circuit 18.
The frequency of the clock signal is divided by 1/N of the frequency of the transmission clock signal after time division multiplexing (=f ₁ ). The output signal of the frequency divider circuit 18 is supplied to a read clock frequency control circuit 19, which generates a read clock signal _RCK having a frequency _f0 . The read clock frequency control circuit 19 includes a dummy flag bit detection circuit 1.
Memory block 1 after the dummy flag is detected by receiving the dummy flag detection output D _MF and the output of the frequency dividing circuit 18 when the dummy flag is detected by 3.
For example, from the time of writing to the first frame memory _MF1 , the read clock signal frequency _f0 is gradually lowered from the frequency _f1 to the frequency _f3 , and when writing to the first frame memory MF1 and the first frame memory _MF1 . When a difference of two frames is detected between the read addresses from the frame memory _MF1 , the frequency is increased from the frequency _f3 to the frequency _f1 by the output of the read/write relative address detection circuit 20.

The read clock signal _RCK is supplied to a read address counter 21, which generates a read address signal RA and a frame memory number signal RF corresponding to the read frame memory number. Read address signal
RA is supplied to memory block 17 to designate a read address, and frame memory number signal RF controls changeover switch 17-4 to select a read frame.

5 a-1, a supplied to the input terminal 10
-2, the multiplexed transmission clock signal, that is, the write clock signal, is obtained from the bit stream shown in FIG.
_WCK and frame synchronization signals are detected and frame synchronization is performed.

In addition, a timing signal from the system timing generation circuit 15 causes a delay of one frame to be provided between the write frame memory and the read frame memory when the power is turned on and when the selected channel is switched by the channel selection instruction switch 14. Switches 17-2 and 17-4 are controlled so as to have an offset of two frames, with one frame existing between the write frame memory and the read frame memory. It is now assumed that the B channel is selected by the large channel selection instruction switch 14, and that the sampling frequency or clock signal frequency of the B channel is lower than that of the other channels before multiplexing on the transmitting side.

After frame synchronization is achieved, the B channel information signal is extracted from the bit stream via the input selection switch 17-3 in response to a timing signal from the system timing generation circuit 15, and the information signal of the B channel is extracted from the bit stream by the frame memory number signal WF.
-2, information signals for one channel are sequentially supplied to one frame memory, and are sent to the frame memory in synchronization with the write clock signal _WCK .
They are sequentially written to MF ₁ , MF ₂ , ...MF ₄ , MF ₁ , .... This state is schematically shown in Figure 5 (b-
1), (as shown in b-2. In addition, Fig. 5b
-1 and b-2 are shown partially overlappingly, illustrating a case where dummy data is inserted every 100th B channel.

On the other hand, the write clock signal _WCK is output from the frequency divider circuit 1.
8, and the read clock frequency control circuit 19 outputs a read clock signal _RCK having a frequency f ₁ (=fw/4). Also,
The frame changeover switch 17-4 is switched by the frame memory number signal RF, two frames behind the write frame memory and in synchronization with the read clock signal _RCK , so that the frame memories MF ₁ , . . . MF ₄ , The information signals of the B _channel stored from . This state is schematically shown in FIG. 5C-1, and as is clear from a comparison with FIG. 5B-1, the read frame memory is two frames behind the write frame memory.

However, dummy data DU is inserted in the 100th B channel. Therefore
A dummy flag bit indicating that the next information signal is dummy data is set in the dummy information immediately before the B channel in the 100th frame row, and this dummy flag bit is detected by the dummy flag bit detection circuit 13. , an inhibition instruction signal W _INH is output. The time when the dummy flag bit is detected in FIGS. 4 and 5 is t ₁
(t ₆ , t ₁₁ ). By outputting the inhibition instruction signal W _INH , writing of one frame's worth of B channel information signals (dummy data in this case) is stopped. However, reading is performed in synchronization with the read clock signal _RCK having the same frequency _f1 . That is, during this period, the clock is not controlled. As a result, the interval between the read frame memory and the write frame memory becomes close, and when writing is resumed, the read frame memory becomes the next frame of the write frame memory. Even in this state, writing to the frame memories MF ₁ , MF ₁ , etc. is performed sequentially. During this period, when the first frame memory MF ₁ is written for the first time after the dummy flag bit is detected (times t ₂ and t ₇ ), the read clock frequency control circuit 19 determines that the data is written to the first frame memory MF 1 from time t ₂ and t ₇ . Frequency of read clock signal _RCK f ₀
is sequentially lowered from frequency f ₁ to frequency f ₃ and is temporarily maintained at frequency f ₃ . In FIG. 4, the times at which the frequency of the read clock signal _RCK matches the frequency _f3 are indicated by _t3 and _t8 .

On the other hand, during the period when the frequency _f0 of the read clock signal _RCK is decreased from the frequency _f1 to the frequency _f3 and during the period when the frequency _f3 is maintained,
The write frame memory is the first frame memory
During the period after the readout frame memory becomes MF ₁ and until the read frame memory becomes the first frame memory MF ₁ , the output number fraction (fw/N) of the frequency dividing circuit 18 is counted, and the counted value is a value equivalent to 2 frame memories. The read/write relative address detection circuit 20 determines whether the
It is determined by As a result of this determination, when the count value reaches a value corresponding to two frame memories (times _t4 and _t9 ), the frequency of the read clock signal _RCK is gradually returned from frequency _f3 to frequency _f1 . In this state, when the frequency f ₀ of the read clock signal R _CK matches the frequency f ₁ (times t ₅ and t ₁₀ ), the frequency is maintained at f ₁ and waits for the next dummy flag bit to be detected. . In addition, Fig. 5 d-
1 and d-2 show a part of the state shown in FIG. 4 superimposed on FIG. 5 C-1 and C-2.

To explain the above operation in other words, assuming that the write frame memory is fixed, as shown in FIG. When a bit is detected, writing is stopped for one frame period.
At the same time, during this period, the read clock signal is in a non-clock controlled state, and only the read frame memory is relatively approaching the write frame memory as shown by the arrow X, and when writing is performed again, , the offset between the write frame memory and the read frame memory is one frame. The selected specific frame memory (in the example above, the first frame memory
Until the information signal is written to MF ₁ ), the state in which the offset is one frame continues. Next, the frequency _f0 of the read clock signal _RCK decreases from the start of writing to the specific frame memory _MF1 .
The offset between the write frame memory and the read frame memory is shifted as shown by arrow Y so that the order becomes 2 frames. When the offset between the write frame memory and the read frame memory becomes 2 frames, the read clock signal
The frequency f ₀ of R _CK will increase and return to the original frequency. In reality, the frequency f ₀ of R CK will be increased and returned to the original frequency. In reality, the frequency _{f 0} of R _CK will increase and return to the original frequency. The distance between the write frame memory and the read frame memory is increased, and the offset between the write frame memory and the read frame memory becomes a value slightly larger than one frame.

Note that the reason why the frequency _f0 of the read clock signal _RCK is gradually decreased or increased is to avoid sudden frequency changes.
This is to reduce deterioration in sound quality, particularly deterioration due to sampling frequency fluctuations, when demodulating into an analog audio signal. Therefore, it is desirable to control the frequency of the read clock signal for as long as possible within the dummy data transmission period with minute frequency changes. For this purpose, the lower limit frequency _f3 of the read clock signal _RCK may be reduced.

In FIG. 4, frequency _f2 indicates the original transmission clock signal frequency before time division multiplexing on the transmitting side.

Next, an example of the read clock frequency control circuit 19 and the read/write relative address detection circuit 20 will be explained with reference to FIGS. 2 and 3.

The read clock frequency control circuit 19 is
The write clock signal W _CK is generated by the variable frequency divider 19-2 at the frequency division ratio stored in the ROM 19-1.
The write clock signal frequency-divided by the variable frequency divider 19-2 is counted by the address counter 19-3 to designate the read address of the ROM 19-4. The ROM 19-4 stores the data of the sine wave signal at each point in time when the period of the sine wave signal is divided, and is read out by address designation by the address counter 19-3, and the read data is sent to the D/A converter 19. -5 to convert it into an analog signal. Therefore, the signal output from the D/A converter 19-5 is a sine wave signal, and its frequency is determined by the division ratio in the variable frequency divider 19-2, that is, the division ratio data stored in the ROM 19-1. dependent.

The output of the frequency dividing circuit 18 and the output of the D/A converter 19-5 are frequency synthesized in a frequency synthesizer 19-6. The frequency synthesis in the frequency synthesizer 19-6 is sin(x-y) when the inputs are sin x and sin y.
The output signal frequency is configured to be the input signal frequency as shown in FIG. can.

On the other hand, the read clock frequency control logic circuit 19-7 receives the detection output _DMF of the dummy flag bit detection circuit 13 and outputs the signal from the read/write relative address detection circuit 20 to the first frame memory.
Address designation of the ROM _19-1 is started from the time when the signal WMF1 indicating the start of writing to _MF1 is received, and variable frequency division is performed. Also, the frequency synthesizer 19
-6 when the output signal frequency reaches f ₃ ROM1
9-1's addressing remains in that state. Therefore, the frequency f ₀ of the read clock signal R _CK
is gradually decreased from frequency f ₁ to f ₃ and kept constant at frequency f ₃ . Also, by receiving the carry output W _OF supplied from the read/write relative address detection circuit 20, the
Addressing of the ROM 19-1 is started, and the output signal frequency is increased little by little from frequency _f3 to frequency _f1 .

The read/write relative address detection circuit 20 receives the frame memory number signal WF output from the write address counter 16 and uses the write frame detector 20-1 to detect the first frame memory.
It is detected that writing to MF ₁ has started, and the flip-flop 20-3 is set based on this detection output. Also, read address counter 21
The lead frame detector 20-2 receives the frame memory number signal RF output from the frame memory number signal RF.
It is detected that reading from frame memory _MF1 has started, and the flip-flop 20-3 is reset by this detection output. The Q output of the flip-flop 20-3 causes the AND gate 20-
By controlling the gate No. 4 to open, the output fw/N from the frequency dividing circuit 18 is sent to the counter 20- for two frames.
Counter 20 for 2 frames
-5 carry output W _pf is obtained.

Therefore, whether there is a two-frame offset between the time when the first frame memory MF ₁ enters the write state and the time when it enters the read state is determined between times t ₂ and t ₄ in FIG. is checked many times, and when a two-frame offset exists, a carry output W _OF is generated. This carry output
From the time W _OF occurs, the frequency of the read clock signal _RCK is increased as described above.

In the embodiment of the present invention described above, the frequency _f0 of the read clock signal _RCK is controlled in a trapezoidal shape, but the frequency f0 is not limited to a trapezoidal shape, and may be controlled in a stepwise or triangular shape. good.

In addition, the memory block 17 is equipped with four frame memories, and the frequency f ₀ of the read clock signal _RCK is
The case where Tmin>T is shown as an example where the control is completed from the detection of the dummy flag bit to the time before the detection of the next dummy flag bit. In this case, a minimum of three frame memories are installed in the memory block 17. You just have to be prepared.

Further, by further increasing the number of frame memories, the frequency control period T can extend over a plurality of dummy flag bit detection periods so that x·Tmin>T (in this case, x≧2 or more integer). For example, if the number of frame memories is “6”, 4×
It becomes possible to control the frequency of the read clock signal _RCK in the frequency control period T such that Tmin>T, and the change in the frequency of the read clock signal can be made smaller. 4×Tmin in Fig. 7b
A case where >T>3×Tmin will be schematically illustrated.

Note that FIG. 7a shows the timing of detection of the dummy flag bit, and FIG. 7c shows the case described above in one embodiment of the present invention rewritten for comparison.

In addition, in this case where the number of frame memories is "6", if the change in the read clock signal frequency f ₀ is the same as in the case of FIG. 7 c, as shown in FIG. 7 d, the frequency fluctuation of the read clock signal frequency f ₀ The width can also be made smaller.

(Effects of the Invention) As explained above, according to the present invention, after detecting a dummy flag bit, writing to the frame buffer memory is stopped during the dummy data reception period, and then the read clock signal frequency is lowered. When the read/write relative address of the firmware memory returns to its original value by the amount shortened during the dummy data reception period, stable write/read operations are enabled by returning the read clock signal frequency to the original frequency, and the sending side Continuous data before time division multiplexing is obtained. In addition, by increasing the capacity of the frame buffer memory, the readout clock signal frequency can be lowered.
The rising motion can be made gentler or the fluctuation range can be made smaller, and the quality deterioration (sampling frequency fluctuation) of demodulated audio can be reduced. Furthermore, since the read clock signal frequency is determined by the amount of delay from data writing to data reading, stable operation is possible against fluctuations in the transmission clock signal frequency and drifts of the frequency control circuit elements.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing an example of the configuration of a read clock frequency control circuit used in one embodiment of the present invention. FIG. 3 is a block diagram showing an example of the configuration of a read/write relative address detection circuit used in an embodiment of the present invention. FIG. 4 is a diagram showing the frequency change of the read clock signal in one embodiment of the present invention. FIGS. 5 and 6 are schematic diagrams showing the timing of writing to and reading from the frame memory in an embodiment of the present invention. FIG. 7 is a diagram showing frequency changes of a read clock signal for explaining a modification of an embodiment of the present invention. FIG. 8 is a schematic diagram showing an example of a frame configuration after time division multiplexing. 11... Frame synchronization signal detection circuit, 12...
Write clock signal regeneration circuit, 13...Dummy flag bit detection circuit, 14...Channel selection instruction switch, 15...System timing generation circuit, 16...Write address counter, 17
... Memory block, 17-1 ... Frame buffer memory, 17-2, 17-4 ... Frame memory selection switch, 17-3 ... Input selection switch, 18 ... Frequency division circuit, 19 ... Readout clock Frequency control circuit, 19-1, 19-4...
ROM, 19-2...Variable frequency divider, 19-3...
Address counter, 19-5...D/A converter,
19-6...Frequency synthesizer, 19-7...Read clock frequency control logic circuit, 20...Read/write relative address detection circuit, 20-1...
...Light frame detector, 20-2...Lead frame detector, 20-3...Flip-flop,
20-4...AND gate, 20-5...2 frame counter, 21...Read address counter, M...time division multiplex signal separation device main unit (decoder), _MF1 to _MF4 ...frame memory.

Claims (1)

[Scope of Claims] 1. In order to combine N frames of channels having different sampling frequencies or clock signal frequencies and transmitted as frames into a unit of multiplexed frame, the sampling frequency or clock signal frequency is adjusted. Time-division multiplexing is performed using a reference clock signal obtained by multiplying the highest frequency or a frequency higher than the highest frequency by N, and inserts a dummy signal and a dummy flag bit in pairs in channels where the information signal is insufficient to constitute a channel frame. This is a time division multiplex signal separation method that receives a time division multiplex signal transmitted as a signal and separates it into the original signal, and the delay between the write frame and read frame of the information signal is (α + βx) frames ≧
A frame buffer memory is provided on the time division multiplexing/demultiplexing side, which can take a real number of 0, an integer of x≧1, and β is a value whose unit is the amount of information sent in one frame, and β>0, and can be used for writing and reading. The relationship is set in the frame buffer memory so that the amount of delay between the write frame and the read frame is (α + βx), and when a dummy flag bit is detected in the incoming information signal, the dummy flag bit is detected. Each time, writing to the frame buffer memory is stopped for β frames, then the read clock signal frequency is lowered, and when the difference between the write frame and the read frame in the frame buffer memory returns to more than β frames, the read clock signal frequency is decreased. A time division multiplex signal separation method characterized in that the information signal before continuous time division multiplexing is restored by controlling the read clock back to the original frequency. 2. The method according to claim 1, wherein the difference between the write frame and the read frame at the start of returning the read clock signal frequency to the original frequency is a preset constant value of β frame or more. Time division multiplexing signal separation method. 3. A patent claim characterized in that when the read clock signal frequency is lowered to a predetermined frequency and the difference between the write frame and the read frame returns to a β frame or more, the read clock signal frequency is sequentially increased from the predetermined frequency. The time-division multiplexing signal separation method according to the first or second range.