JPH0369463B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention is a method for detecting multiplexed signals obtained by time-division multiplexing a plurality of digital or analog information signals having different sampling frequencies or clock signal frequencies. The present invention relates to a time division multiplexing signal separation method for separating original information signals.

(Background of the Invention) In the time-division multiplexing signal separation method as described above, N-channel information signals having different sampling frequencies or clock signal frequencies are separated from each other at the highest frequency of the sampling frequency or clock signal frequency, or at the highest frequency. Time division multiplexing is performed using a reference clock signal obtained by multiplying the above frequency by N, and a dummy signal is sent to the part where the information signal is insufficient.After detecting the dummy data on the receiving side, the dummy signal is not written to the storage device and the reading frequency is changed. proposed a time-division multiplexing signal separation method that separates the signal into the original information signal (patent application 1986-
114355).

In this time-division multiplexing signal separation method, when a dummy flag bit inserted in a pair with a dummy signal is detected, the read clock frequency control of the storage device writes an inter-frame information signal (corresponding to the dummy signal) to the storage device. First, the write address counter is held without being incremented. At the same time, the read clock frequency of the storage device is lowered to return to the relative address relationship before the read/write relative address detection circuit started the read clock frequency control, and then the read clock frequency control of the storage device is ended.

(Problems to be Solved by the Invention) In the conventional time division multiplexing system as described above, when a dummy flag bit is generated on the time division multiplexing side, a data error occurs in the transmission system and/or the time division multiplexing system. However, if the dummy flag bit is inverted, a malfunction will occur.
An example of this is as follows. Even though no dummy flag bits are output on the time division multiplexing side, dummy flag bits (pseudo dummy flag bits) are mistakenly detected on the time division multiplexing/demultiplexing side, or conversely, dummy flag bits are output on the time division multiplexing side. However, there are cases where the time division multiplexing and demultiplexing side cannot be detected.

In other words, if a pseudo dummy flag bit occurs during read clock frequency control and read clock frequency control is restarted, the read address will overtake the write address of the storage device and the read and write operations of the storage device will continue for a long period of time. Due to the overlapping, long burst errors occur, it takes a long time to restore correct memory operation, and there are problems in that long shock noise occurs when demodulating.

Additionally, if a pseudo dummy flag bit is generated while read clock frequency control is stopped and read clock frequency control is started, writing to the storage device will be stopped, resulting in one frame of read data being lost, resulting in demodulation. There is a problem that waveform distortion occurs.

SUMMARY OF THE INVENTION An object of the present invention is to minimize the above-mentioned problems and provide a time division multiplex signal separation system that reduces the occurrence of shocks.

(Means for Solving the Problems) The present invention provides N-channel information signals having mutually different sampling frequencies or clock signal frequencies at the highest frequency of the sampling frequency or clock signal frequency, or at a frequency higher than the highest frequency. A dummy flag bit detection circuit detects a dummy flag by receiving a time-division multiplexed signal obtained by time-division multiplexing with a reference clock signal multiplied by N and inserting a dummy flag and a subsequent dummy signal in the portion where the information signal is insufficient. a write address counter that specifies a write address to a storage device that stores an information signal and stops counting when a dummy flag bit is detected; a read address counter that specifies a read address to the storage device; a read clock frequency control circuit that temporarily reduces the read clock frequency supplied to the read address counter when a dummy flag is detected; In the time division multiplexed signal separation method in which the clock frequency is read out and restored to the original signal, the read clock frequency control circuit outputs a clock frequency control state signal to the dummy flag bit detection circuit while reducing the clock frequency, Generation of detection output is now prohibited.

(Function) In the present invention configured as described above, detection of dummy data is stopped during read clock frequency control, so even if an error occurs in the dummy flag bit and a pseudo dummy flag bit occurs, a pseudo dummy flag bit is detected. The dummy flag bit prevents read clock frequency control from starting again.

(Example of the invention) The present invention will be explained below with reference to Examples.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention.

In this example, for example, the audio subcarrier of satellite broadcasting is QPSK demodulated, and the resulting 2048 Mbit/
s bitstream is converted to N by the method described above.
(=4) The case where multiplexed signals in the case of channel multiplexing are separated is illustrated.

The frame structure of this bitstream is
As shown in the figure. That is, 16-bit frame synchronization data, 8-bit dummy information, 2032-bit A channel information signal, 8-bit dummy information, 2032-bit B channel information signal, 8-bit dummy information, and 2032-bit C channel information. A unit frame string is formed by the signal, 8-bit dummy information, 2032-bit D channel information signal, and 16 remaining bits. The dummy information before the information signal of each channel includes a dummy flag bit indicating whether the information signal of the following channel is dummy data or not.
By checking this dummy flag bit, it is determined whether the information signal of the following channel is dummy data or not.

A time division multiplexed signal obtained by the above-described time division multiplexing method is input to the input terminal 10. In this embodiment, a bit stream of 4×2048 Mbit/s is input to the input terminal 10.

This bit stream is transmitted to the frame synchronization signal detection circuit 11 and the write clock signal regeneration circuit 1.
The frame synchronization signal detection circuit 11 detects the frame synchronization signal, and the clock signal regeneration circuit 12 reproduces the write clock signal _WCK . Further, the bit stream and write clock signal _WCK are supplied to a dummy flag bit detection circuit 13, which detects the dummy flag bit in the dummy information and determines whether the information signal of the following channel is dummy data or not. When it is determined that this is the case, a prohibition instruction signal that prohibits counting by the write address counter 16, which will be described later.
Output W _INH .

Frame synchronization signal, write clock signal
W _CK , the output of the channel selection instruction switch 14 for selecting a reception channel, and a read clock signal R _CK to be described later are supplied to the system timing generation circuit 15 .
A timing signal necessary for a decoding operation by a time division multiplex signal demultiplexing device (hereinafter also referred to as a decoder) main body M is generated from the time division multiplex signal demultiplexing device (hereinafter also referred to as a decoder).

On the other hand, in this embodiment, a buffer frame memory 1 having a configuration of 4 frame memories (MF ₁ to _{MF 4} ) is used.
7-1 and frame memory selection switch 17-2
and 17-4, and an input selection switch 17-4 that supplies the information signal of the channel selected by the channel selection instruction switch 14 from the bit stream to the frame memory changeover switch 17-2.
A memory block 17 consisting of 3 is provided.
Here, the one frame memory is set to have a capacity that can store the amount of data sent for one frame (2032 bits in this example).

The write clock signal _WCK is supplied to the write address counter 16 to generate the write address signal.
A frame memory number signal WF corresponding to WA and the write frame memory number is generated. The write address signal WA is supplied to the memory block 17 to designate a write address, and the frame memory number signal WF controls the changeover switch 17-2 to select a write frame. On the other hand, the inhibition instruction signal _INH is also input to the write address counter 1.
6, the progress of the address signal is stopped by the inhibition instruction signal _INH , and the memory block 17 is
The write operation for one frame memory is prohibited.

The write clock signal _WCK is also passed through the frequency divider circuit 18.
The frequency of the clock signal is divided by 1/N of the frequency of the transmission clock signal after time division multiplexing (=f ₁ ). The output signal of the frequency divider circuit 18 is supplied to a read clock frequency control circuit 19, which generates a read clock signal _RCK having a frequency _f0 . The read clock frequency control circuit 19 includes a dummy flag bit detection circuit 1.
Writing to a specific frame memory of the memory block 17, for example, the first frame memory MF1, after the dummy flag is detected by receiving the dummy flag bit detection output _DMF when the dummy flag bit is detected by 3 and the output of the frequency dividing circuit ₁₈ . From time to time, the read clock signal frequency _f0 gradually decreases from frequency _f1 to frequency _f3 , and the first frame memory
The frequency is increased from frequency f ₃ to frequency f _{1 by the output of the read/write relative address detection circuit 20 which detects a difference of, for example, two frames between addresses written in MF 1 and} read from the first frame memory MF ₁ . It is configured to do so.

Furthermore, during the read clock frequency control described above, the read clock frequency control circuit 19
The clock frequency control state signal STATE is supplied to the dummy flag bit detection circuit 13 to inhibit the operation of the dummy flag bit detection circuit 13.

The read clock signal _RCK is supplied to a read address counter 21, which generates a read address signal RA and a frame memory number signal RF corresponding to the read frame memory number. Read address signal
RA is supplied to memory block 17 to designate a read address, and frame memory number signal RF controls changeover switch 17-4 to select a read frame.

A multiplexed transmission clock signal, that is, a write clock signal _WCK , and a frame synchronization signal are detected from the bit stream supplied to the input terminal 10, and frame synchronization is performed.

In addition, a timing signal from the system timing generation circuit 15 causes a delay of one frame to be provided between the write frame memory and the read frame memory when the power is turned on and when the selected channel is switched by the channel selection instruction switch 14. Switches 17-2 and 17-4 are initialized so as to have an offset of two frames, with one frame existing between the write frame memory and the read frame memory.

On the other hand, the address signal WA from the write address counter 16 and the read address counter 2
The address signal RA from 1 is supplied to the address counter relative difference detection circuit 22, which detects the read/write address counter relative difference before the read address and write address overlap, and uses the address relative difference detection signal _INT to Write address counter 16 and read address counter 2
It is set to initialize to 1.

Assume that the B channel is currently selected by the channel selection instruction switch 14, and that the sampling frequency or clock signal frequency of the B channel is lower than that of the other channels before multiplexing on the transmitting side.

After frame synchronization is achieved, the B channel information signal is extracted from the bit stream via the input selection switch 17-3 according to the timing signal from the system timing generation circuit 15, and the information signal of the B channel is extracted from the bit stream by the frame memory number signal WF.
By switching 7-2, the information signal for one channel is sequentially supplied to one frame memory, and the information signal for one channel is sequentially supplied to the frame memory in synchronization with the write clock signal _WCK .
They are sequentially written to MF ₁ , MF ₂ , ...MF ₄ , MF ₁ , ....

On the other hand, the write clock signal _WCK is output from the frequency divider circuit 1.
8, and the read clock frequency control circuit 19 outputs a read clock signal _RCK having a frequency f ₁ (=fw/4). Also,
The frame changeover switch 17-4 is switched by the frame memory number signal RF with a delay of two frames relative to the write frame memory and in synchronization with the read clock signal _RCK , so that the frame memories MF ₁ , . . . MF ₄ The information signal of the B channel stored from , ... is 1/ at the time of writing.
The data are sequentially read out by a read clock signal _RCK having a frequency of 4.

However, it is now assumed that dummy data DU is inserted in the 100th B channel. Therefore, a dummy flag bit indicating that the next information signal is dummy data is set in the dummy information immediately before the B channel in the 100th frame row, and this dummy flag bit is detected by the dummy flag bit detection circuit. 13, and an inhibition instruction signal _INH is output.
FIG. 3 shows the frequency variation of the read clock signal _RCK . In FIG. 3, DU schematically shows the detection of the dummy flag bit, and the time at which the dummy flag bit is detected is shown as t ₁ (t ₆ , t ₁₁ ). When this dummy flag bit is detected, an inhibition instruction signal _INH is output, and writing of one frame's worth of B channel information signals (dummy data in this case) is stopped. Also,
The inhibition instruction signal W _INH is output, the count value of the write address counter 16 is stopped for one frame, and the information of the B channel next to the dummy data is written on the one frame memory where the dummy data was temporarily stored, and the actual Writing of one frame's worth of B channel information signals (dummy data in this case) may be substantially prohibited. Therefore, the data written to the frame memory is only the B channel information signal excluding dummy data. However, during this time, reading is performed in synchronization with the read clock signal _RCK of the same frequency _f1 . As a result, the interval between the read frame memory and the write frame memory becomes close, and when writing is resumed, the read frame memory becomes the next frame of the write frame memory. Even in this state, writing to each frame memory MF ₁ , . . . MF ₄ . . . is performed sequentially. During this period, the read clock frequency control circuit 19 determines when the first frame memory MF ₁ is written for the first time after the dummy flag bit is detected (times t ₂ and t ₇ ).
From times _t2 and _t7 , the frequency _f0 of the read clock signal _RCK is gradually lowered from the frequency _f1 to the frequency _f3 , and is temporarily maintained at the frequency _f3 . Third
In the figure, the times at which the frequency of the read clock signal _RCK matches the frequency _f3 are indicated by _t3 and _t8 .

On the other hand, during the period when the frequency _f0 of the read clock signal _RCK is decreased from the frequency _f1 to the frequency _f3 and during the period when the frequency _f3 is maintained,
The write frame memory is the first frame memory
After becoming MF ₁ , the frequency (fw/N) of the frequency dividing circuit 18 is counted during the period until the read frame memory becomes the first frame memory MF ₁ , and whether the counted value has reached a value equivalent to 2 frames or not. The read/write relative address detection circuit 20 determines whether or not the read/write relative address is detected. As a result of this determination, when the count value reaches a value corresponding to two frames (times _t4 , _t9 ), the frequency of the read clock signal _RCK is gradually returned from frequency _f3 to frequency _f1 . In this state, when the frequency f ₀ of the read clock signal R _CK matches the frequency f ₁ (times t ₅ and t ₁₀ ), the frequency is maintained at f ₁ and waits for the next dummy flag bit to be detected. .

Note that the reason why the frequency _f0 of the read clock signal _RCK is gradually decreased or increased is to avoid sudden frequency changes.
This is to reduce deterioration in sound quality, particularly deterioration due to sampling frequency fluctuations, when demodulating into an analog audio signal. Therefore, it is desirable to control the frequency of the read clock signal for as long as possible within the dummy data transmission period with minute frequency changes. For this purpose, the lower limit frequency _f3 of the read clock signal _RCK may be reduced.

In FIG. 3, frequency _f2 indicates the original transmission clock signal frequency before time division multiplexing on the transmitting side.

When operating as described above, a data error occurs in the transmission system and/or demodulation system,
The dummy flag bit detection circuit 13 outputs a dummy flag detection output _DMF . When the read clock frequency control circuit 19 receiving this dummy flag detection output _DMF is controlling the read clock frequency, the clock frequency control status signal STATE is output to the dummy flag detection circuit 13, and the dummy flag detection circuit 13 prohibits the clock frequency control. Generation of instruction signal _INH and dummy flag detection output _DMF is prohibited. Therefore, no further dummy flag bit detection output is generated during read clock frequency control, and the occurrence of long burst errors is suppressed.

On the other hand, the read/write address counter relative difference detection circuit 22 detects the relative difference between the write address signal WA and the read address signal RA. When , the address difference detection signal from the read/write address counter relative difference detection circuit 22
The write address counter 16 and the read address counter 21 are initialized by AD _INT . As a result, the occurrence of long burst errors can be avoided.

Furthermore, if the dummy flag bit is missing and the read clock frequency cannot be controlled, a dummy signal will be written to the frame memory 17-1. Furthermore, if the read clock frequency cannot be controlled, dummy data will be output as read data from the frame memory 17-1, and shock noise will occur during demodulation. In this case, if you give the PN signal (generator polynomial G(x) = x ¹⁰ + x ³ + 1) as dummy data,
Even if the dummy data is demodulated, it will be at zero level, so shock noise can be avoided.

(Effects of the Invention) As explained above, according to the present invention, the dummy flag bit is inverted in the transmission system or the demodulation system,
Even if a pseudo dummy flag bit occurs, during read clock frequency control, even if a new dummy flag bit is detected, read clock frequency control based on the detection of that dummy flag bit is prohibited, ensuring stable readout. Clock frequency control can be performed, which has the effect of suppressing the occurrence of burst errors.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a schematic diagram showing an example of a frame configuration after time division multiplexing. FIG. 3 is a diagram showing the frequency change of the read clock signal in one embodiment of the present invention. 11... Frame synchronization signal detection circuit, 12...
Write clock signal regeneration circuit, 13...Dummy flag bit detection circuit, 14...Channel selection instruction switch, 15...System timing generation circuit, 16...Write address counter, 17
-1...Frame buffer memory, 17-2 and 17-4...Frame memory changeover switch, 1
7-3... Input selection switch, 18... Frequency divider circuit, 19... Readout clock frequency control circuit,
20...Read/write relative address detection circuit,
21...Read address counter, 22...Address counter relative difference detection circuit.

Claims (1)

[Claims] 1. Time-division multiplexing of N channels of information signals having mutually different sampling frequencies or clock signal frequencies with a reference clock signal obtained by multiplying the highest frequency of the sampling frequency or clock signal frequency, or a frequency equal to or higher than the highest frequency by N, A dummy flag bit detection circuit receives a time division multiplexed signal in which a dummy flag and a subsequent dummy signal are inserted in the portion where the information signal is insufficient, and a dummy flag bit detection circuit detects the dummy flag, and a write address is sent to the storage device that stores the information signal. a write address counter that stops counting when a dummy flag bit is detected, a read address counter that specifies a read address to the storage device, and a dummy flag that is supplied to the read address counter when a dummy flag is detected. a readout clock frequency control circuit that temporarily reduces a readout clock frequency, and reads out an information signal stored in the storage device according to address designation by the readout address counter and restores the information signal to the original signal. In the separate method, the read clock frequency control circuit outputs a clock frequency control status signal to the dummy flag bit detection circuit while reducing the clock frequency, thereby inhibiting generation of the dummy flag detection output. Division multiplexing signal separation method.