JPH0328055B2 - - Google Patents
Info
- Publication number
- JPH0328055B2 JPH0328055B2 JP56096259A JP9625981A JPH0328055B2 JP H0328055 B2 JPH0328055 B2 JP H0328055B2 JP 56096259 A JP56096259 A JP 56096259A JP 9625981 A JP9625981 A JP 9625981A JP H0328055 B2 JPH0328055 B2 JP H0328055B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor
- interface
- gaas
- mis
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
Landscapes
- Formation Of Insulating Films (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Description
【発明の詳細な説明】
本発明は界面準位密度の少ない良好MIS（Me−
tal−Insulator−Semiconductor）特性を示す
−化合物半導体装置に関する。Detailed Description of the Invention The present invention provides a good MIS (Me-
tal-Insulator-Semiconductor) characteristics - relates to a compound semiconductor device.
−化合物半導体への絶縁膜形成技術は、高
速動作可能なｎチヤネル絶縁ゲート型電界効果ト
ランジスタ（MISFET）の実現や、半導体装置
の表面安定化にとつてきわめて重要であり、現在
までに−化合物自体の酸化膜を形成する方法
（陽極酸化法、プラズマ酸化法、熱酸化法）や被
着法によつて絶縁膜を形成する方法（化学気相成
長法、スパツタリング法などによる酸化ケイ素
膜、窒化ケイ素膜、酸化アルミニウム膜の形成）
が試みられてきた。しかしながら、たとえば−
化合物として砒化ガリウム（GaAs）に対して
は、これらのいずれの方法においても界面準位密
度は1011〜1012cm-2ときわめて大きな値に達し、
しかもそのMIS特性は周波数分散が大きく良好な
特性を得るに至つていない。この理由は、−
化合物では、族元素そのものおよび族元素の
酸化物の蒸気圧が高く、酸化法では酸化膜自体に
おいても化学量論比を持つた酸化膜が得られない
こと、また−化合物表面においても、族元
素が欠乏した欠陥が形成され化学量論比が得られ
難く界面に高密度の不対結合（ダングリングボン
ド）および欠陥準位が形成されるためと考えられ
る。 - Insulating film formation technology on compound semiconductors is extremely important for realizing high-speed n-channel insulated gate field effect transistors (MISFETs) and for stabilizing the surface of semiconductor devices. Methods for forming oxide films (anodic oxidation method, plasma oxidation method, thermal oxidation method) and methods for forming insulating films by deposition methods (silicon oxide film, silicon nitride film by chemical vapor deposition method, sputtering method, etc.) (formation of aluminum oxide film)
has been attempted. However, for example -
For gallium arsenide (GaAs) as a compound, the interface state density reaches an extremely large value of 10 11 to 10 12 cm -2 in any of these methods.
Moreover, the MIS characteristics have large frequency dispersion and have not yet achieved good characteristics. The reason for this is −
In compounds, the vapor pressure of group elements themselves and oxides of group elements is high, and oxidation methods cannot produce oxide films with stoichiometric ratios even on the surface of compounds. This is thought to be because defects lacking in ions are formed, making it difficult to obtain a stoichiometric ratio, resulting in the formation of a high density of dangling bonds and defect levels at the interface.
本発明の目的は、従来のこれらの欠点を解決
し、界面準位密度のきわめて少ないMIS構造をも
つた半導体装置を提供することにある。 An object of the present invention is to solve these conventional drawbacks and provide a semiconductor device having an MIS structure with extremely low interface state density.
本発明によれば、−化合物半導体からなる
表面組成をもつ半導体基板に接して該半導体とは
異なつた材料でかつ１ないし５原子層の膜厚をも
つ半導体層を設け、該半導体層に接して絶縁膜を
設けたことを特徴とする半導体装置が得られる。 According to the present invention, - a semiconductor layer made of a material different from the semiconductor and having a thickness of 1 to 5 atomic layers is provided in contact with a semiconductor substrate having a surface composition consisting of a compound semiconductor; A semiconductor device characterized in that an insulating film is provided is obtained.
以下、本発明を図を用いて説明する。 Hereinafter, the present invention will be explained using figures.
図は本発明の一実施例を示す断面図で、１は
GaAs基板、２は少なくとも１原子層以上の厚さ
で多くとも５原子層以下の厚さのシリコン（Si）
膜、３は酸化シリコンよりなる絶縁膜、４はアル
ミニウムよりなる金属膜である。本発明の構造の
MISダイオードが従来のものと異なる点は２のSi
膜がGaAs基板１と酸化シリコン膜３の間に挿入
されているところにある。従来の構造のMISダイ
オードでは、酸化ケイ素膜形成時に、族元素が
抜けた欠陥が形成され、界面に高密度の深い準位
が形成されたり、あるいは酸化ケイ素膜形成時
に、GaAs表面が非化学量論比で酸化され、界面
に高密度の不対結合が形成されるため、界面準位
密度の少ない、良好なMIS特性は得られなかつ
た。本発明では、極めて薄いSi膜を被着した後
SiO2膜が形成されている。GaAsとSiの格子常数
のずれは約４％であり、被着されるSi膜２の厚さ
が５原子層を越えるとGaAs基板１とSi膜２の界
面に不対結合が形成され界面準位が発生するが、
５原子層以下の厚さでは、Siの格子が歪むことに
より、界面には不対結合は形成されない。またSi
膜２とSiO2膜３との間では、良好な界面が得ら
れ、1011cm-2以下の低い界面準位密度が実現す
る。したがつて本発明の構造のMISダイオードで
は絶縁膜と半導体間の界面準位密度は1011cm-2以
下のきわめて良好な界面が実現する。本発明でSi
膜２の厚さを１〜５原子層にかぎつた理由の第１
は前述したようにGaAs基板１とSi膜２の界面に
結晶欠陥の生成を避けるためであるが、第２に
は、GaAs基板１の表面の欠陥形成を防ぐために
は、少なくとも１原子層以上のSi膜２で覆う必要
があり、かつ５原子層以上では、GaAsのMIS構
造というよりむしろSiのMOS構造となつてしま
いGaAsMISのもつ優れた特性が発揮できないた
め５原子層以下の膜厚に限定されたものである。
本発明の実施例は具体的には、到達真空度が１×
10-9Torr以下の超高真空装置内での分子線エピ
タキシヤル成長装置で製造される。すなわち、ｐ
型もしくは高抵抗GaAs基板上にｐ型もしくは高
抵抗GaAsを分子線エピタキシヤル法で形成さ
れ、次いで１〜５原子層の厚さのシリコン膜２が
形成され、さらに低圧化学気相成長法もしくはイ
オンビーム法、もしくは蒸着法もしくはプラズマ
化学気相成長法により酸化シリコン膜３が形成さ
れ、さらに蒸着法によりアルミニウムが形成され
る。 The figure is a sectional view showing one embodiment of the present invention, and 1 is a sectional view showing an embodiment of the present invention.
GaAs substrate, 2 is silicon (Si) with a thickness of at least 1 atomic layer or more and at most 5 atomic layers or less
The film 3 is an insulating film made of silicon oxide, and 4 is a metal film made of aluminum. The structure of the present invention
The difference between MIS diodes and conventional ones is the 2nd Si
The film is inserted between the GaAs substrate 1 and the silicon oxide film 3. In a MIS diode with a conventional structure, when a silicon oxide film is formed, defects are formed where group elements are missing, and a high-density deep level is formed at the interface, or when a silicon oxide film is formed, the GaAs surface has a non-stoichiometric content. Since it is oxidized at a stoichiometric ratio and a high density of unpaired bonds is formed at the interface, good MIS characteristics with a low density of interface states could not be obtained. In the present invention, after depositing an extremely thin Si film,
A SiO 2 film is formed. The difference in lattice constant between GaAs and Si is about 4%, and when the thickness of the deposited Si film 2 exceeds 5 atomic layers, dangling bonds are formed at the interface between the GaAs substrate 1 and the Si film 2, resulting in an interface quasi. However,
When the thickness is less than 5 atomic layers, the Si lattice is distorted and no dangling bonds are formed at the interface. Also, Si
A good interface is obtained between the film 2 and the SiO 2 film 3, and a low interface state density of 10 11 cm -2 or less is achieved. Therefore, in the MIS diode having the structure of the present invention, an extremely good interface with an interface state density of 10 11 cm -2 or less between the insulating film and the semiconductor is realized. In the present invention, Si
The first reason for limiting the thickness of film 2 to 1 to 5 atomic layers
As mentioned above, this is to avoid the formation of crystal defects at the interface between the GaAs substrate 1 and the Si film 2. Secondly, in order to prevent the formation of defects on the surface of the GaAs substrate 1, it is necessary to It needs to be covered with a Si film 2, and if it is more than 5 atomic layers, it becomes a Si MOS structure rather than a GaAs MIS structure, and the excellent characteristics of GaAs MIS cannot be exhibited, so the film thickness is limited to 5 atomic layers or less. It is what was done.
Specifically, in the embodiment of the present invention, the ultimate vacuum degree is 1×
Manufactured using molecular beam epitaxial growth equipment in an ultra-high vacuum equipment below 10 -9 Torr. That is, p
P-type or high-resistance GaAs is formed on a mold or high-resistance GaAs substrate by molecular beam epitaxial method, then a silicon film 2 with a thickness of 1 to 5 atomic layers is formed, and then low-pressure chemical vapor deposition or ion deposition is performed. A silicon oxide film 3 is formed by a beam method, an evaporation method, or a plasma chemical vapor deposition method, and aluminum is further formed by an evaporation method.
本発明の実施例では、１〜５原子層の厚さの半
導体材料としてシリコンを用いたが、他の半導体
材料でもよい。たとえばゲルマニウムを用いた場
合には、GaAs基板１との格子常数のずれがきわ
めて小さいためGaAs基板１と半導体薄膜２の間
の界面はきわめてよい利点がある。またインジウ
ム燐を用いた場合には、SiO2膜３を被着したと
きにインジウム燐に欠陥が導入されるにもかかわ
らず、欠陥の準位が伝導帯にきわめて近いところ
に形成されるため、MIS特性としては良好なもの
が得られる。インジウム砒素、インジウム砒素・
リン混晶、インジウム・ガリウム燐混晶、インジ
ウム・アルミニウム・燐混晶を用いた場合にも、
インジウム燐と同様な効果が得られる。また半導
体基板１としては実施例ではGaAsを用いたが、
インジウム燐に対してもシリコンあるいはゲルマ
ニウム、ガリウム砒素、アルミニウム・ガリウ
ム・砒素等の１〜５原子層厚の半導体薄膜２の形
成により、MIS特性は改善される。基板材料１と
してはインジウム燐の外、インジウム・砒素・燐
混晶、ガリウム燐・ガリウム砒素・燐、インジウ
ムアンチモン等を含むすべての−化合物に対
して、本発明の構造は有効である。実施例では、
絶縁膜３はSiO2を用いているが、他の絶縁膜材
料たとえば窒化シリコン・窒化ゲルマニウム、酸
化アルミニウムを用いても有効であることはいう
までもない。また金属膜４材料としても、絶縁膜
３と反応性の低い金属であれば、何でもよく、さ
らに述べれば導電性をもつものなら金属でなくて
もよい。−化合物装置の表面安定化の目的で
あれば、金属膜４は除去される。 In the embodiments of the present invention, silicon is used as the semiconductor material with a thickness of 1 to 5 atomic layers, but other semiconductor materials may be used. For example, when germanium is used, there is an advantage that the interface between the GaAs substrate 1 and the semiconductor thin film 2 is extremely good because the deviation in lattice constant from the GaAs substrate 1 is extremely small. Furthermore, when indium phosphorus is used, although defects are introduced into indium phosphorus when the SiO 2 film 3 is deposited, the level of the defects is formed very close to the conduction band. Good MIS characteristics can be obtained. Indium arsenide, indium arsenide・
Even when using phosphorus mixed crystal, indium-gallium-phosphorus mixed crystal, and indium-aluminum-phosphorus mixed crystal,
The same effect as indium phosphorus can be obtained. In addition, although GaAs was used as the semiconductor substrate 1 in the embodiment,
Even for indium phosphorus, the MIS characteristics can be improved by forming a semiconductor thin film 2 of silicon, germanium, gallium arsenide, aluminum, gallium, arsenic, etc. with a thickness of 1 to 5 atomic layers. As the substrate material 1, the structure of the present invention is effective for all -compounds including indium-arsenic-phosphorus mixed crystals, gallium-phosphorus, gallium-arsenic-phosphorus, indium-antimony, etc., in addition to indium-phosphorus. In the example,
Although SiO 2 is used for the insulating film 3, it goes without saying that other insulating film materials such as silicon nitride, germanium nitride, and aluminum oxide are also effective. Further, the material of the metal film 4 may be any metal as long as it has low reactivity with the insulating film 3, and more specifically, it does not need to be a metal as long as it has conductivity. - If the purpose is to stabilize the surface of the compound device, the metal film 4 is removed.
図は本発明の一実施例であるGaAs MISダイ
オードの断面を示し、１はGaAs基板、２は１な
いし５原子層の厚さをもつSi膜、３は酸化シリコ
ン膜、４はアルミニウム膜である。
The figure shows a cross section of a GaAs MIS diode that is an embodiment of the present invention, where 1 is a GaAs substrate, 2 is a Si film with a thickness of 1 to 5 atomic layers, 3 is a silicon oxide film, and 4 is an aluminum film. .
Claims (1)
半導体基板に接して、該半導体とは異つた材料で
かつ１ないし５原子層の膜厚をもつ半導体層を設
け、該半導体層に接して絶縁膜を設けたことを特
徴とする半導体装置。1 - In contact with a semiconductor substrate having a surface composition consisting of a compound semiconductor, a semiconductor layer made of a material different from the semiconductor and having a thickness of 1 to 5 atomic layers is provided, and an insulating film is provided in contact with the semiconductor layer. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56096259A JPS57211238A (en) | 1981-06-22 | 1981-06-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56096259A JPS57211238A (en) | 1981-06-22 | 1981-06-22 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57211238A JPS57211238A (en) | 1982-12-25 |
| JPH0328055B2 true JPH0328055B2 (en) | 1991-04-17 |
Family
ID=14160185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56096259A Granted JPS57211238A (en) | 1981-06-22 | 1981-06-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57211238A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59119869A (en) * | 1982-12-27 | 1984-07-11 | Fujitsu Ltd | Semiconductor device |
| JPS59127839A (en) * | 1983-01-11 | 1984-07-23 | Nec Corp | Inactivation of surface of iv-v group element compound semiconductor |
| JPS59172728A (en) * | 1983-03-22 | 1984-09-29 | Fujitsu Ltd | Semiconductor device |
| JPS63274176A (en) * | 1987-05-06 | 1988-11-11 | Seiko Instr & Electronics Ltd | Insulated gate field effect transistor |
| US4987095A (en) * | 1988-06-15 | 1991-01-22 | International Business Machines Corp. | Method of making unpinned oxide-compound semiconductor structures |
| JP5047486B2 (en) * | 2004-10-13 | 2012-10-10 | アイメック | Manufacturing method of semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5513956A (en) * | 1978-07-17 | 1980-01-31 | Nec Corp | Insulation film forming method for compound semiconductor |
| JPS5846169B2 (en) * | 1979-11-16 | 1983-10-14 | 沖電気工業株式会社 | Oxide film coating manufacturing method for compound semiconductor devices |
-
1981
- 1981-06-22 JP JP56096259A patent/JPS57211238A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57211238A (en) | 1982-12-25 |
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