JPH0328118B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an audible signal tone detection circuit for an audible signal tone generation circuit in a time division digital exchange by periodically reading out a digital code sequence stored in a memory.

Time division digital switching equipment is becoming the most popular switching equipment due to rapid advances in digital communication technology and LSI technology. Furthermore, due to its affinity for digital signals, its scope of application is expanding not only to telephones but also to data terminals and data processing devices. Particularly from the viewpoint of streamlining business communications, it is essential to develop an integrated voice/data exchange that accommodates both telephones and data equipment and exchanges them all at once.

There are various ways to implement such an integrated voice/data switch. For example, it is conceivable to provide advanced functions to the exchange itself using a packet switching method, but it is also possible to achieve this by interconnecting devices with equivalent functions using a circuit switching method. This is because, in this method, the exchange itself becomes extremely simple, and the restrictions on connections with terminals and the like are relaxed.

There are several possible circuit switching methods. The big issue here is how to deal with the differences in terminal types. Particularly problematic is the difference in line control signals between the terminal and the exchange, such as line setting, disconnection, and transmission of selection signals. On the other hand, the method of using different line control signals for each terminal has the disadvantage that the control program for the exchange becomes complicated and requires registration of the type of terminal, which causes inconvenience when changing. On the other hand, if an interface circuit is provided at the input section from the terminal to the exchange, and the line control signals are unified by this interface circuit, so that all terminals appear to be exactly the same from the control section of the exchange, then It is extremely advantageous without the above-mentioned problems. Furthermore, since telephones are considered to be the most common terminal in business communications, a method of unifying the line control signals of each terminal into the line control signal of the telephone is promising.

That is, in the above-mentioned interface circuit, call origination and call termination signals (STX,
ETX) into off-hook and on-hook signals, and converts selection signals from character dials, etc., into dial pulses or push button signals. On the other hand, the exchange sends an audible signal tone (dial tone, busy tone, ringback tone, etc.) to notify the progress status of the call, such as dial reception ready, busy, ringing, etc. In the interface circuit, these signal tones must be converted into ACK, NACK, Ready, Wait, etc. signals for data terminals and the like. Therefore, the interface circuit requires an audible signal tone detection circuit.

However, in the past, these audible signal tones were used for humans to listen to to detect movements and to plan the progress of a call, so there are almost no examples of circuits that can recognize these signals by machines. Good fit.

However, by analogy with the function of detecting a specific frequency in a situation where audio signals are also present, a push-button signal receiver (PBR) is used.
If an audible signal detection circuit is constructed according to the following, it will be as shown in FIG. Note that these audible signal tones are, in principle, signal tones expressed in the form of the sum of sine waves of two frequencies.

In FIG. 1, the digital code word applied to the input terminal 10 is normally a compressed nonlinear code, so it is converted into a linear code by the decompression circuit 11, and then passed through the low-pass filter 12 and the high-frequency code word. area filter 13. These filters are
Both are digital filters, and the cutoff frequency is determined according to the two frequencies contained in the audible signal sound to be detected. For example, 350
In the case of a dial tone consisting of two frequencies, Hz and 440Hz, it is simply the frequency between the two.
With 395 Hz as the boundary, frequency components below this are added to the band filter 14, and frequency components above it are added to the band filter 15. The filters 14 and 15 are narrowband filters whose center frequencies are the two frequencies contained in the audible signal to be detected, and are also constituted by digital filters. In the dial tone example described above, filter 14 is a band filter with a center frequency of 350 Hz and filter 15 is a band filter with a center frequency of 440 Hz. In this way, desired frequency components are extracted by the filter and applied to the detection circuits 16 and 17, and the level of each frequency component is measured. The determination circuit 18 determines the presence or absence of an audible signal sound from the measured level and outputs the result to the output terminal 19.

When there are several types of audible signal tones, a set of a low-pass filter, a high-pass filter, a band filter, a detection circuit, and a determination circuit are provided for each type to detect the presence or absence of each audible signal tone.

Examples of audible signal tones other than dial tone include ringback tone: 440 Hz and 480 Hz, busy tone: 480 Hz and 620 Hz, etc.

In the conventional audible signal sound detection circuit as described above, the frequency components are 350Hz and 440Hz in the above example.
There are four types: Hz, 480Hz, and 620Hz, but the combined frequencies and frequency differences are different, and the smallest frequency difference is 40Hz, which is quite small. Therefore, the cut-off frequencies of the low-pass filter 12 and the high-pass filter 13 are different, and a high-order filter is required to deal with small frequency differences. That is, the number of filters and the complexity of the individual filters increases.

In addition, such an audible signal tone detection circuit is
As in the case of PBR, in order to prevent malfunctions for audio signals and to quickly and accurately detect desired audible signal sounds, various characteristic standards are set, and the order of the filter is adjusted to meet these standards. Coefficients etc. must be optimally designed. A further problem is that standards for audible signals such as dial tone and busy tone
This is because they are not as unified and standardized as traffic lights). In other words, it is necessary to optimally design a filter that satisfies the characteristic standards as described above for various audible signal sounds, which is complicated and inefficient, and increases the amount of work required for design. It also leads to an increase in Further, it is not desirable to include such a complicated circuit in each interface circuit provided for each terminal. Therefore, the method of unifying line control signals using an interface circuit also has little feasibility.

Although the above explanation assumes a digital filter, it is of course possible to convert a digital code into an analog signal by a decoding circuit and configure an audible signal tone detection circuit using an analog filter. It is possible. However, even in that case, the design of the filter is considered to be more complicated and difficult than in the digital case.

The present invention eliminates such shortcomings in the prior art and utilizes the fact that an audible signal tone is generated by periodic reading of a digital code sequence stored in memory to provide memory, address and comparison circuits. It is an object of the present invention to provide an extremely simple audible signal sound detection circuit consisting of a detection circuit and a determination circuit, which has good detection accuracy and a short detection time.

That is, according to the present invention, in an audible signal tone detection circuit of a digital exchange having an audible signal tone generating circuit that generates an audible signal tone by periodically reading out a digital code series stored in a memory, a digital code word is generated. a first memory storing as data one of the positions of the digital code word in the digital code series stored in the audible signal tone generation circuit; a second memory storing a digital code sequence exactly the same as the digital code sequence; a comparison circuit for comparing the output of the second memory with the received digital code; and a sampling clock according to the output of the comparison circuit. a read address circuit that counts signals or takes in the output of the first memory and reads out the second memory using the counted value or the read value as an address; and a sampling clock according to the output of the comparison circuit. The present invention provides an audible signal sound detection circuit comprising a determination circuit that counts signals and determines the presence or absence of an audible signal sound.

Hereinafter, the present invention will be explained in detail with reference to the drawings. FIG. 2 is a diagram showing an embodiment of the present invention. In FIG. 2, the memory 20 is a memory that stores a digital code sequence that is exactly the same as the digital code sequence representing the audible signal tone stored in the audible signal tone generation circuit, and is read according to the output address of the read address circuit 21. , outputs the digital code stored at that address. The comparison circuit 22 compares this digital code with the received digital code applied to the input terminal 23, and if they match, outputs a signal "1", for example, and if not, outputs a signal "0". Output.

The read address circuit 21 is an n-ary counter that counts the sampling clock (a clock having a frequency equal to the reciprocal of the reception interval of the digital code) applied to the input terminal 24. However, n is the number of digital code words constituting the digital code sequence. The read address circuit 21 is
If the output of the comparison circuit 22 is "1", that is, the received digital code and the digital code output from the memory 20 match, a signal "1" is received through the gates 25 and 26, and is output by the sampling clock. Step forward by 1. The memory 20 outputs a new digital code according to the address incremented by 1, and the comparison circuit 22 compares it with the next received digital code. If the output is still "1", the above operations are repeated in sequence.

On the other hand, if the output of the comparison circuit 22 is "0", that is, the received digital code and the digital code output from the memory 20 do not match, the read address circuit 21 is provided with input terminals via gates 25 and 26. The inverted version of the load pulse applied to 27 is input. The read address circuit 21 takes in the output of the memory 28 by this load pulse and outputs it as a new address value. Here, the load pulse is a narrow clock pulse signal having the same frequency as the sampling clock signal but with a delayed phase.

The memory 28 stores data indicating the position of the received digital code word applied to the input terminal 23 in the digital code series stored in the audible signal tone generating circuit in a memory area whose address is the digital code word. It's something I remember. Every time a digital code word is received, location information indicating the position of the code word in the digital code series is output.

Therefore, the read address circuit 21 takes in the output of the memory 28 by the load pulse, and
If you output it to the memory 20 as a new address,
At the output of memory 20 there should appear the same digital code as the received digital code applied to input terminal 23. However, the received digital code is
Although this does not occur in the case of codes that are not included in the digital code series originally stored in the audible signal tone generation circuit, there is no problem in that case as will be described later.

In this way, the received digital code and memory 2
After the output code of 0 coincides with the output code, the read address circuit 21 increments by 1 at the next sampling clock, and the memory 20 outputs a new digital code in accordance with the address incremented by 1. Comparison circuit 22 compares the code with the next received digital code, and repeats the above-described operation according to its output.

Now, when the digital code sequence representing the audible signal tone to be detected is applied to the input terminal 23, if it does not match the output code of the memory 20, the output of the memory 28 is immediately taken into the readout address circuit and the memory 20 Output to. Now memory 2
The output sign of 0 coincides with the received digital sign, and from then on, read address circuit 21 advances in accordance with the sampling clock, except as described below. Correspondingly, the memory 20 outputs a digital code, which should all match the received digital code, so that from now on, while the audible signal tone to be detected is applied to the input terminal 23,
The comparison circuit 22 continues to output "1".

On the other hand, when an audio signal or a different audible signal tone is applied to the input terminal 23, the output of the comparator circuit 22 may coincidentally coincide with the output digital code of the memory 20 and become "1"; Disagreement occurs. Each time, read address circuit 2
1 takes in the output of the memory 28 and attempts to match it with the received digital code, but a mismatch immediately occurs and the above operations are repeated.

Therefore, if "1" appears continuously as the output of the comparator circuit 22, it means that the received digital code during that period corresponds to a part of the digital code sequence in the audible signal tone generating circuit. If a predetermined number (assumed to be m) or more occur consecutively, it can be determined that a desired audible signal tone has arrived.

The determination circuit 29 is a circuit for determining this. That is, the determination circuit 29 is a counter that counts the sampling clock applied to the input terminal 24 similarly to the read address circuit 21, and when the output of the comparison circuit 22 is "1", it is counted by the sampling clock. Take one step at a time,
After stepping by m, a detection signal of an audible signal tone is outputted to the output terminal 30. Thereafter, if the output of the comparator circuit 22 is "1", the detection signal continues to be output. On the other hand, when the output of the comparison circuit 22 is "0", the determination circuit 29 is immediately reset by the sampling clock. A time chart explaining the above operation is shown in FIG. FIG. 5 shows an example in which the comparator circuit 22 outputs a mismatch signal up to the received digital code _D0 , but the comparator circuit 22 outputs a mismatch signal for the received digital code _D1 . In response to a mismatch signal, the output of the memory 28 is read out from the address circuit 2 in the latter half of one sampling period.
1 and supplied to the memory 20. As a result, the memory 20 outputs the same code as the received digital code, and the comparison circuit 22 outputs a matching signal. At the beginning of the next sampling period, read address circuit 21 increments by one according to the sampling clock and moves on to the next comparison operation. The determination circuit 29 counts up by 1 when the comparison circuit 22 outputs a match signal in the middle of the sampling period, and is reset to 0 when it outputs a mismatch signal.

In this way, when receiving an audible signal sound to be detected, the detection signal is definitely output to the output terminal 30.
It is possible to construct an audible signal tone detection circuit that almost never erroneously transmits a detection signal when transmitting a signal to a user or receiving a voice or other audible signal.

Note that the sampling of the read address circuit 21
A gate 31 is inserted to avoid a collision between the time of change caused by the clock and the time of determination by the determination circuit 29. Also, the load applied to the input terminal 27
It is assumed that the phase of the pulse is further delayed than the time point at which the determination circuit 29 makes a determination.

Although it is possible to detect an audible signal tone using the method described above, some caution is required since the digital code sequence in the audible signal tone generation circuit often includes a plurality of the same digital code words.

Including this point, this method will be explained in more detail below using a specific example. Figure 3 shows one of the world's standard audio PCM encoding rules. Dial tone (350Hz, 440Hz) according to μ law
This is an example expressed as a word code sequence. This corresponds to the content stored in the memory 20.

In other words, each code word and its location are 16
When expressed in base numbers, the correspondence relationship is obtained such that the 00th is the code AA, the 01st is the code CC, the 02nd is the code D7, and so on.

According to these correspondences, the memory 28 in FIG.
FIG. 4 shows part of the relationship between data to be stored and addresses. i.e. "00" for address AA
However, "01" is stored in address CC and "02" is stored in address D7. Code D7 is the 18th and 19th
th (these are hexadecimal numbers, so on)
However, only one piece of data, for example "02", is stored here. DE,
The same applies to other codes that appear repeatedly, such as E1.

Further, fixed data such as "00" may be written in blank areas, that is, areas corresponding to codes that do not appear in the code series shown in FIG. In FIG. 3, a circle mark indicates that the same code exists after that, and a circle mark indicates that the same code already exists before it. Further, in FIG. 4, the ● mark corresponds to a code whose address position appears repeatedly, and indicates that only one of the existing positions is stored as data.

Now, suppose that the code sequence shown in FIG. 3 is applied to the input terminal 23 from "D3" at address 08 at a certain point in time. Normally, the output code of the memory 20 at this time does not match this, so the comparator circuit 22 outputs "0" and the read address circuit 21 immediately receives the output of the memory 28 at this time (see FIG. 4).
"08" is input. Therefore, the output code of the memory 20 becomes "D3", and as the read address circuit 21 advances, it becomes "C2", "1F", and so on.
"47"... is output. Since this exactly matches the received digital code sequence, the comparator circuit continues to output a matching signal "1", and when m consecutive matching signals occur, the determining circuit 29 outputs a detection signal to the terminal 30.

Further, if this code series is added from "C9" at address 39, "1C" is first inputted to read address circuit 21 in accordance with the mismatch output from comparator circuit 22. As a result, the output of the memory 20 becomes "C9", but when the read address circuit 21 advances in response to the next sampling clock signal, the memory 20 outputs "BB" at address 1D, whereas the received digital The code is "C5"
and does not match. However, if the output ``3A'' of the memory 28 is once again input to the read address circuit based on this ``C5'', the subsequent output of the memory 20 will exactly match the received digital code sequence.

In other words, when the read address circuit 21 receives an input from the symbol marked with ● in FIG. A match between the digital code sequence and the contents stored in the memory 20 can be detected.

Therefore, the problem is the continuity of ● marks, but as can be seen from Fig. 3, the proportion of such cases is extremely small, and by writing the contents of the memory 28 shown in Fig. 4, It is also possible to avoid continuity as much as possible.

Also, if you write address 00 for codes that do not appear in Figure 3 (corresponding to the blank areas in Figure 4), such codes will always be stored in memory 20.
The comparison will be attempted from address 00 of , and a mismatch will occur, so no problem will occur.

As can be seen from the above explanation, in this method, when comparing the received digital code sequence and the code sequence stored in the memory 20, the memory 20
8 to instantaneously give the phase of the code sequences to be compared, thereby speeding up the detection.

Note that a value of about 8 or 16 is considered to be sufficient for determining that an audible signal tone has been detected. This is because the audible signal tone detection circuit according to the present invention strictly monitors the order of the received digital codes, whereas the appearance of the codes in the audio signal is close to random, and the audible signal tone has 8 words or 16 words.
This is because the code sequence rarely matches, even partially, with other audible signal tones.

Furthermore, the fact that m = about 16 is sufficient means that in the case of the standard PCM method with 8KHz sampling, the detection time is extremely short at 125μsec x 16 = 2msec, which means that it has good response as an audible signal sound detection circuit. I understand that.

As can be seen from the above description, the audible signal tone detection circuit according to the present invention has an extremely simple configuration.
First of all, there is no need for an expansion circuit for the digital filter or a decoding circuit for the analog filter. Further, the basic operation of the detection circuit is only memory reading, simple comparison and counting of the read data, and no filter operation is performed. Once the digital code sequence to be stored in the audible signal tone generating circuit is determined, the memory 20,
The data stored in 28 is also automatically determined. In addition, since no filter operation is performed, there is no need to optimally design the filter order and coefficients.
Circuit design is also extremely easy. Also, even if the standards for audible signals change, memory 2
Just by changing the data stored in 0 and 28,
It is easily manageable. The memory capacity of the memory 28 is 256 words if an 8-bit digital code, which is the world standard, is used.
The memory capacity of 0 is also the code sequence length of the audible signal tone, so 256 words at most is sufficient. 16Kbit,
In today's world, where 32Kbit memory is now available, this is a very small amount of memory.

In the above explanation, we have assumed that the audible signal tone is a signal expressed as the sum of sine waves of two frequencies, but it is clear that the application is also applicable to signals expressed as a sine wave of a single frequency. It is.

As described above with respect to the embodiments, according to the present invention, an audible signal sound detection circuit with excellent characteristics can be obtained with a very simple configuration without using complex functions and circuits such as filters. The effect is extremely large.

The present invention is also applicable when the audible signal tone is generated by periodic reading of a digital code sequence stored in memory, but is also applicable to push-button (PB) signals, multi-frequency (MF) signals, etc. It is also applicable to PB signal receiver (PBR), MF signal receiver (MFR) if the signal is generated by a similar method, and is much easier to configure than traditional PBR, MFR. Therefore, the effect is significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an audible signal detection circuit according to the prior art, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIGS. FIG. 5 is an explanatory diagram illustrating the operation timing of each circuit in the embodiment of the present invention. 12,1 in the figure
3, 14, 15 are filter circuits, 16, 17 are detection circuits, 20, 28 are memories, 22 is a comparison circuit,
21 is a read address circuit, and 29 is a determination circuit.

Claims (1)

[Claims] 1. In an audible signal tone detection circuit of a digital exchange having an audible signal tone generation circuit that generates an audible signal tone by periodically reading out a digital code series stored in a memory, the digital code word is used as an address, and an audible signal a first memory storing as data one of the positions of the digital code word in the digital code series stored in the sound generation circuit; a second memory that stores the same digital code sequence; a comparison circuit that compares the output of the second memory with the received digital code; and if the results of the comparison by the comparison circuit match, sampling is performed. a read address circuit for reading the second memory, which increments the address by 1 in accordance with a clock signal and, if they do not match, takes in the output of the first memory and uses it as a new address; If the comparison result by the comparator circuit matches, the sampling clock signal is counted; if they do not match, the counted value is reset, and when the counted value reaches a predetermined value, an audible signal tone is received. 1. An audible signal sound detection circuit comprising: a determination circuit for determining an audible signal sound;