JPH0237753B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an audible signal receiving circuit for an audible signal generating circuit that periodically reads out a digital code sequence stored in a memory in a time division digital exchange.

Time division digital switching equipment is becoming the most popular switching equipment due to rapid advances in digital communication technology and LSI technology. Furthermore, due to its affinity for digital signals, its scope of application is expanding not only to telephones but also to data terminals and data processing devices. Particularly from the point of view of streamlining business communications, the emergence of an integrated voice/data switch that accommodates both telephone and data equipment and exchanges them all together is essential.

There are various ways to implement such an integrated voice/data switch. For example, it is conceivable to provide advanced functions to the exchange itself using a packet switching method, but it is also possible to achieve this by interconnecting devices with equivalent functions using a circuit switching method. This is because, in this method, the exchange itself becomes extremely simple, and the restrictions on connections with terminals and the like are relaxed.

There are several possible circuit switching methods. The big issue here is how to deal with the various differences in terminals. Particularly problematic is the difference in line control signals between the terminal and the exchange, such as line setting, disconnection, and transmission of selection signals. On the other hand, the method of using different line control signals for each terminal has the disadvantage that the control program of the exchange becomes complicated, and it is necessary to register the type of terminal, which causes inconvenience when changing. On the other hand, if an interface circuit is provided at the input section from the terminal to the exchange, and this interface circuit unifies the line control signals so that all terminals look exactly the same from the control section of the exchange, the above-mentioned method can be achieved. It has no problems and is extremely advantageous. Furthermore, since telephones are considered to be the most common terminal in business communications, a method of unifying the line control signals of each terminal into the line control signal of the telephone is promising.

Although the above-mentioned interface circuit is installed on the exchange side, it can also be installed on the terminal side in principle.

In other words, in the above-mentioned interface circuit, call origination and call termination signals (STX,
ETX) into off-hook and on-hook signals, and converts selection signals from character dials, etc., into dial pulses or push button signals. Meanwhile, the exchange is ready to receive dials.
Audible signals (dial tone, busy tone,
Lindback tone, etc.) is sent. The interface circuit must convert these signals into ACK, NACK, Ready, Wait, etc. signals for data terminals, etc. Therefore, the interface circuit requires an audible signal receiving circuit.

However, since these audible signals have conventionally been used to prompt humans to take action and facilitate the progress of a call, it can be said that there are almost no examples of circuits for receiving these signals by machines. However, by analogy with the function of specific frequency identification in a situation where audio signals are present, if we construct an audible signal receiving circuit modeled after a push-button signal receiving device (PBR), the result will be as shown in Figure 1. Become. Note that these audible signals are, as a general rule, signals expressed in the form of the sum of sine waves of two frequencies.

In FIG. 1, since the digital code word applied to the input terminal 10 is normally a compressed nonlinear code, it is converted into a linear code by the decompression circuit 11, and then passed through the low-pass filter 12 and the high-pass filter. Added to 13. Both of these filters are digital filters, and the cutoff frequency is determined depending on the two frequencies contained in the audible signal to be received. For example, in the case of a dial tone consisting of two frequencies, 350Hz and 440Hz,
Simply put, the boundary is 395Hz, which is the intermediate frequency between the two, and the frequency components below that are filtered through band filter 1.
4, the higher frequency components are passed through a band filter 15.
Add to. The filters 14 and 15 are narrowband filters whose center frequencies are two frequencies included in the audible signal to be received, and are also constructed from digital filters. In the dial tone example described above, filter 14 is a band filter with a center frequency of 350 Hz and filter 15 is a band filter with a center frequency of 440 Hz. In this way, desired frequency components are extracted by the filter and added to the detection circuits 16 and 17 to measure the level of each frequency component. The determination circuit 18 determines the presence or absence of an audible signal from the measured level and outputs the result to the output terminal 19.

When there are several types of audible signals, a set of a low-pass filter, a high-pass filter, and a band filter, a detection circuit, and a determination circuit are provided for each type to identify the presence or absence of each audible signal. Examples of audible signals other than dial tone include Lindback tone: 440Hz and 480Hz.
Hz, busy tone: 480Hz and 620Hz, etc.

In the conventional audible signal receiving circuit as described above, the frequency components are 350Hz in the above example and 440Hz in the above example.
There are four types: Hz, 480Hz, and 620Hz, but the combined frequencies and frequency differences are different, and the smallest frequency difference is 40Hz, which is quite small. Therefore, the cut-off frequencies of the low-pass filter 12 and the high-pass filter 13 are different, and a high-order filter is required to deal with small frequency differences. This increases the number of filters and the complexity of the individual filters.

Also, similar to the case of PBR, such an audible signal receiving circuit prevents malfunctions in response to audio signals,
Furthermore, in order to quickly and accurately receive a desired audible signal, various characteristic standards must be set and the order, coefficients, etc. of the filter must be optimally designed to meet the standards. A further problem is that the standards for audible signals such as dial tones and busy tones are not as unified and standardized as push button signals (PB signals). In other words, it is necessary to optimally design a filter that satisfies the characteristic standards as described above for various audible signals each time, which is complicated and inefficient, and increases the cost due to the increased amount of work required for design. It also leads to Furthermore, it is not desirable to include such a complicated circuit in each interface circuit provided for each terminal. Therefore, the method of unifying line control signals using an interface circuit is less feasible.

Although the above explanation assumes a digital filter, it is of course also possible to convert the digital code to an analog signal by a decoding circuit and configure an audible signal receiving circuit using an analog filter. It is. However, even in that case, the design of the filter is considered to be more complicated and difficult than in the digital case.

The present invention eliminates such drawbacks in the prior art, and utilizes the fact that an audible signal is generated by periodic reading of a digital code sequence stored in a memory to generate signals from a memory, an arithmetic circuit, and a determination circuit. The present invention aims to provide an extremely simple audible signal receiving circuit with high reception accuracy.

That is, according to the present invention, in an audible signal receiving circuit of a digital exchange having an audible signal generating circuit that generates an audible signal by periodically reading out a digital code series stored in a memory, an audible signal is generated using a digital code word as an address. a first memory storing as data one of the positions of the digital code word in the digital code series stored in the signal generating circuit; A second memory that stores the mutual relationship of existing positions, selects and holds one of the outputs of the first memory and the output of the second memory, and connects it to the input terminal of the second memory. A selection holding circuit supplies the output, a holding circuit captures and holds the output of the second memory every sample period, and calculates the difference between the output of the second memory and the output of the holding circuit, and calculates the difference between the output of the second memory and the output of the holding circuit. It is comprised of an arithmetic circuit that determines whether the signal is a value and outputs the result, and a determination circuit that determines the presence or absence of an audible signal by counting or storing a plurality of outputs of the arithmetic circuit. A characteristic audible signal receiving circuit is obtained.

The present invention will be described in detail below with reference to the drawings.
FIG. 2 is a diagram showing an embodiment of the present invention. In FIG. 2, a memory 20 stores data indicating the position of the received digital code word applied to the input terminal 21 in the digital code series stored in the audible signal generating circuit, using the digital code word as an address. This is what is stored in the memory area. Every time a digital code word is received at a sampling period interval (125 μsec in the case of standard PCM), location information indicating the position of the code word in the digital code series is outputted to the output terminal 22. .

First, for convenience of explanation, consider the case where there are no two or more identical digital code words in the digital code series, and in FIG.
3. It is assumed that there is no memory 24, and the location information on the output terminal 22 can be obtained as is on the output terminal 25.

Holding circuit 26 captures this information at the moment the next digital code word is applied to input terminal 21 and holds it for one sample period. Therefore, the existence position information of the previous received digital code word always appears at the output terminal 27 of the holding circuit 26. This information is inverted into "1" and "0" by the inversion circuit 28 and is supplied to the addition circuit 29. The other input of the adder circuit 29 is supplied with the output terminal 25, that is, the output of the memory 20. Therefore, the addition circuit 29 subtracts the previous location information from the latest location information. However, since the previous existing location information is expressed in 1's complement, if the latest existing location information is increased by 1 from the previous existing location information, that is, the continuously received digital code word If they match consecutive digital code words in the digital code series of the audible signal generating circuit, the addition results 30 and 31 will be all bits "0". Therefore, at this time, the output of the NOR gate 32 becomes "1". That is, the inverting circuit 28,
The adder circuit 29 and the NOR gate circuit 32 as a whole are an arithmetic circuit that subtracts the output of the holding circuit 26 from the output on the output terminal 25 and outputs a signal indicating whether the subtraction result is 1 or not.

For example, as a time series of existing position information corresponding to the digital code word input to the input terminal 21.
If 0010, 0011, 1000 (an example of a 4-bit binary number representation) are output from the memory 20, the output of the arithmetic circuit at each point in time will be as follows.

(i) When 0011 is output from the memory 20: Since the one's complement representation 1101 of the previous output 0010 appears at the output of the inverting circuit 28, the adding circuit 2
The result of addition of 9 is 1101+0011=0000 (ignoring the carry of the most significant bit), and the output of the gate 32 becomes "1". In other words, the difference from the previous location information is 1
Indicates that it was warm.

(ii) When 1000 is output from memory 20: Similarly, the one's complement representation of the previous output 0011 is 1100
appears at the output of the inverting circuit 28, the addition result of the adding circuit 29 is 1100+1000=0100 (ignoring the carry of the most significant bit), and the output of the gate 32 becomes "0". In other words, the difference from the previous location information is 1
It shows that this was not the case.

If "1" appears continuously as the output of gate 32 over a plurality of sample periods, it means that the received digital code word during that period exactly matches a part of the digital code sequence in the audible signal generation circuit. If the signal continues for a period corresponding to a predetermined number (assumed to be m) of sample periods, it can be determined that the desired audible signal has arrived.

The counter 33 is a circuit for determining this.

That is, the counter 33 is an m-ary counter, and counts the clock (sampling clock) equal to the sampling frequency (=reciprocal of the reception interval of the digital code) applied to the input terminal 34 while the output of the gate 32 is "1". , after m consecutive count-ups, a full-up signal is outputted to the output terminal 35 as an audible signal detection signal. Thereafter, if the output of the gate 32 is "1", the full-up signal, that is, the detection signal continues to be output. On the other hand, when the output of the gate 32 becomes "0" during count-up or after full-up, the counter is immediately reset in accordance with the sampling clock.

In principle, it is possible to detect an audible signal in this way, but since the digital code series in the audible signal generation circuit often contains multiple identical digital code words, only the method described above can be used. That's not enough.

This point will be explained below using a specific example. First of all,
The number of digital codewords required to represent a dial tone is determined as follows.

The number of digital code words required is the number of words necessary to express the waveform of one cycle of time for a frequency that is the greatest common divisor of the two frequencies to be added. Thus, for example, dial tone
If you add 350Hz and 440Hz, the greatest common divisor frequency is 10Hz, and if you sample it at 8kHz, you will need 800 words. However, by considering the symmetry of the two waveforms to be added, this can be reduced to 1/
It is possible to compress it by 2 or 1/4.

On the other hand, when actually configuring the exchange, 350Hz,
Specifications are determined with an error of approximately ±1% for the frequency of 440Hz. By utilizing this tolerance range, the greatest common frequency can be increased, and as a result, the number of required code words can be reduced. For example, by setting the dial tone frequencies to 351.6484Hz and 439.5604Hz, the greatest common frequency can be approximately 87.9Hz, which can be expressed in 91 words. FIG. 3 shows an example in which the dial tone described above is expressed as a code sequence of 91 words in accordance with the μ law, which is one of the world's standard speech encoding laws. In other words, when each code word and its location are expressed in hexadecimal, the code AA is at the 00th position,
A correspondence relationship is obtained in which the 01st is the code CC, the 02nd is the code D7, and so on.

According to these correspondence relationships, the memory 20 in FIG.
FIG. 4 shows part of the relationship between data to be stored and addresses. As already explained, the memory 20 is a memory that uses each digital code word as an address and uses the position of the code word in the digital code series as data. Therefore, "00" is stored in address AA, "01" is stored in address CC, and "02" is stored in address D7. However, as shown in Figure 3, the code D7 is the 18th and 19th (these positions are also expressed in hexadecimal).
However, only one piece of data, for example "02", is stored here. DE,
The same applies to other codes that appear overlapping E1, etc.

Also, in the blank areas, that is, the areas corresponding to codes that do not appear in the code series in Figure 3, you can write code positions that do not exist in reality, such as "FF", or fixed data, such as "00". . In Figure 3,
The circle symbol indicates that the same code exists after the existence position 00, and the circle symbol indicates that the same symbol already exists before it. Further, in FIG. 4, the ● mark corresponds to a code whose address position appears repeatedly, and indicates that only one of the existing positions is stored as data.

Therefore, the code sequence of the regular audible signal is stored in the memory 20.
When applied to the input terminal 21 of the output terminal 22,
Therefore, the temporal sequence of the presence position information obtained at the output terminal 25 and the output of the gate 32 is as follows (the vertical direction corresponds to the same time).

Reception code AA, CC, D7, DE, E1, E1, E0,
DB, ... Existence position 00, 01, 02, 03, 04, 04, 06, 07, ... Gate 32 output -, 1, 1, 1, 1, 0, 0, 1, ...... In other words, normal audible Code E1 that appears repeatedly even though the signal code sequence is being received
The output of the gate 32 becomes "0" near .

Therefore, it is necessary to supply both the existence positions "04" and "05" to the code E1 so that one of them can be selected. The selection and holding circuit 23 and memory 24, which have been omitted in the explanation so far, are circuits that make this possible.

The memory 24 stores, in a digital code sequence,
It stores the mutual relationship of existing location information with the same code. For example, data "05" is stored in address "04" and data "04" is stored in address "05" for positions "04" and "05" where code E1 exists. Also, the position where code D7 exists is “02”, “18”,
For "19", address and data are stored cyclically as follows.

Address-Data 02-18 18-19 19-02 Similarly, the relationship between addresses and data for the entire code series shown in FIG. 3 is determined as shown in FIG. 5. In the blank part, the same value as the address of that part is stored as data. For example, data "00" is stored at address "00".

The selection holding circuit 23 is connected to the input terminal 2 of the memory 20.
When a received digital code is added to 1, the corresponding location information output of the memory 20 is first selected and held, and is added to the input terminal of the memory 24.
The memory 24 outputs other location information having the same code to the input location information to an output terminal 25.
Output to. The selection and holding circuit 23 then selects and holds this output and inputs it to the memory 24. The memory 24 similarly outputs existence position information corresponding to the input existence position information, and selects and holds the selection holding circuit 23.
select this and keep it. By repeating this operation several times during one sampling period, all the location information in the digital code sequence of the received digital code applied to the input terminal 21 of the memory 20 is output to the output terminal 25 of the memory 24. . Their location information and the holding circuit 26
The addition circuit 29 calculates the difference between the existence position information corresponding to the previous digital code word held in When becomes "1", the selection operation of the selection holding circuit 23 is stopped and the data held at that time is continued to be held as is. Therefore, the memory 24 continues to output the same output, and the output of the gate 32 is also fixed at "1".
Then, at the moment when the next digital code word is applied to the input terminal 21, the output of the memory 24 is transferred to the holding circuit 2.
6 is taken in, and the counter 33 is counted up. On the other hand, if the output of the gate 32 is not "1" for any location information,
After all, memory 2 is stored at the moment when the next digital code is received.
The holding circuit 26 takes in the output of 4, and the counter 33 is reset at the same time. The above operation is repeated every time a new code is received at the input terminal 21, and when the counter 33 counts up by a predetermined number m, a detection signal is outputted to the output terminal 35. Note that if the maximum value of the number of existing position information for the same code is n, the selection and holding operation of the selection and holding circuit 23 may be configured so that it can be performed n times during one sampling period.

Specifically, using a clock (selective hold clock) with a frequency n times that of the sampling clock,
It is only necessary to drive the selection and holding operation of the selection and holding circuit 23.

The above operation will be specifically explained based on the example shown in FIG. In the example of FIG. 3, since n=3, the selection and holding operation is performed three times. First, when the code D7 is applied to the input terminal 21, the existence position information "02" appears at the output of the memory 20 according to the contents of FIG. The selection holding circuit 23 captures and holds this output in accordance with the selection holding clock, and inputs it to the memory 24.

The memory 24 outputs the existence position information "18" according to the contents of FIG. If the output of the gate 32 does not become "1" with respect to this output and the output of the holding circuit 26, the selection holding circuit 23 selects and holds the output "18" of this memory 24 according to the next selection holding clock. Add to 24. On the other hand, memory 24
outputs "19", and if the output of the gate 32 does not become "1" in response to this, the above operation is repeated and the memory 24 outputs "02". Further, if the output of the gate 32 becomes "1" in response to, for example, "18" among the outputs of the memory 24, that signal is supplied to the selection and holding circuit 23 to stop the subsequent selection and holding operation. Therefore, immediately before the next code is added to the input terminal 21, the output of the memory 24 will contain the existing position information that caused the output of the gate 32 to be "1", if that information exists, and if there is no such information, the output will be "3". The th existence position information “02” appears. The counter 33 is counted up or reset according to the output of the gate 32 at this time, and the holding circuit 26 captures and holds the output of the memory 24 at this time in preparation for a series of operations for the next received digital symbol. .

For the code E1, the location information appears in the output of the memory 24 in the order of "05", "04", and "05". Furthermore, for the code AA, which exists only once in the digital code series, "00" appears three times repeatedly in the output of the memory 24. In either case, there is no problem with the above-mentioned detection operation.

Note that for the last code in the code series shown in FIG. 3, a jump occurs in the existing position when moving to the first code. To prevent this, the holding circuit 26 shown in FIG.
When the last existing position of the code series ("5A" in the example in Figure 3) is detected in the output of the gate 32, a circuit is inserted to set all bits to "1", or the output of the gate 32 is sampled by two samples. Monitor the period,
The counter 33 may be configured to be reset only when both are "0" and counted up at other times.

With the above-described circuit configuration, even if there are codes that appear redundantly in a digital code series, the audible signal to be detected can be detected without error. Furthermore, since the order of received digital codes is strictly monitored, the probability of erroneously detecting a voice signal or a different audible signal is extremely small even when m=8 or 16. The appearance of the codes in the audio signal is close to random, and the audible signal has 8 words or 16 words.
This is because words and code sequences rarely match even partially with other audible signals.

Furthermore, the fact that about m=16 is sufficient indicates that in the case of the standard PCM method using 8KHz sampling, the detection time is extremely short at 125 μsec×16=2 msec. On the other hand, the digital
The method using a filter requires 30 msec or more, but the present invention can significantly shorten the detection time, and it can be seen that it has good responsiveness as an audible signal receiving circuit.

Furthermore, the audible signal receiving circuit according to the present invention has an extremely simple structure. First of all, there is no need for an expansion circuit for the digital filter or a decoding circuit for the analog filter. Further, the basic operation of the detection circuit is only reading out the memory, simple calculations and counting or pattern detection on the read data, and does not perform any filter operation. Once the digital code series stored in the audible signal generation circuit is determined, the data stored in the memories 20 and 24 is also uniquely determined. Further, since no filter operation is performed, there is no need to optimally design the order and coefficients of the filter, and the circuit design is extremely easy. Furthermore, even if the standards for audible signals change, the memory 20, 24
This can be easily resolved by simply changing the data stored in the . If the world standard 8-bit digital code is used, the memory capacity of the memory 20 may be 265 words, and the memory capacity of the memory 24 may be about the length of the code sequence of the audible signal.
In today's situation where 16Kbit and 32Kbit memory are also appearing, it can be said that the amount of memory required is extremely small.

In the above explanation, we have assumed that the audible signal is a signal expressed in the form of the sum of sine waves of two frequencies, but it is clear that the application is also applicable to signals expressed as a sine wave of a single frequency. be.

As described above with respect to the embodiments, according to the present invention, the detection accuracy is high with a very simple configuration without using complicated functions and circuits such as filters, and the time required for detection is extremely short. A receiving circuit can be obtained, and its effects are extremely large.

The present invention is also applicable to cases where the audible signal is generated by periodic reading of a digital code sequence stored in memory; It is also applicable to PB signal receiver (PBR), MF signal receiver (MFR) if the signal is generated by a similar method, and is much easier to configure than traditional PBR, MFR. Therefore, the effect is significant.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing an audible signal receiving circuit according to the prior art, FIG. 2 is an explanatory diagram showing an embodiment of the present invention, FIG. 3 is an explanatory diagram showing an example of a code sequence of an audible signal, and FIGS. FIG. 5 is a diagram showing an example of the stored contents of the memory in FIG. 2. In the figure, 12, 13, 14, 15 are filter circuits, 16, 17 are detection circuits, 20, 24 are memories, 23 is a selection holding circuit, 26 is a holding circuit, 2
9 is an adding circuit, and 33 is a counting circuit.

Claims (1)

[Claims] 1. In an audible signal receiving circuit of a digital exchange having an audible signal generating circuit that generates an audible signal by periodically reading out a digital code series stored in a memory, each digital code word is used as an address, and the audible signal generating circuit a first memory storing as data one of the locations of the digital code word in the digital code series stored in the digital code series; If the same code word as the digital code word existing at the position of the code word exists in the digital code series, one of the other code positions is stored as data, and if the same code word does not exist, the address is stored. a second memory that stores the data as data; a holding circuit that captures and holds the output of the second memory every sample period; and the holding circuit that reads the output of the second memory every sample period. Subtract the output of
an arithmetic circuit that outputs a signal indicating whether the subtraction result is 1; and a calculation circuit that selectively holds the output of the first memory and subsequently selectively holds the output of the second memory during the sampling period. In a series of selection and holding operations performed a predetermined number of times, when a signal indicating that the subtraction result is 1 is output from the arithmetic circuit, the next selection and holding operation is stopped, and the holding held in each selection operation is stopped. A selection holding circuit that supplies an output to the second memory and the output of the arithmetic circuit are monitored, and when the signal indicating that the subtraction result is 1 continues for a predetermined period, it is determined that the audible signal has been received. 1. An audible signal receiving circuit comprising: a determination circuit for determining