JPH0329213B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a frame synchronization forming circuit in a digital transmission device.

[Prior art]

In the following explanation, one block is m-bit parallel data, one frame is m-row (n-column) parallel data consisting of n blocks, and m-row (n x s) parallel data consisting of s frames is assumed to be one block. Let the data be one multiframe. Assume that m-bit parallel data is input to the frame synchronization forming circuit at a transmission rate of q bits/second.

A frame synchronization forming circuit is a circuit in a digital transmission device that adds a serial frame synchronization pattern (α bit) to the data to be transmitted according to the standard frame structure of the digital transmission hierarchy in order to transmit digital data. It is. The data transmitted from the frame synchronization forming circuit is serial data.

Conventionally, in order to transmit digital data signal-processed as parallel data in a digital transmission device according to a standard frame structure, a conventional frame synchronization forming circuit converts m-bit parallel data into serial data, which is the result of parallel/serial conversion. An α-bit frame synchronization pattern (serial data) was added to the .

As a result, the conventional frame synchronization forming circuit requires a processing speed of {(m×n×s+α)×q/(n×s)} bits/second. This processing speed is close to the upper limit of the operating speed of the circuit elements, and the operation becomes uncertain due to variations in element characteristics.

Furthermore, this processing speed becomes the transmission speed of the serial data that is output as is, but this processing speed often does not match the transmission speed specified in the digital transmission hierarchy. Therefore, a circuit for matching the speeds is required, which complicates the circuit configuration.

[Purpose of the invention]

A first object of the present invention is to add a parallel frame synchronization pattern equivalent to a serial frame synchronization pattern to parallel data without converting parallel data to serial data when adding a serial frame synchronization pattern. q
It is an object of the present invention to provide a frame synchronization forming circuit which can operate at bit per second speeds, thus reducing the processing speed compared to serial type processing.

The second object of the present invention is to convert parallel data with a parallel frame synchronization pattern into serial data (m/k) instead of converting it directly into serial data.
After dividing the bit parallel data into k channels, convert the (m/k) bit parallel data into (m×q/k) bits/second serial data for each channel, and convert the values of m, k, and q into A frame synchronization forming circuit that can set the value of (m x q/k) to the transmission speed of the digital transmission hierarchy by appropriately combining it, and therefore can simplify the circuit without requiring extra circuits. It is about providing.

[Structure of the invention]

One block is m-bit parallel data, one frame is m rows and n columns of parallel data where n blocks are collected, and one frame is m rows (n x s) parallel data where s frames are collected. Multi-frame. A parallel frame synchronization pattern, which is parallel data of m rows and l columns, is added to the front of the one multiframe, and the parallel data of m rows and columns (n×s+l) is defined as a parallel frame synchronization format.

In order to add a parallel frame synchronization pattern to each consecutively input multi-frame (to form a parallel frame synchronization format), the frame synchronization forming circuit according to the present invention inserts the time slots necessary for inserting the parallel frame synchronization pattern into the above-mentioned time slots. a signal control circuit that outputs parallel data between multiple frames; a pattern generation circuit that generates the parallel frame synchronization pattern; a signal synthesis circuit that inserts the parallel frame synchronization pattern to form the parallel frame synchronization format, and converts the parallel frame synchronization format formed by the signal synthesis circuit into k (m/k) rows of parallel data; Divide the data, perform a parallel/serial conversion operation on each divided parallel data, and
The circuit includes a parallel/serial conversion circuit that outputs serial data to four output terminals, and a control clock circuit that generates various clock signals that control the operations of the four circuits.

The first objective is achieved by a combination of a signal control circuit, a pattern generation circuit, a signal synthesis circuit, and a control clock circuit. The second objective is achieved by a combination of a parallel/serial conversion circuit and a control clock circuit.

The parallel frame synchronization pattern, which is parallel data of m rows and l columns, is configured to have a pattern configuration on the premise that it is divided into k channels by the parallel/serial conversion circuit.

In the (m/k) rows of parallel data divided into k channels by the parallel/serial conversion circuit, the (m/k) rows and l columns of parallel data added to the beginning of each multi-frame are It is clear that the frame synchronization pattern is (l/k). Configuring the parallel frame synchronization pattern so that the (m/k)×l bit serial data obtained by converting the (m/k) rows and l columns of parallel data into serial data becomes a serial frame synchronization pattern. . Depending on the pattern configuration, the parallel frame synchronization format is divided into k channels, and the parallel/frame synchronization format is divided into k channels.
By performing a serial conversion operation, it is possible to easily form a serial frame synchronization format that is compatible with the digital transmission hierarchy.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is an input terminal, 2 is a serial clock input terminal, 3 is a control clock circuit, 4 is a signal control circuit, 5 is a pattern generation circuit, and 6 is a block diagram showing an embodiment of the present invention. is a signal synthesis circuit,
7 is a parallel/serial conversion circuit, 8 and 9 are output terminals, A is a parallel clock, B is input parallel data, C is a read clock, D is parallel data having a time slot for a frame synchronization pattern, and E is a pattern clock. , F is the frame synchronization pattern, G is the selection clock, H is the parallel frame synchronization format, I is the serial clock,
J and K indicate serial frame synchronization formats.

In Figure 1, serial clock input terminal 2
The 16-bit parallel data B input from the input terminal 1 is synchronized with the parallel clock A generated by the control clock circuit 3 by the serial clock I input from the control clock circuit 3. input to the first buffer memory. In order to process the input parallel data B as one multi-frame, 16 blocks are set as one frame, and in order to form a time slot for a frame synchronization pattern every 16 frames, it is synchronized with the read clock C generated by the control clock circuit 3. 1 from the first buffer memory in the signal control circuit 4.
Input parallel data B is input to the second buffer memory in the signal synthesis circuit 6 for each block. That is, after inputting the parallel data of the 16th block of the 16th frame to the second buffer memory in the signal synthesis circuit 6, the parallel data of the 16th block of the parallel clock A is input to the second buffer memory in the signal synthesis circuit 6.
The read clock C is stopped for the clock period, and the 2
After the clock period has elapsed, the read clock C is generated again and the parallel data of the first block of the next multi-frame is inputted from the first buffer memory in the signal control circuit 4 to the second buffer memory in the signal synthesis circuit 6.

Further, the pattern generation circuit 5 generates a transmission line frame synchronization pattern and a channel synchronization pattern in synchronization with the pattern clock E generated by the control clock circuit 3, and sends them to the signal synthesis circuit 6.

In the signal synthesis circuit 6, the frame synchronization pattern F from the pattern generation circuit 5 is controlled by the selection clock G generated in the frame synchronization pattern time slot period control clock circuit 3. input to buffer memory,
Outside the frame synchronization pattern time slot period, parallel data from the signal control circuit 4 is input to the second buffer memory in the signal synthesis circuit 6. By the above processing, a parallel frame synchronization format H is formed in the second buffer memory in the signal synthesis circuit 6.

Further, in synchronization with the parallel clock A, the parallel frame synchronization format H is sent to the signal synthesis circuit 6.
The 16-bit parallel data is divided into two channels of upper 8 bits and lower 8 bits and inputted from the second buffer memory in the parallel/serial conversion circuit 7 to the third buffer memory in the parallel/serial conversion circuit 7. The two channels of data are each subjected to parallel/serial conversion and sent to output terminals 8 and 9 as serial frame synchronization formats J and K, respectively.

Although a specific embodiment has been described above, in general, parallel data is divided into k channels, and in order to transmit it as serial data, transmission line frame synchronization is performed and each serial data divided into k channels is It is necessary to synchronize the channels. Therefore, in order to form a frame synchronization pattern time slot, the signal control circuit reads m bits from the first buffer memory in the signal control circuit in synchronization with the readout clock generated by the control clock circuit, excluding the time slot period. Read the parallel data and send it to the signal synthesis circuit.

On the other hand, the pattern generation circuit generates a transmission line frame synchronization pattern and a channel synchronization pattern between k pieces of serial data in synchronization with the pattern clock generated by the control clock circuit, and sends them to the signal synthesis circuit.

In the signal synthesis circuit, during the time slot period, the frame synchronization pattern from the pattern generation circuit is input to the second buffer memory in the signal synthesis circuit, and outside the time slot period, the frame synchronization pattern is input to the first buffer memory of the signal control circuit. The m-bit parallel data from the buffer memory is input to a second buffer memory to form an m-bit parallel frame synchronization format.

The frame synchronization format is inputted from the second buffer memory to the third buffer memory in the parallel/serial conversion circuit, and the third buffer memory converts the parallel/serial format in units of (m/k) bit parallel. The k serial frame synchronization formats formed by the conversion are sent to each of the k output terminals.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, since data is processed in parallel, the processing speed can be reduced compared to serial processing. Therefore, a frame synchronization forming circuit can be realized without using high-speed circuit elements or having a complicated configuration. By not using high-speed circuit elements, power consumption can be reduced, and the simple circuit configuration reduces the number of parts and makes the circuit smaller.

Furthermore, parallel data can be divided into multiple channels and then output as serial data.
By setting the parallel data speed, number of parallel bits, and number of divided channels to appropriate values, it is possible to match the speed of the output serial data to the speed of the digital transmission hierarchy, making it compatible with the digital transmission hierarchy. transmission lines can be used. Therefore, there is no need to provide an additional circuit for connecting to the transmission line, and it is possible to simplify the circuit, reduce power consumption, and improve reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Input terminal, 2...Serial clock input terminal, 3...Control clock circuit, 4...Signal control circuit, 5...Pattern generation circuit, 6...Signal synthesis circuit, 7...Parallel/serial conversion circuit, 8,
9... Output terminal, A... Parallel clock, B...
...Input parallel data, C...Read clock,
D...Parallel data, E...Pattern clock, F...Frame synchronization pattern, G...Selection clock, H...Parallel frame synchronization format, I...Serial clock, J, K...Serial frame synchronization format .

Claims (1)

[Claims] 1 m bit parallel data is set as 1 block,
One frame is parallel data of m rows and n columns consisting of n blocks, and m of s frames.
A parallel frame synchronization pattern consisting of 1 block is added immediately before each multiframe to input data in which parallel data of rows (n × s) columns constitute one multiframe, and m rows (n × s × l) A signal control circuit which forms a time slot for a parallel frame synchronization pattern immediately before each multi-frame in order to form a parallel frame synchronization format consisting of parallel data of a column, and outputs parallel data having the time slot; The parallel frame synchronization pattern output from the pattern generation circuit is inserted into the time slot of the parallel data output from the pattern generation circuit that generates the parallel frame synchronization pattern and the signal control circuit and synthesized. A signal synthesis circuit for forming a frame synchronization format is provided, and in order to convert the parallel frame synchronization format into a k-channel serial frame synchronization format and output it, the parallel frame synchronization format outputted from the signal synthesis circuit is k
The system is equipped with a parallel/serial conversion circuit that divides the data into four channels, performs a parallel/serial conversion operation for each divided channel, and outputs it to k output terminals as a serial frame synchronization format, and operates the four circuits. 1. A frame synchronization forming circuit comprising a control clock circuit that generates various clock signals for controlling the frame synchronization.