JPH0330907B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a transistor circuit, and more particularly to a transistor circuit that multiplies four analog signals.

[Background of the invention]

One of the methods of transmitting a digital signal on a carrier wave is called a four-phase phase modulation method.
This is a modulation method that changes the phase of the carrier wave by 0°, 90°, 180°, and 270° for every 2 bits of the input digital signal. When demodulating such a modulated signal, the demodulator side oscillates with a reference constant phase, and uses this to phase-detect the input signal.
It is configured to obtain a bit digital signal.

The phase of the input signal to the demodulator is constantly changing due to modulation, and the Costas loop method is one of the methods for reproducing the reference constant phase oscillation output from this signal. In this method, the first demodulated signal P, the second
The demodulated signal Q, their sum signal P+Q, and their difference signal P-Q are all multiplied, and the output is applied to a voltage controlled oscillator to perform reference constant phase oscillation.

Conventionally, a so-called double differential circuit has been known as a circuit that multiplies two signals, and therefore,
By using three of these, a four-signal multiplication circuit can be obtained as shown in FIG. First, second and third double differential circuits 29, 31 and 26
The first bi-differential circuit 29 has a transistor 1
~6. Consisting of a constant current source 28 and loads 19, 20, the product of the first and second two signal sources 26 and 27 containing a predetermined bias is generated in the loads 19, 20. This signal is level-shifted by a level shift circuit 38 and applied to one input terminal of a second bi-differential circuit 31 at the next stage. A third signal source 30 is connected to the other input of this circuit 31, so that the product of the output of the first circuit 29 and the signal source 30 appears at the loads 21, 22. Note that the second double differential circuit 3
1 is composed of transistors 7 to 12, a constant current 32, and loads 21 and 22. The product signal obtained from the output of the circuit 31 is further applied to one input terminal of a third bi-differential circuit 36 at the next stage via a level shift circuit 39, where the signal source connected to the other input is applied. 33 occurs at loads 23, 24 and appears at terminals 34, 35. Here, the third bi-differential circuit 36 includes transistors 13 to 18, a constant current 37, and loads 23 and 24. Note that 25 is a power source.

As shown below, the output terminals 34 and 35 have (signal source 26) x (signal source 27) x (signal source 30) x (signal source 3
The signal 3) will be generated. Signal source 26,2
7, 30 and 33 are the aforementioned P signal, Q signal, and a circuit (not shown) for producing the sum of these signals, respectively.
A predetermined bias voltage is superimposed on the output signal P+Q of the circuit and the output signal P-Q of the difference generating circuit (not shown), thereby obtaining the reference constant phase oscillation signal used for the above-mentioned demodulation. can.

With the above configuration, a circuit that generates the product of four signals can be realized, but this has the following drawbacks.
The first is that the motion is not very fast. This is because the delay in the time constant due to the load resistances 19 to 24 of each stage and the stray capacitance at this point is added over the three stages, and the two level shift circuits 3
This is because there is a delay in the signal at 8 and 39. Second, it consumes a lot of power. This is because the three constant current sources 28, 32 and 37 and the two level shift circuits 38 and 39 require power consumption. Thirdly, a large number of elements are required.

[Purpose of the invention]

An object of the present invention is to provide a transistor circuit suitable for multiplication of four signals, which improves operating speed, reduces current consumption and the number of elements.

[Structure of the invention]

According to the present invention, each has a first input terminal pair, a second input terminal pair, an output terminal pair, and first to fourth transistors, and one of the first input terminal pairs has the first and second input terminal pairs. The emitter of the second transistor is connected to the other of the first input terminal pair, the emitters of the third and fourth transistors are connected to the other of the first input terminal pair, and the bases of the first and fourth transistors are connected to one of the second input terminal pair. The bases of the second and third transistors are at the other of the pair of input terminals, the collectors of the first and third transistors are at one of the pair of output terminals, and the collectors of the second and fourth transistors are at the other of the pair of output terminals. The circuit blocks are stacked vertically such that the output terminal pair of the previous stage circuit block is connected to the first input terminal pair of the next stage, and the circuit blocks of the first stage are connected to each other. At least one of the first pair of input terminals and at least one of the second pairs of input terminals from the first circuit block to the final circuit block each receive a signal, and each of the second input terminal pairs from the first circuit block to the final circuit block receives a signal. A transistor circuit is obtained in which an output is taken out from at least one of the output terminals of the transistor circuit.

[Embodiments of the invention]

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 2 shows an embodiment of the invention. This circuit consists of three differential amplifier circuits 101, 102 and 104.
, a 4-signal multiplication circuit 103 and a bias circuit 105
It is composed of. The differential amplifier circuit 101 is
Transistors 109, 110, emitter resistor 11
1,112, constant current source 114 and load resistance 115
It consists of garlic. A bias is applied to the base of the transistor 110 from a bias power supply 153, and a resistor 113 is applied to the base of the transistor 109.
A bias is applied from the bias power supply 153 via the capacitor 107 and the input terminal 10.
A signal P from a signal source 106 is input via 8. By selecting the sum of resistors 111 and 112 and the value of resistor 115 to be approximately equal, the load resistor 115
A signal with the same phase and approximately the same level as signal P can be obtained. The differential amplifier circuit 102 includes transistors 116 and 117 and emitter resistors 118 and 11.
9, a constant current 120, and a load resistor 121. If the actual circuit numbers are set in the same way as the differential amplifier circuit 101, the load 121 can obtain a signal having a level that is almost the same in phase as the signal P. Differential amplifier circuit 10
4 is composed of transistors 141, 142, emitter resistors 143, 144, bias resistor 148, and load resistors 146, 147. A signal Q from a signal source 156 is input to the base of the transistor 142 via a capacitor 115 and an input terminal 154, and a bias voltage is further supplied from bias waves 152 and 153 via a resistor 148.
Therefore, a signal that is in phase with the signal Q is generated at the load resistor 146, and a signal that is in phase opposite to the signal Q is generated at the load resistor 147 at approximately the same level.

The 4-signal multiplication circuit 103 includes a constant current source 140 and transistors 138 and 13 that constitute a differential amplifier.
9, load resistance 124, 125, transistor 13
The circuit block includes a first circuit block consisting of transistors 4 to 137, a second circuit block consisting of transistors 130 to 133, and a third circuit block consisting of transistors 126 to 129. A signal P is input to the base of the transistor 138, and this transistor 138 is connected to the transistor 139.
Since this constitutes a differential amplifier circuit, transistor 1
At the collectors 38 and 139, signals having the same phase and the opposite phase of the signal P appear, respectively. Since the signal Q is applied to the bases of the transistors 135 and 136 constituting the first circuit block, the transistors 134 to 139 operate as a conventional bidifferential circuit, and the outputs of the transistors 134 and 139 operate as a conventional bidifferential circuit. 1
36 collector currents and transistor 13
As the sum of the 5,137 collector currents, a current corresponding to the signal P×signal Q and its reverse phase current are obtained. Since these currents have opposite phases to each other, they are equivalent to the output current when a signal "signal P×signal Q" is created in advance and applied to the input of another differential amplifier. Therefore, by applying the output current of the first circuit block to the second circuit block, the differential amplifier circuits 101 and 101 which are audibly applied to the bases of the transistors 130 to 133 constituting the second circuit block. 104
(as described above, a signal in phase with the input signal P and signal Q signal) and the output signal of the first circuit block described above (signal P x signal Q as described above)
(equivalent to), that is, signal P x signal Q x (signal P - signal Q) is obtained. The output of the differential amplifier 102 ((in phase with the signal P as described above) is connected to the base of each of the transistors 126 to 129 constituting the third circuit block.
and the output of the differential amplifier 104 (as described above, the signal Q
Since the signals (with opposite phase and negative phase) are applied differentially, the current corresponding to the product of this and the output current of the second circuit block is applied differentially, using the same principle as above, that is, signal P x signal Q x (signal P - Signal Q) × {(Signal P-(-Signal Q)} The corresponding signal becomes the output current of the third circuit block. This generates an output voltage across the load resistors 124 and 125, which is output from the output terminals 122 and 123 as an output. It goes without saying that this signal is proportional to the following: signal P x signal Q x (signal P - signal Q) x (signal P + input signal Q). Although shown as voltage sources 149 to 153 that generate such voltages, any circuit that generates such voltages may be used.For example, it may be constructed from a combination of diodes and/or resistors.

According to the present invention, the four-signal multiplier circuit 103 has only one set of loads and does not have a level shift circuit, so it can operate at a higher speed than the one shown in FIG. Note that the differential amplifiers 101, 102 and 104
Although not shown in FIG. 1, they are similarly necessary as circuits for creating the sum and difference of the signal P and the signal Q. In addition, the 4-signal multiplication circuit 103
The current is only from the constant current source 140, which is 1/3 of the current in the circuit shown in Figure 1, and furthermore,
The number of elements may also be smaller than that of FIG. 1 by at least the level shift circuit.

FIG. 3 shows another embodiment of the present invention, and the same parts as in FIG. 3 are given the same numbers. Signal P from signal source 106 is connected to the base of transistor 202 forming an emitter follower via capacitor 107 and input terminal 108, and a signal in phase with signal P is generated at the emitter of transistor 202. The diodes 203 to 208 are for level shifting, and have a potential difference of approximately 0.7 V in direct current, and have low impedance in alternating current, so that a signal in phase with the signal P is generated at each part of the diodes 203 to 208. Note that 209 is a constant current source, and the voltage of the bias source 231 is applied to the transistor 202 via the resistor 201. Similarly, signal Q from signal source 156 is applied to capacitor 155.
It is connected to the base of the transistor 211 constituting the emitter follower via the input terminal 154, and its emitter is connected to the level shift diode 2.
12-217 to a constant current source 218, and its base is biased via a resistor 210. Also, a transistor 22 whose base is connected to a bias power supply 231 by a resistor 219
0, and level shift diodes 221 to 226 and constant current source 227 connected to the emitter thereof.
There is a bias circuit consisting of 232 is a power source. The 4-signal multiplier circuit 103 is the same as that shown in FIG.

A signal in phase with the signal P is applied to the base of the transistor 138 together with a bias, and a signal in phase with the signal Q is applied together with a bias to the base of the transistor 228. transistor 13
Since transistors 5 and 228 constitute a differential amplifier together with transistors 139 and 229, respectively, transistor 1
The sum of the collector currents of transistors 38 and 228 and the sum of the collector currents of transistors 139 and 229 are a sum signal (P+Q) of signal P and signal Q, respectively, and a signal in reverse phase thereof. A signal in phase with the signal Q is applied together with a bias to the bases of the transistors 134 to 137 constituting the first circuit block. A signal having the same phase as the signal P is applied together with a bias to the bases of the transistors 130 to 133 constituting the second circuit block. Furthermore, the third
The transistors 126 to 126 constituting the circuit block of
A signal in phase with signal P and a signal in phase with signal Q are differentially applied to the base of 129. Therefore, in the same manner as described in FIG.
It can be seen that a voltage proportional to (signal P+signal Q)×signal Q×signal P×(signal P−signal Q) is generated at 22 and 123. Needless to say, this is exactly the same as the output shown in FIG.

In addition to the same features as the embodiment shown in FIG. 2, the circuit shown in FIG. It is characterized by less signal lag.

As described above, according to the present invention, four high speed and low current consumption
A signal multiplier circuit is obtained. Note that the gist of the present invention is not necessarily limited to multiplication of four signals, and can generally be used as a multistage multiplication circuit.
Furthermore, since it is a multiplication circuit, it goes without saying that even if the order of applying which signal to which stage is changed, exactly the same output can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a transistor circuit based on a combination of conventional techniques, FIG. 2 is a circuit diagram showing one embodiment of the present invention, and FIG. 3 is a circuit diagram showing another embodiment of the present invention. . 29, 31, 36...double differential circuit, 38, 39
...Level shift circuit, 26, 27, 30, 33
...Input signal source, 34, 35...Output terminal, 10
1, 102, 104...Differential amplifier circuit, 106...
...Signal P, 156...Signal Q, 122, 123...
...Output terminal, 202, 211... Emitter follower transistor, 203-208, 212-21
7,221-226...level shift diodes.

Claims (1)

[Scope of Claims] 1. Each transistor has a first input terminal pair, a second input terminal pair, an output terminal pair, and first to fourth transistors, and one of the first input terminal pair has the above-mentioned transistor. The emitters of the first and second transistors are connected to the other of the first input terminal pair, the emitters of the third and fourth transistors are connected to the other of the second input terminal pair, and the emitters of the third and fourth transistors are connected to one of the second input terminal pair. The bases of the transistors are connected to the other of the second pair of input terminals, the bases of the second and third transistors are connected to the other of the pair of output terminals, the collectors of the first and third transistors are connected to one of the pair of output terminals, and the collectors of the first and third transistors are connected to the other of the pair of output terminals. On the other hand, a plurality of circuit blocks are provided in which the collectors of the second and fourth transistors are respectively coupled, and the output terminal pair of the circuit block in the previous stage is connected to the first input terminal pair in the next stage. At least one of the first input terminal pair of the first stage circuit block and at least one of the second input terminal pairs of each of the first stage circuit block to the final stage circuit block 1. A transistor circuit, wherein each of the transistor circuits receives a signal, and an output is taken out from at least one of the output terminals of the final stage circuit block. 2. The first input signal, the second input signal, their sum signal, and their difference signal are obtained from at least one of the pair of output terminals of the final stage circuit block. and a signal based on the second input signal to at least one of the first pair of input terminals of the first-stage circuit block and each of the second input terminals from the first-stage circuit block to the final-stage circuit block. 2. The transistor circuit according to claim 1, wherein said transistor circuit is supplied to at least one of said pairs.