JPH033234B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention aims to improve brightness, contrast, etc. in an image display device using a display element without a memory function, such as a discharge display tube, liquid crystal, light emitting diode, or fluorescent display tube. It is something to do.

A display device using the display element as described above is configured as follows, for example.

In FIG. 1, 1 is a display element. For example, m display elements 1 are arranged in a matrix in the X-axis direction (horizontal direction) and n in the Y-axis direction (vertical direction), and one electrode of the display element 1 is sequentially connected in the Y-axis direction. From this connection point, terminals x ₁ , x ₂ . . . x _n are derived for each column. Further, the other electrodes of the display element 1 are sequentially connected in the X-axis direction, and terminals y ₁ , y _{2 ,} . . . , y _o are led out for each column from this connection point.

Reference numeral 2 denotes, for example, a microcomputer, and the computer 2 performs arithmetic processing in accordance with data and programs inputted from a keyboard 3 or the like.

Furthermore, 4 is a random access memory (RAM) for display, and the number of display elements 1 (m
×n), and the computer 2
Storage is performed at an address corresponding to the display element 1 to be displayed in accordance with a part of the content such as the processing result.

An output terminal is provided for each memory address of this RAM 4 corresponding to one line in the X-axis direction, and this output signal is supplied to the output control circuit 5. Furthermore, this output control circuit 5 receives a signal from the computer 2.
A line synchronization signal is supplied every time a line is displayed, and according to this synchronization signal, one line is sequentially stored in the RAM from the memory address corresponding to the highest line.
The contents of 4 are read out.

This read signal is supplied to a shift register 6 having a number of stages equal to the number m of display elements 1 constituting one line, and this shift register 6
The signals of each stage are supplied to the latch circuit 7, and the above-mentioned line synchronization signal is also supplied to the latch circuit 7 to perform latching. These latched signals are supplied to terminals x ₁ -x _n through drive circuit 8, respectively.

Further, a line synchronization signal is supplied to a shift terminal of a shift register 9 having the number of stages equal to the number of lines n, and "1" signals are sequentially shifted from the highest stage in synchronization with this synchronization signal.
These signals are supplied to the terminals y ₁ to _yo through the drive circuit 10, respectively.

Therefore, in this device, the contents of RAM4 are 1
Each line is read out and supplied to the terminals _x1 to _xn , and the line is driven in accordance with the read line to display the contents of the RAM 4.

Furthermore, in this device, the shift register 9 generally includes the Q output terminals of n D-type flip-flops 90 ₁ , _{90 2} .
The input terminals are sequentially connected in series, and the Q output terminal of the final stage flip-flop _90o is connected to the D input terminal of the first stage flip-flop ₉₀₁ .
In the initial state, flip-flop 90 ₁ is inverted, the Q output terminal is set to "1", and the above-mentioned line synchronization signal is supplied to the clock terminals of flip-flops 90 ₁ to 90 _o . Therefore, each time the clock signal is applied, the flip-flop 90 ₂
~90 _o are inverted in turn and flip-flop 9
The flip-flop ₉₀₁ is inverted at the next line synchronization signal in which _0o is inverted. The Q output terminals of the flip-flops 90 ₁ to 90 _o are connected to terminals y ₁ to _yo , respectively.

However, in such devices, display elements that do not have a memory function, such as the above-mentioned discharge display tube, liquid crystal, light emitting diode, fluorescent display tube, etc., have low display brightness and poor contrast. On the other hand, in the above-mentioned circuit, since each of the n lines is displayed in turn, each display element only displays for 1/n of the total time, further reducing the brightness and contrast. Ta.

In view of these points, the present invention aims to improve brightness and contrast with a simple configuration.

By the way, when the above-mentioned display device is used as an output device of a computer, two types of display formats can be considered: a so-called graphic display and a character display. That is, in a graphic display for displaying figures and the like, the display is performed over almost all lines of the display surface, as shown in FIG. 3A.
On the other hand, in the character display for displaying characters, etc., as shown in FIG. 3B, the lines between each line are not displayed. Also, in graphic displays, the display may not cover all lines. The present invention focuses on this point.

That is, in the present invention, display elements having no memory function are arranged in a matrix in the X-axis and Y-axis directions, and image signals are sequentially supplied line by line in the X-axis direction, and lines are sequentially supplied in the Y-axis direction. In a device configured to select and display an image, the image signal is supplied and the line is selected by skipping lines that are not displayed, depending on the content of the image signal.

Therefore, according to the present invention, the display time of each display element is 1/l (l is the number of lines performing display), and since l<n, the display time becomes long. As the display time becomes longer, the brightness of each display element increases and the contrast also improves.

Thus, according to the present invention, the brightness and contrast of the display can be improved.

Hereinafter, specific circuits for achieving the present invention will be further explained with reference to the drawings.

Incidentally, improvements in brightness and contrast are particularly desired in character displays. Therefore, FIG. 4 shows a case where the lines between lines are skipped when displaying characters. Here, in the character display, it is assumed that each line of characters is displayed using p lines, and the line spacing is composed of q lines.

In the figure, the shift register 9 is divided into q stages and p stages alternately. The Q output terminal of each final stage of the shift registers 91 ₁ , 91 _{3 . .} . of the q stage is connected to the D input terminal of the first stage of the next p stage shift register 91 ₂ , 91 ₄ . shift register 91 ₂ ,
The Q output terminals of each final stage of 91 ₄ . . . are connected to the movable contacts of changeover switches 92 ₁ , 92 ₂ . The fixed contacts of one of the switches 92 ₁ , 92 ₂ . . . are connected to the shift registers 91 ₃ , 91 ₅ . . . of the next q stage.
is connected to the D input terminal of the first stage, and the other fixed contact is connected to the shift register 91 ₄ , 91 ₆ of the next p stage.
It is connected to the D input terminal of the first stage of... The other fixed contact of the changeover switch _92s connected to the Q output terminal of the final stage of the shift register (91r _-1 ) of the final p stage is connected to the D input terminal of the first stage of the shift register ₉₁₂ of the first p stage. Connected. Further, the Q output terminal of the final stage of the shift register 91 _r of the final q stage is connected to the D input terminal of the shift register 91 ₁ of the first q stage. Others are first
Connected as shown in the diagram.

Therefore, in this circuit, when displaying graphically, by switching the switches 92 ₁ to 92 _s to one fixed contact side, the shift registers 91 _{1 to 92 s} are switched to one fixed contact side.
91 _r are all connected in series, resulting in the same effect as in FIG. 1 described above. On the other hand, in the case of character display, only the shift registers 91 ₂ , 91 ₄ . . . 91 _r-1 of the p stage are connected in series by switching the switches 92 ₁ to 92 _s to the other fixed contact side. Therefore, among the lines of the display element 1, only the lines corresponding to each row are sequentially driven.
Then, by sequentially reading out only the memory addresses corresponding to each row in the output control circuit 5, each row is displayed on a predetermined portion of the display element 1.

In this manner, in this circuit, when displaying characters, image signals are supplied and lines are selected by skipping lines that are not displayed, and a display with improved brightness and contrast is performed.

Furthermore, Figure 5 shows the RAM 4 corresponding to each line.
This shows the case where the contents of the memory address of are detected and line skipping is performed accordingly.

In the figure, the output signals of each line of the RAM 4 are supplied through the output control circuit 11 to the set terminals of flip-flops 12 ₁ , 12 ₂ . . . 12 _o , respectively. The switches 92 ₁ -92 _o between the respective stages of the shift register 9 are controlled by the output signals of the flip-flops 12 ₁ -12 _o , respectively.

As _shown in _FIG .
Switches 92 ₁ to 92 _o similar to those shown in the figure are provided.

A signal returned from the output side of the flip-flop 90 _o at the final stage of the shift register 9 to the input side of the flip-flop 90 ₁ is supplied to the control terminal of the output control circuit 11 and the reset terminals of the flip-flop circuits 12 ₁ to 12 _o .

Furthermore, the output signals of flip-flops 12 ₁ to 12 _o are supplied to a decoder 13, and the decoded output is supplied to an output control circuit 5. Also decoder 1
The output signal No. 3 is supplied to the limiter 14, and the drive circuit 10 is controlled by this limiter output.

And in this circuit, flip-flop 9
When the signal on the output side of _0o becomes "1", the flip-flops 12 ₁ to 12 _o are reset, and the signals on each line of the RAM 4 are read out at high speed to set the set terminals of the flip-flops 12 ₁ to 12 _o . supplied to For this reason, when this readout is completed, the flip-flop 1 of the line with the signal is
2 ₁ to 12 _o become "1", and flip-flops 12 ₁ to 12 _o of lines with no signal become "0".

When the flip-flops 12 ₁ to 12 _o are "1", the corresponding switches 92 ₁ to 92 _o are switched to one fixed contact side, and when they are "0", the corresponding switches 92 1 to 92 o are switched to the other fixed contact side.

Furthermore, the output signals of the flip-flops 12 ₁ to 12 _o are supplied to the decoder 13, and this decoded output is supplied to the output control circuit 5, so that the contents of the lines in which the flip-flops 12 ₁ to 12 _o are "1" are sequentially read out. It will be done like this.

Furthermore, flip-flop 1 from decoder 13
A signal corresponding to the number of "1" in 2 ₁ to 12 _o is supplied to the limiter circuit 14, and when the number of "1" is less than a predetermined value, the drive circuit 10 is controlled so that the brightness and contrast do not rise too much. .

Therefore, in this circuit as well, image signals are supplied and lines are selected by skipping lines that are not displayed.

Thus, according to the present invention, brightness and contrast can be improved with an extremely simple configuration.

[Brief explanation of the drawing]

1 and 2 are configuration diagrams of a conventional device, FIG. 3 is a diagram for explaining the present invention, FIG. 4 is a configuration diagram of an example of a specific circuit of the present invention, and FIGS. 5 and 6. is a configuration diagram of another example. 91 ₁ to 91 _r are shift registers, 92 ₁ to 92 _s
is a switch.

Claims (1)

[Claims] 1 Display elements without memory function are placed on the X-axis and Y-axis.
In a device arranged in a matrix in the axial direction, image signals from an image memory are sequentially supplied line by line in the X-axis direction, and images are displayed by sequentially selecting lines in the Y-axis direction. By providing a switching circuit that substantially drives only the stage on which display is performed by controlling a shift register that discriminates the content of the image signal and sequentially selects lines in the Y-axis direction, A driving method for an image display device in which the image signal is supplied and the line is selected by sequentially skipping the lines that are not displayed.