JPH0332817B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is designed to correctly disassemble the execution of a transfer instruction (hereinafter referred to as MOVES instruction) that specifies a segment in the 16-bit microprocessor MC68010 manufactured by Motorola. The present invention relates to a transfer instruction detection circuit that detects the execution cycle of the transfer instruction and generates a signal used when performing disassembly.

(Prior art) Like the MC68000 manufactured by the same company, the MC68010 has a fetish (identified by program reference, which is identified by decoding function codes FC0 to FC2 issued from the processor) in cycles of program reference (identified by decoding function codes FC0 to FC2 issued from the processor). By taking the instruction code into the processor and managing the number of execution cycles, it is possible to disassemble the operations of the processor.

(Problem to be Solved by the Invention) In the MC68010, in the MOVES instruction, depending on the value of a register inside the processor, memory read and/or memory write during the execution cycle is performed instead of data reference. Although it is possible to operate as a program reference, in this case, there is a problem that disassembly becomes abnormal because the instruction code fetched in the program reference cycle becomes unmanageable.

In view of these points, the purpose of the present invention is to
Detects memory read and write cycles of instructions, generates a signal that forces the cycle to be a data reference cycle, and obtains the signal used to correctly disassemble the execution of the MOVES instruction. An object of the present invention is to provide a transfer command detection circuit.

(Means for solving the problem) In order to achieve such an objective, the present invention has the following features:
A means for detecting a MOVES instruction and determining which cycle is a memory read or memory write cycle, a counter for counting instruction execution cycles, and a cycle to be forcibly made into a data reference from the output of the means and the counter. It is equipped with a circuit that generates a signal indicating a data reference cycle, and a circuit that uses the output of this circuit to convert a function code into a data reference code. It is characterized by being configured to create and output.

(Example) The present invention will be explained in detail below using the drawings. FIG. 1 is a block diagram of main parts showing an embodiment of a transfer command detection circuit according to the present invention. In the figure, 1 is
The MOVES instruction detection circuit receives data output from the MC68010 via the data bus DB (16 bits D0 to D15), and when a MOVES instruction is detected, outputs MOVES #2 to #5 signals during the execution cycle. 2 is the bus cycle counter,
Clock CLK output from MC68010 side
(1 pulse generated in synchronization with read and write operations of MC68010)
Output once per cycle. ) to count the number of cycles of instruction execution.

3 is MOVES instruction detection circuit 1 and bus cycle.
This is a data reference detection circuit that generates a data signal indicating a data reference cycle from the output of the counter 2.

4 is a function/code conversion circuit (hereinafter referred to as
The FC conversion circuit partially converts the data of the function codes FC0 to FC2 given from the MC68010 according to the output data of the data reference detection circuit 3, and outputs them as FC'0 to FC'2.

The operation in such a configuration will be explained next with reference to FIG. The MOVES instruction has three execution cycles, the second cycle of which is a memory read/write cycle, and the operation when memory access is performed as a program reference will be described. In the MOVES instruction detection circuit 1,
When a MOVES instruction is detected, signals MOVES #2 to #5 are output during the execution cycle depending on the addressing mode and the size of data to be handled. In the case of Figure 2, there is a memory access in the second cycle, so as shown in Figure C, MOVES#2
set to High level (hereinafter referred to as "H").

On the other hand, bus cycle counter 2 is clocked.
Count CKL and refer to the value as data detection circuit 3
give to Bus cycle counter 2 counts up at the rising edge of clock CKL and is cleared in the last cycle of instruction execution.

The data reference detection circuit 3 generates a data signal indicating a data reference cycle from the output of the MOVES command detection circuit 1 and the output of the bus cycle counter 2. In the case of this embodiment, since MOVES #2 is output, the data signal is output in the second cycle, that is, in the section where the value of counter 2 is 1, as shown in Figure 2 D. . When the data signal given from the data reference detection circuit 3 is "H", the FC conversion circuit 4 sets FC'0 to "H" and FC'1 to "L" (Low), as shown in FIG. level)
, and the other FC′0 and FC′2 output FO0 and FC2 as they are. Such FC′0～FC′2
is a data reference code, and by using this signal, disassembling can be performed correctly.

Note that the above operation is for the case where the MOVES instruction has 3 execution cycles, but in cases other than 3 cycles, data reference is similarly indicated in the memory read or memory write cycle.
Can generate FC signal.

Since a signal indicating data reference can be created in this way, the MOVES instruction can also be disassembled using the same method as other general instructions.

(Effects of the Invention) As explained above, according to the present invention, the signals necessary for disassembling the MOVES instruction of MC68010 can be easily obtained using a simple circuit, and the effects of the present invention can be achieved by using a simple circuit. is large.

[Brief explanation of the drawing]

FIG. 1 is a main part configuration diagram showing an embodiment of a transfer command detection circuit according to the present invention, and FIG. 2 is a time chart for explaining the operation. 1... MOVES command detection circuit, 2... Bus cycle counter, 3... Data reference detection circuit, 4...
Function code conversion circuit.

Claims (1)

[Claims] 1 Receives the necessary data from the microprocessor, which is configured so that the fetched instruction code cannot be managed from outside while a transfer instruction that specifies a segment is being executed, and detects that the transfer instruction specifies a segment. a MOVES detection circuit that outputs a signal indicating which cycle is a memory read or memory write, and a bus cycle counter that counts clocks from the microprocessor and outputs a count value corresponding to the bus cycle. , a data reference detection circuit that generates a signal indicating a cycle to be forcibly made data reference from the output of the MOVES detection circuit and the output of the bus cycle counter; The function code conversion circuit converts the output signal of the reference detection circuit into a data reference code. A transfer command detection circuit is characterized in that a signal having a cycle of is obtained.