JPH0332822B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a microcomputer system, and more particularly to a failure detection technique thereof.

Prior art and its problems In microcomputer systems, a memory protection circuit is often provided to prevent important information stored in random access memory (hereinafter referred to as "RAM") from being rewritten. be.

However, simply by providing a memory protect circuit, if the memory protect circuit fails, the system cannot detect it. Therefore, if a protect error occurs after the memory protect circuit has failed, the abnormality cannot be detected, and the system mistakenly assumes that the memory protect circuit is normal and operates, resulting in a double failure. There was a problem with the transition to .

Purpose of the present invention The present invention solves the above-mentioned conventional problems,
It is an object of the present invention to provide a microcomputer system in which the function of a memory protection circuit is periodically inspected to prevent malfunction due to overlooked protection errors and to prevent transition to a double failure.

Structure of the Present Invention In order to achieve the above object, the present invention provides a microcomputer system having a memory protect circuit that prevents rewriting of information stored in memory, in which data that will cause a protect error is set in advance, and data that causes a protect error is periodically set. The memory protection circuit is characterized in that the normality or abnormality of the memory protection circuit is monitored by writing a protection error to the memory protection circuit and confirming that the protection error is detected.

Embodiment FIG. 1 is a block diagram of a microcomputer system according to the present invention. In the figure, 1 is a microcomputer (hereinafter referred to as "CPU");
2 is a RAM, and 3 is a read-only memory (hereinafter referred to as "ROM"). The RAM 2 is divided into several areas by dividing addresses, and protection can be set/cancelled for each area.

Reference numeral 4 denotes a memory protect circuit that prevents the information stored in the protected area of the RAM 2 from being rewritten. The memory protect circuit 4 includes a protect instruction latch circuit 40, a protect area selection circuit 41, AND gates 42 and 43, an inverter 44, and the like. The protection instruction latch circuit 40 is a circuit that stores protection setting/cancellation for each area of the RAM 2, and its contents can be changed by receiving data from the CPU 1. Further, the protect area selection circuit 41 selects a protect area based on the protect instruction signal given from the protect instruction latch circuit 40 and the address signal given from the CPU 1, and if the area is writable, a logic "1" is set. Output.

5 is a transformer-coupled AC amplifier circuit, 6 is a rectifier circuit, 7 is a relay, 71 is a contact thereof, and 8 is a power source. 9 is an address bus, 10 is a data bus, 11
is an interrupt signal line.

Next, the operation will be explained with reference to the flowcharts of FIGS. 2a and 2b. First, according to the software, normal process processing and failure checking of the memory protect circuit 4 are periodically and alternately performed at fixed time intervals. When the normal processing is completed, the software is checking the memory and protection circuit 4, as shown in FIG. 3a. Data that will cause a protect error is set in advance in the CPU 1, and when the software is checking the memory protect circuit 4,
This data is periodically written to the protect instruction latch circuit 40 through the data bus 10. In the protect area selection circuit 41, CPU1
A protect area of the RAM 2 is selected based on an address signal applied from the RAM 2 through the address bus 9 and a protect instruction signal applied from the protect instruction latch circuit 40. If the selected area is writable, a logic "1" is output to the signal line 12 and input to the AND gate 43 through the AND gate 42 and the inverter 44.

On the other hand, when writing data to the RAM 2, a memory/write signal of logic "1" (hereinafter referred to as "M/W signal") is input from the CPU 1 to the AND gate 42 through the signal line 13, and the protected area is selected. A check of circuit 41 is performed. Here, if the area selected by the protect area selection circuit 42 is writable, the logic "1" signal is output from the protect area selection circuit 42 to the signal line 12 as described above, so that the AND gate 42 Input conditions are correct, AND gate 4
A WE signal indicating that data can be written to the RAM 2 is inputted from the RAM 2 through the signal line 14. Note that the M/W signal of logic "1" is also input to the AND gate 43, but before the AND gate 43, the inverter 4
4 is connected, the output of AND gate 43 is logic "0".

However, if writing is disabled, the M/W signal applied from the CPU 1 to the AND gate 42 through the signal line 13 becomes logic "0", and the AND gate 4
Since the input condition is not satisfied on the 2 side, the WE signal is not generated, but the input condition is satisfied on the AND gate 43, an interrupt signal is generated on the output side of the AND gate 43, and a protect error is detected. This interrupt signal is input to CPU1 through signal line 11,
As shown in the flowchart of FIG. 3b, it is determined whether or not the memory protect circuit is being checked. Software can determine whether or not the memory protect circuit is being checked. If the result is ``YES'', the memory protect circuit check process is canceled and the process moves to the next process processing software.

On the other hand, if the result of the above determination is "NO", it is determined that the memory protect circuit 4 is abnormal because the interrupt signal was generated even though the memory protect circuit was not being checked.
Execute the stop command.

As mentioned above, if the memory protection circuit 4 is normal, normal process processing and memory protection circuit check processing are performed periodically at fixed time intervals, and an interrupt is generated each time memory protection circuit check processing is performed. A signal is generated. Therefore, the output of the memory protect circuit 4 becomes a pulse train, and the AC signal amplified by the transformer-coupled AC amplifier circuit 5 is input to the rectifier circuit 6, and since a rectified output is obtained from the rectifier circuit 6, the relay 7 is tripped. Up,
The contact 71 inserted and connected in series to the power supply 8 closes,
It is connected to CPU1 and power is supplied to it.

On the other hand, if a protect error cannot be detected because the memory protect circuit 4 has failed, no interrupt signal is generated and the output of the memory protect circuit 4 does not become a pulse train, so the output of the transformer-coupled amplifier 5 is A constant DC level or no output. Further, even when a stop command is executed according to the software, the output of the memory protect circuit 4 does not become a pulse train. Therefore, in these cases, no rectified output is obtained from the rectifier circuit 6 and the relay 7 falls, so its contact 71 opens and the power supply to the CPU 1 is cut off, causing the CPU 1 to continue operating without abnormal operation. Stop.

Effects of the Invention As described above, the present invention provides a microcomputer system having a memory protection circuit that prevents rewriting of information stored in a memory.
By setting data that will cause a protect error in advance, writing a protect error periodically, and confirming that this protect error is detected, the normality of the memory protect circuit can be confirmed.
Since it is characterized by monitoring abnormalities, memory
It is possible to provide a microcomputer system in which the function of the protect circuit is periodically inspected to prevent malfunctions due to missed protection errors and to prevent transition to double failure.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microcomputer system according to the present invention, and FIGS. 2a and 2b are flowcharts of the microcomputer system according to the present invention. 1... Microcomputer (CPU), 2...
Random access memory (RAM), 4...
Memory protect circuit, 40...protect instruction latch circuit, 41...protect area selection circuit.

Claims (1)

[Claims] 1. In a microcomputer system that has a memory protect circuit that prevents the rewriting of information stored in memory, data that will cause a protect error is set in advance, a protect error is generated periodically, and this protect error is detected. By making sure that the memory
A microcomputer system characterized by monitoring whether a protection circuit is normal or abnormal.