JPH0332936B2 - - Google Patents

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Working Example (a) One Implementation Explanation of the configuration of an example (Fig. 2) (b) Explanation of the operation of one embodiment Effects of the invention [Summary] In a timing synchronization method in which a timing component is extracted from an input signal and a synchronized operation is performed, the extracted timing component is By providing a phase hold step that holds the timing component when the threshold is exceeded and outputs the held timing component when the timing component is below the threshold, synchronized operation can be performed even if the timing component is small. It is.

[Industrial application field]

The present invention relates to a timing synchronization method for synchronizing the phase and frequency of a timing signal included in a received signal in a modem receiving section, etc., and in particular can prevent an increase in phase jitter even if information with a small timing component is successive. This invention relates to a timing synchronization method.

The use of existing telephone lines is widely used for data transmission. Since such telephone lines are analog lines, a modem (modem) is used to modulate and demodulate digital data into analog signals.

In such a modem, it is necessary to extract a timing component from a received signal, create a synchronization clock, and operate each part in synchronization.

[Conventional technology]

For example, as shown in the block diagram of the modem demodulator shown in FIG. After being converted into a digital signal at the cycle of a sampling clock, which will be described later, it is input to a digital signal processor DSP. In the digital signal processor DSP, the output from the A/D converter 2 is demodulated in the demodulation unit 3, converted to baseband, and then waveform-shaped in the roll-off filter unit 6.
After AGC control in the AGC section 8, a timing component is extracted in the timing extraction section 4, and lead/delay information based on the timing component is given to the microprocessor MPU, which controls the PLL (phase lock loop) section 7 of the microprocessor MPU. The baud rate clock is adjusted to synchronize its output, the baud rate clock, with the timing signal. The baud rate clock acts as an internal clock that allows the modem internals to operate in synchronization with the timing signals.

In addition, the demodulation section 3, the roll-off filter section 6,
The AGC section 8 and the timing extraction section 4 are blocks of processing executed by the digital signal processor DSP.

This timing extraction section 4 is constructed as shown in FIG. 4A.

That is, in FIG. 4A, 41 and 42 are timing extraction filters (1200Hz band filter), and the real part and imaginary part AX, respectively, from the AGC section 8 are received.
43 and 44 are squaring circuits that extract the timing component of the timing signal band among the AY components; 45 is an adder that squares the output of each filter 41 and 42;
46 is a low-pass filter (2400Hz band filter) that removes the AC component and outputs the timing component TX. 47 is a 90° component detector. , X timing component of low-pass filter 46
It outputs the Y timing component TY rotated by 90 degrees from TX.

To explain this operation, after the timing components are extracted by the timing extraction filters 41 and 42,
They are each squared by squaring circuits 43 and 44, and further added by an adder 45 to obtain power, and a low-pass filter 46 cuts off the alternating current component to obtain the timing X component TX. Further, the 90° component detection unit 47 detects the timing Y component from the timing X component TX.
TY is created. When these outputs TX and TY are normalized by a circle with a radius of 1, as shown on the vector plane in Figure 4B, when timing synchronization is established, they are at the position (1 + j0) of point a, and when synchronization is When there is, it is at a position rotated by α as shown in the figure. Therefore,
For TX and others, the amount of phase shift can be determined by the value of TY,
The PLL section 7 is adjusted accordingly.

[Problem that the invention seeks to solve]

On the other hand, the output levels of such timing components TX and TY are not constant and vary depending on the data pattern and line characteristics.

The timing signal is placed at the phase or amplitude conversion point of the received signal, and appears at both ends of the signal band in terms of frequency. Therefore, depending on the characteristics of the band filter or roll-off filter, the timing component may be extremely reduced depending on the data pattern or a specific training pattern, as shown in FIG.

If such a timing component decreases, it becomes difficult to determine an accurate timing phase no matter how much normalization is performed. In particular, when information with few timing components is consecutive, a problem arises in that phase jitter increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a timing synchronization method that can perform synchronous operation with minimal increase in phase jitter even if the timing component is small.

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1A, the same parts as those shown in FIGS. 3 and 4 are indicated by the same symbols, and 5 is a phase hold section, which is the timing component TX extracted by the timing extraction section 4. , TY and a predetermined threshold TH, and if the timing component is greater than or equal to the threshold TH, the timing component is held, and if it is less than the threshold TH, the held timing component is used as timing information TX', TY' This is what is output as.

That is, the present invention includes a timing extraction step for extracting X and Y timing components from an input signal;
A timing synchronization method includes a synchronization step of synchronizing internal clocks according to a phase shift caused by the extracted X and Y timing components, a step of calculating vector components of the X and Y timing components, and a step of calculating vector components of the X and Y timing components; comparing the vector components with a predetermined threshold;
When the vector component is above a predetermined threshold, the X and Y timing components are held and output, and when the vector component is below a predetermined threshold, the previously held timing is The present invention is characterized by comprising a phase hold step that outputs the components, and an amplitude normalization step that normalizes the amplitudes of the X and Y timing components from the phase hold step and outputs the same to the synchronization step.

[Effect]

In the present invention, even if a timing component as shown in FIG. 1B is extracted, if it is below the threshold TH, the phase of the timing component above the previous threshold TH is output.

That is, the portion below _the threshold between time t ₁ and time t ₂ in FIG.
It can be replaced as follows.

In other words, for the portion below the threshold, the phase of the immediately preceding timing component is held and output.

Therefore, the timing phase during this period remains the same even if the timing phase actually changes, and although synchronization occurs during this period and phase jitter increases, this period of small timing component does not continue for a long time, and moreover, the phase fluctuation during this period Since is small, phase jitter can be substantially minimized. Incidentally, even if the timing component is small and the synchronization is performed, the synchronization that is erroneously caused by the inability to synchronize can only be performed, and the phase jitter will be large.

〔Example〕

(a) Description of the configuration of one embodiment FIG. 2 is an explanatory diagram of the phase hold step of the present invention, and shows an equalization circuit diagram of the phase hold section 5.

In the figure, the same parts as those shown in FIG. 1A are the same symbols, and 5a is a timing phase hold circuit, which is used to control the vector components of the timing components TX and TY of the timing extractor 4 and the threshold hold TH. If the vector component is greater than or equal to the threshold TH, the timing components TX and TY are held and output, and the threshold is
If it is less than TH, the held timing component TX,
It outputs TY, and the vector determination unit 50
5b is an amplitude normalization circuit, and a timing phase hold circuit 5a
This normalizes the outputs TX and TY of the circuit to the amplitude of a circle with a radius of 1, and includes a vector component calculation section 52 and a normalization section 53.

501 and 502 are multipliers that square the timing components TX and TY, respectively, and 503 is an adder that adds the outputs TX ² and TY ² of each multiplier to obtain the vector component (TX ²
+TY ² ), 504 is an adder,
505 is a polarity determiner that subtracts the vector component and a predetermined threshold TH, and determines the polarity of the output {(TX ² +TY ² )−TH} of the adder 504, and determines whether the polarity is positive or (TX ² +TY ² ) ≧ TH, the control output ATL is “1” and BTL is “0”; if the polarity is negative (TX ² +TY ² ) < TH, the control output ATL is “0” and BTL is “1”. ,511,51
2 are first multipliers, each of which multiplies the timing components TX, TY, and the control output ATL; 513, 514 are adders, which connect multipliers 511, 512 and a second multiplier to be described later. 515 and 516 are second multipliers, respectively, which perform addition with the output of the multiplier and generate the outputs XTMR and XTMI.
A device that multiplies the output of each tap and a control output BTL, which will be described later, and outputs the result to adders 513 and 514,
Taps 517 and 518 hold the outputs XTMR and YTMI of adders 513 and 514, respectively, and output them to second multipliers 515 and 516, respectively.

512 and 522 are multipliers, and the output
XTMR, XTMI multiplied by 1/√2, 5
23 and 524 are multipliers, and each multiplier 5
525 is an adder that adds the outputs of multipliers 523 and 524 to obtain a vector component (XTMR ² +YTMI ² )/2; 531 is an inverter ROM (read-only memory); ), which stores the reciprocal of the vector component and outputs the reciprocal in accordance with the value of the vector component, 532 and 533 are multipliers, and the output of the inverter ROM 513 and the output
It multiplies XTMR and YTMI and outputs normalized timing components TX' and TY'.

(b) Description of operation of one embodiment When the timing components TX and TY are given to the timing phase hold circuit 5a from the timing extraction section 4, each multiplier 501 of the vector determination section 50,
At 502, the timing components TX and TY are squared,
These are added by an adder 503 to obtain a vector component (TX ² +TY ² ). This vector component is subtracted by the threshold TH by an adder 504 and input to a polarity determiner 505 . If the output of the adder 504 is positive and the vector component≧TH, the polarity determiner 505 sets the control output ATL to “1” and sets the control output to “1”.
BTL is set to "0", and if vector component < TH, control output ATL is set to "0" and control output BTL is set to "1".

Therefore, if the vector component≧TH, the first multipliers 511, 512 output the timing components TX, TY
is output as is to adders 513 and 514.

On the other hand, since the control output BTL is "0", the second multipliers 515, 516 to adders 513, 5
Since no output is sent to adder 51
Timing components TX and TY are output from 3,514
Output as XTMR, XTMI, tap 517,
It is held at 518.

Conversely, if the vector component < TH, the control output
Since ATL becomes “0”, the first multiplier 511,
The output of 512 becomes zero, while the control output BTL
Since is "1", the hold values of taps 517 and 518 are input to adders 513 and 514, and the hold values of taps 517 and 518 are output as outputs XTMR and YTMI of adders 513 and 514, respectively.

Therefore, if the vector component of the timing component is greater than or equal to the threshold TH, the timing component
TX and TY are output and held, and conversely, if the vector component of the timing component is less than the threshold, the previous held timing component is output.

The outputs XTMR and YTMI are input to the amplitude normalization circuit 5b, multiplied by 1/√2 by the nominal multipliers 521 and 522 of the vector component calculation unit 52, squared by the nominal multipliers 523 and 524, and then squared by the nominal multipliers 523 and 524. vector component (XTMR ² + YTMI ² )/
2 is obtained.

The inverter ROM 531 outputs the reciprocal of this vector component, which is output by the multipliers 532 and 533.
Multiply XTMR, YTMI and the reciprocal, and the fourth radius of 1
Timing information TX', TY' shown in FIG. B is obtained.

Therefore, timing synchronization is performed by determining the timing phase from this timing information and adjusting the PLL section 7 as in the conventional case.

Although the present invention has been described above using one embodiment, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects are achieved.

Since the phase of the timing component that shows a phase shift due to the amplitude of X and Y can be held based on the results of the calculation step and the comparison step,
Even if information with a small timing component continues, phase synchronization will not become impossible or phase jitter will not increase.

Since the X and Y timing components can be output with a certain amplitude or more, errors in phase shifts due to vectors that can indicate phase shifts with high precision are further reduced.

Since the hold output is amplitude normalized, a phase shift can be applied to the synchronization step regardless of the amplitude.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an equalization circuit diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of the demodulation section of the modem, Fig. 4 is an explanatory diagram of the conventional method, and Fig. 5 is an explanatory diagram of conventional problems. In the figure, 4... timing extraction section, 5... phase hold section, 7... PLL section.

Claims (1)

[Scope of Claims] 1. Timing having a timing extraction step for extracting X and Y timing components from an input signal, and a synchronization step for synchronizing internal clocks in accordance with the phase shift caused by the extracted X and Y timing components. The synchronization method includes a step of calculating a vector component of the X and Y timing components, a step of comparing the calculated vector component with a predetermined threshold, and a step of comparing the vector component with a predetermined threshold. a phase hold step for holding and outputting the X, Y timing components and outputting the held timing components when the vector components are below a predetermined threshold; A timing synchronization method comprising: an amplitude normalization step for normalizing the amplitudes of X and Y timing components from a hold step and outputting the same to the synchronization step.