JPS6035862B2 - timing extraction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing extraction circuit in a PCM (Pulse Code Modulation) signal repeater.

The timing extraction circuit in the PCM signal repeater is
It is necessary to extract the bit timing component contained in the M signal input and have the PCM repeater reproduce and transmit the PCM signal based on this bit timing.

FIG. 1 is a block diagram of an example of a conventional timing extraction circuit.

In this conventional circuit, a differential waveform related to a bit timing component of a PCM signal input IN is double-wave rectified by a double-wave rectifier circuit REC, and then inputted to a resonant circuit RSN.

The resonant circuit RSM sends out a resonant output based on its differential waveform (bit timing component), but depending on the code pattern, even if there is some bit timing component missing in the PCM signal input IN, its resonant effect will continue. , and outputs continuous bit timing components.

The limiter amplifier LAMP inputs this to the phase-locked loop circuit PLL and outputs the reproduction timing signal OUT.
to be sent.

This phase-locked loop circuit PLL is not necessarily necessary, but since the resonant circuit RSN has a limited ability to compensate for missing bit timing (usually up to 8 bits at most), it is added to further compensate for this. It is something that

Such conventional circuits require extremely high precision and highly stable inductors and capacitors for their resonant circuit RSM. The device becomes large and uneconomical, and the device's I
This was also a major bottleneck for conversion to C.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide an economical timing extraction circuit that can be integrated into an IC.

The configuration of the timing extraction circuit according to the present invention includes an integrating circuit and a sample hold circuit on the input side of a loop filter constituting a phase-locked loop. By adding a phase information holding circuit having a predetermined holding characteristic that can compensate for missing bit timing components, the oscillation output of the phase-locked loop can be sent out as a desired reproduction timing signal output.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of an embodiment of the timing extraction circuit according to the present invention, and FIG. 3 is a time chart thereof.

Here, 1 is a differentiator circuit that detects the rising edge of the PCM signal input IN (for example, zero return type RZ-PCM signal input), 2 is a set/reset type flip-flop, and 3
4 is an integrator circuit related to the phase information holding circuit; 4 is a sample and hold circuit; 5 is a loop filter; 6 is a voltage-controlled oscillator; and 7 is a differential circuit that detects the rise of the output waveform of the voltage-controlled oscillator 6. It is. Note that a~ in Figure 3
g is the signal waveform at points a to g drawn in FIG.

First, "differentiator circuit 1 receives PCM signal input IN (signal waveform a
), for example, each rising edge of data "11011..." is detected and a pulse is sent out (signal waveform b).

The flip-flop 2 receives this pulse at its set terminal S, and also receives the pulse of the output signal waveform d of the differentiating circuit 7, which detects the rising edge of the output signal waveform c of the voltage controlled oscillator 6, at its reset terminal R. Perform phase comparison.

That is, when a pulse of signal waveform b is input to the set terminal S, the output terminal Q of flip-flop 2 becomes high level, and when a pulse of signal waveform d is input to the reset terminal R, the output terminal Q becomes low level. , the high level period of the output terminal Q has the above phase difference. When the output terminal Q of the flip-flop 2 becomes high level, the integrating circuit 3 closes the switch SWA, delays the pulse of the signal waveform b by a predetermined time by the delay circuit 7, and the output pulse causes
The switch SWB is momentarily closed, the capacitor C is discharged, and the previous integral value is canceled.

After canceling this integral value, a new switch S
Capacitor C is charged through WA, integration is started, and an integral output (signal waveform f) is sent out.

Thereafter, when a pulse of signal waveform d is input to the reset terminal R of the flip-flop 2, the flip-flop 2 is reset and the output terminal Q becomes low level, so the switch SWA is opened and the integration is completed.

・The integral value Vo at that time is proportional to the phase difference ◇ between the pulses of the signal waveforms b and d.

On the other hand, when the switch SWC of the sample and hold circuit 4 is closed by a pulse of the signal waveform b, the sample and hold circuit 4 samples and holds the output of the integrating circuit 3 (signal waveform f) for each pulse.

That is, the output signal waveform is sampled and held by each differential pulse of signal waveform b, as shown in signal waveform g (in signal waveform g, pulses of the integral output value are applied at positions as indicated by the broken line), so As shown by the solid line, it has a predetermined constant value.

This means that even if a differential pulse is not obtained in the signal waveform b, such as during the bit period of the third data "0", the bit timing component can be This is because they are filling in the gaps.

The output of this sample and hold circuit 4 is fed back to the voltage controlled oscillator 6 via a loop filter 5, forming a phase locked loop.

As described above, the loss of bit timing components can be eliminated by adding a circuit with a simple configuration. Therefore, the voltage controlled oscillator 6 has a PCM signal input I
Output (
Send out signal waveform c).

In other words, this becomes the reproduction timing signal output OUT.

In this way, by inserting the phase information holding circuit made up of the integrating circuit 3 and the sample-hold circuit 4 into a part of the phase-locked loop, it is possible to compensate for missing bit timing components within the range of its holding characteristics.

In the above embodiment, it is clear that if a frequency divider circuit or a multiplier circuit is added to the voltage controlled oscillator 6, a reproduction timing signal output OUT having a frequency obtained by dividing or multiplying the clock frequency of the PCM signal input can be obtained.

As described above in detail, according to the present invention, high precision,
Does not require high stability inductors and capacitors, almost
Since only a digital circuit is required, a remarkable effect can be obtained in making the timing extraction circuit economical and eliminating bottlenecks in IC implementation.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an example of a conventional timing extraction circuit, FIG. 2 is a block diagram of an embodiment of a timing extraction circuit according to the present invention, and FIG. 3 is a time chart thereof. be.

1, 7...Differentiating circuit, 2...Flip-flop, 3...Integrator circuit, 4...Sample and hold circuit, 5... Loop fill evening,
6... Voltage controlled oscillator.

Figure 1 Figure 2 Figure 3

Claims (1)

[Scope of Claims] 1. The input side of the loop filter constituting the phase lock loop is composed of an integrating circuit and a sample-hold circuit, which operates according to the bit timing components of the signal input, and operates by the bit timing components of the desired number of the bit timing components. A timing extraction circuit characterized in that the oscillation output of the phase lock loop can be sent out as a desired reproduction timing signal output by adding a phase information holding circuit having a predetermined holding characteristic that can compensate for omissions. . 2. In the device described in claim 1, the phase information holding circuit operates based on the bit timing component of the signal input, and operates at predetermined time intervals from the bit timing component to the rise of the next oscillation output of the phase lock loop. A timing circuit that performs an integration operation to obtain an output proportional to the phase difference thereof, and a sample-and-hold circuit that samples and holds the output of the integrator circuit for each bit timing component and has a predetermined holding characteristic. extraction circuit.