JPH0334287B2 - - Google Patents
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- Publication number
- JPH0334287B2 JPH0334287B2 JP57019089A JP1908982A JPH0334287B2 JP H0334287 B2 JPH0334287 B2 JP H0334287B2 JP 57019089 A JP57019089 A JP 57019089A JP 1908982 A JP1908982 A JP 1908982A JP H0334287 B2 JPH0334287 B2 JP H0334287B2
- Authority
- JP
- Japan
- Prior art keywords
- feeder
- zero
- current
- phase current
- absolute value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Emergency Protection Circuit Devices (AREA)
- Relay Circuits (AREA)
Description
【発明の詳細な説明】
本発明は配電線保護リレー装置に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power distribution line protection relay device.
従来の配電線保護リレー方式は第１図に示すよ
うに母線Ｂより出る各フイーダFi毎に過電流リレ
ーOCiと地絡方向リレーGDiを設置し、過電流リ
レーOCiで短絡保護し、地絡方向リレーGDiで地
絡保護を行なつていた。ここでｉ＝１，２，…，
ｎであり、PTは計器用変圧器である。 As shown in Figure 1, the conventional distribution line protection relay system installs an overcurrent relay OCi and a ground fault direction relay GDi for each feeder Fi that exits from bus B.The overcurrent relay OCi protects against short circuits, and Ground fault protection was provided by relay GDi. Here i=1, 2,...,
n and PT is the potential transformer.
この従来の配電線保護リレー方式は過去長い間
採用されてきた方式であるが次のような問題点を
有する。 Although this conventional power distribution line protection relay system has been employed for a long time, it has the following problems.
(1) フイーダ毎に個々のリレーを設置しなければ
ならない。(1) An individual relay must be installed for each feeder.
(2) 信頼度向上のため、自動点検機能を付加しよ
うとしても単体コストに対して高価となりメリ
ツトがない。(2) Even if an attempt is made to add an automatic inspection function to improve reliability, it will be expensive compared to the unit cost and there will be no benefit.
(3) 数多くのリレーがあるため、保守や定期点検
などにかかる労力が大である。(3) Since there are a large number of relays, maintenance and periodic inspections require a lot of effort.
本発明は従来の問題点を解決しようとするもの
で、以下実施例を用いて説明する。 The present invention is intended to solve the conventional problems, and will be explained below using examples.
第２図は本発明による配電線保護リレー装置の
一実施例を示し、同図において１は母線、２は各
配電線のフイーダ、３は各配電線のフイーダ２に
介挿された変流器、４は各フイーダ２に介挿され
た零相変流器、５は配電線保護リレー装置であつ
て、この配電線保護リレー装置５に各フイーダ２
の変流器３からの各相電流および零相変流器４か
らの零相電流が夫々入力される。 FIG. 2 shows an embodiment of the distribution line protection relay device according to the present invention, in which 1 is a bus bar, 2 is a feeder of each distribution line, and 3 is a current transformer inserted in the feeder 2 of each distribution line. , 4 is a zero-phase current transformer inserted in each feeder 2, 5 is a distribution line protection relay device, and each feeder 2 is connected to this distribution line protection relay device 5.
Each phase current from the current transformer 3 and the zero-sequence current from the zero-sequence current transformer 4 are respectively input.
この配電線保護リレー装置５は、変流器３から
の各相電流ｉおよび零相変流器４からの零相電流
i0が供給され、これら各相電流ｉおよび零相電流
i0をアナログ／デイジタル変換し、各相電流ｉに
ついては短絡保護判定部７へ送出し、零相電流i0
について地絡保護判定部８へ送出するアナログ−
デイジタル変換部６と、短絡保護判定部７と、地
絡保護判定部８と、オア回路９とからなる。ここ
で短絡保護判定部７はアナログ−デイジタル変換
部６からの各相電流ｉの絶対値を求め、各相毎に
相電流ｉの絶対値の緩和が一定値ｋを越えたこと
を条件に、当該相の最大電流のフイーダにしや断
指令を出力するものであつて、アナログ−デイジ
タル変換部６からの各相電流ｉの絶対値をとる絶
対値算出部１０と、この絶対値算出部１０から時
分割により各相毎に供給される各フイーダの電流
ｉの絶対値の総和を求め、その総和が一定値ｋを
越えたか否かを判定する加算比較部１１と、前記
絶対値算出部１０から時分割により供給される当
該相（前記加算比較部１１の処理と対応した相）
の最大電流のフイーダを検出しそのフイーダ番号
信号を送出する事故フイーダ検出部１２と、加算
比較部１１の出力と事故フイーダ検出部１２の出
力とが供給されるアンド回路１３とからなる。 This distribution line protection relay device 5 handles each phase current i from the current transformer 3 and the zero-phase current from the zero-phase current transformer 4.
i 0 is supplied, and each phase current i and zero-sequence current
i 0 is converted from analog to digital, each phase current i is sent to the short-circuit protection determination section 7, and the zero-phase current i 0
The analog signal sent to the ground fault protection determination unit 8 for
It consists of a digital conversion section 6, a short circuit protection determination section 7, a ground fault protection determination section 8, and an OR circuit 9. Here, the short-circuit protection determining section 7 calculates the absolute value of each phase current i from the analog-digital converting section 6, and on the condition that the relaxation of the absolute value of the phase current i exceeds a certain value k for each phase, An absolute value calculation unit 10 which outputs a shedding command to the feeder of the maximum current of the phase, and which takes the absolute value of each phase current i from the analog-digital conversion unit 6, and from this absolute value calculation unit 10. An addition/comparison unit 11 that calculates the sum of the absolute values of the currents i supplied to each feeder for each phase by time division, and determines whether the sum exceeds a certain value k, and the absolute value calculation unit 10. The relevant phase supplied by time division (the phase corresponding to the processing of the addition comparison section 11)
It consists of an accidental feeder detection section 12 that detects the feeder with the maximum current and sends out the feeder number signal, and an AND circuit 13 to which the output of the addition/comparison section 11 and the output of the accidental feeder detection section 12 are supplied.
また地絡保護判定部８はアナログ−デイジタル
変換部６からの零相電流i0の絶対値を求めすべて
のフイーダ２についての零相電流i0の絶対値の総
和が一定値K0を越えたことを条件に最大の零相
電流i0のフイーダにしや断指令を出力するもので
あつて、アナログ−デイジタル変換部６からの零
相電流i0の絶対値をとる絶対値算出部１４と、こ
の絶対値算出部１４から供給されるすべてのフイ
ーダ２についての零相電流i0の絶対値の総和を求
め、その総和が一定値K0を越えたか否かを判定
する加算比較部１５と、前記絶対値算出部１４か
ら供給される零相電流i0のうちの最大の零相電流
i0のフイーダを検出し、そのフイーダ番号信号を
送出する事故フイーダ検出部１６と、加算比較部
１５の出力と事故フイーダ検出部１６の出力とが
供給されるアンド回路１７とからなる。 In addition, the ground fault protection determining unit 8 calculates the absolute value of the zero-sequence current i 0 from the analog-digital converter 6 and determines whether the sum of the absolute values of the zero-sequence current i 0 for all feeders 2 exceeds a certain value K 0 . an absolute value calculation unit 14 that outputs a shearing command to the feeder of the maximum zero-sequence current i 0 on the condition that the absolute value of the zero-sequence current i 0 from the analog-digital converter 6 is taken; an addition comparison unit 15 that calculates the sum of the absolute values of the zero-sequence currents i 0 for all feeders 2 supplied from the absolute value calculation unit 14 and determines whether the sum exceeds a certain value K 0 ; The maximum zero-sequence current among the zero-sequence currents i 0 supplied from the absolute value calculation unit 14
It consists of an accidental feeder detection section 16 that detects the feeder of i 0 and sends out its feeder number signal, and an AND circuit 17 to which the output of the addition and comparison section 15 and the output of the accidental feeder detection section 16 are supplied.
なお、配電線保護リレー装置５をマイクロコン
ピユータで構成することができ、この場合に短絡
保護判定部７と地絡保護判定部８とオア回路９の
部分を適当な演算処理装置（CPU）で構成する
ことができる。 Note that the distribution line protection relay device 5 can be configured with a microcomputer, and in this case, the short circuit protection determining section 7, the ground fault protection determining section 8, and the OR circuit 9 can be configured with a suitable arithmetic processing unit (CPU). can do.
次に動作について説明する。 Next, the operation will be explained.
まず短絡保護の場合には、アナログ−デイジタ
ル変換部６からの各相電流ｉの絶対値算出部１０
で求め、時分割により各相毎にすべてのフイーダ
についての相電流ｉの絶対値を加算比較部１１お
よび事故フイーダ検出部１２に送出する。たとえ
ばａ相短絡についての判定の場合には、加算比較
部１１では絶対値算出部１０から供給される各フ
イーダのａ相電流ｉの絶対値の総和を求め、その
総和が一定値Ｋを越えたか否かを判定し、一定値
Ｋを越えたらアンド回路１３に出力を送出してア
ンド回路１３のゲートを開く。一方事故フイーダ
検出部１２では各フイーダのａ相電流ｉのうち、
最大のａ相電流ｉが流れているフイーダを検出
し、その該当するフイーダ番号信号をアンド回路
１３に送出する。従つて、加算比較部１１の出力
が供給されたことを条件にアンド回路１３は事故
フイーダ検出部１２の出力信号をオア回路９を介
して該当フイーダのしや断器のトリツプ信号（し
や断指令）として送出する。これによりａ相短絡
のあるフイーダの保護がなされる。なお加算比較
部１１でａ相電流ｉの絶対値の総和が一定値Ｋを
越えないときには出力を送出せず、アンド回路１
３はフイーダのしや断器トリツプ信号を送出しな
い。 First, in the case of short circuit protection, the absolute value calculation unit 10 of each phase current i from the analog-digital conversion unit 6
The absolute value of the phase current i for all feeders for each phase is sent to the addition/comparison section 11 and the faulty feeder detection section 12 by time division. For example, in the case of a determination regarding an a-phase short circuit, the addition and comparison section 11 calculates the sum of the absolute values of the a-phase currents i of each feeder supplied from the absolute value calculation section 10, and determines whether the sum exceeds a certain value K. If it exceeds a certain value K, the output is sent to the AND circuit 13 and the gate of the AND circuit 13 is opened. On the other hand, in the accident feeder detection unit 12, among the a-phase current i of each feeder,
The feeder through which the maximum a-phase current i is flowing is detected, and the corresponding feeder number signal is sent to the AND circuit 13. Therefore, on the condition that the output of the addition/comparison section 11 is supplied, the AND circuit 13 converts the output signal of the faulty feeder detection section 12 into a trip signal for the breakout of the corresponding feeder via the OR circuit 9. command). This protects the feeder with the a-phase short circuit. Note that when the sum of the absolute values of the a-phase current i does not exceed a certain value K in the addition/comparison section 11, no output is sent out, and the AND circuit 1
3 does not send out the feeder cutout trip signal.
次に時分割によりｂ相についてのフイーダにつ
いての相電流ｉの絶対値データを加算比較部１１
および事故フイーダ検出部１２に送出し、前述し
たと同様の処理を行なう。次にｃ相についても同
様の処理を行なう。 Next, the comparator 11 adds the absolute value data of the phase current i for the feeder for the b phase by time division.
The data is then sent to the accident feeder detection unit 12, and the same processing as described above is performed. Next, similar processing is performed for the c phase.
また地絡保護の場合には、アナログ−デイジタ
ル変換部６からの零相電流i0の絶対値を絶対値算
出部１４で求め、その絶対値を加算比較部１５に
出力する。加算比較部１５は零相電流i0の絶対値
の総和を求め、その総和が一定値K0を越えたか
否かを判定し、一定値K0を越えたらアンド回路
１７に出力を送出してアンド回路１７のゲートを
開く。一方、事故フイーダ検出部１６は各フイー
ダの零相電流i0のうち、最大の零相電流i0のフイ
ーダを検出し、そのフイーダ番号信号を送出す
る。アンド回路１７の一方に加算比較部１５の出
力が供給されていると、事故フイーダ検出部１６
の出力信号（該フイーダ番号信号）をアンド回路
１７、オア回路９を介して該当フイーダのしや断
器のトリツプ信号（しや断指令）として送出す
る。これにより地絡のあるフイーダの保護がなさ
れる。なお加算比較部１５の出力が送出されない
ときは、アンド回路１７はフイーダのしや断器ト
リツプ信号を送出しない。 In the case of ground fault protection, the absolute value of the zero-sequence current i 0 from the analog-digital converter 6 is determined by the absolute value calculator 14, and the absolute value is output to the addition and comparison unit 15. The addition/comparison section 15 calculates the sum of the absolute values of the zero-sequence current i0 , determines whether the sum exceeds a certain value K0 , and sends an output to the AND circuit 17 if it exceeds the certain value K0 . Open the gate of AND circuit 17. On the other hand, the accidental feeder detection unit 16 detects the feeder with the maximum zero-sequence current i 0 among the zero-sequence currents i 0 of each feeder, and sends out the feeder number signal. When the output of the addition comparison section 15 is supplied to one side of the AND circuit 17, the accident feeder detection section 16
The output signal (the feeder number signal) is sent out via the AND circuit 17 and the OR circuit 9 as a trip signal (breakdown command) for the breakout switch of the corresponding feeder. This provides protection for feeders with ground faults. Note that when the output of the addition/comparison section 15 is not sent out, the AND circuit 17 does not send out the feeder edge disconnection trip signal.
本発明はこのように数多くあるフイーダ電流の
うち、事故フイーダの電流（ａ相電流，ｂ相電
流，ｃ相電流，零相電流）の絶対値の総和が一定
値を越えたことを条件に、最大の電流絶対値をも
つフイーダを選択しや断するものである。 The present invention is based on the condition that the sum of absolute values of faulty feeder currents (a-phase current, b-phase current, c-phase current, zero-sequence current) among these many feeder currents exceeds a certain value. The feeder with the maximum absolute current value is selected and cut off.
なお本実施例においては、短絡保護と地絡保護
を一つの配電線保護リレー装置で構成している
が、本発明は短絡保護と地絡保護を別々の配電線
保護リレー装置で構成してもよいことはもちろん
である。 In this embodiment, short circuit protection and ground fault protection are configured with one distribution line protection relay device, but the present invention may also configure short circuit protection and ground fault protection with separate distribution line protection relay devices. Of course it's a good thing.
また本実施例においては、配電線保護リレー装
置はデイジタル処理装置で構成しているけれども
本発明はこれに限定されることなくアナログ装置
で構成することもできることはもちろんである。
この場合、アナログ−デイジタル変換部６を不要
にし、絶対値算出部１０，１４と加算比較部１
１，１５と事故フイーダ検出部１２，１６とアン
ド回路１３，１７とオア回路９をアナログ装置で
構成することになる。 Further, in this embodiment, the power distribution line protection relay device is constituted by a digital processing device, but the present invention is not limited to this, and it goes without saying that it can be constituted by an analog device.
In this case, the analog-digital converter 6 is unnecessary, and the absolute value calculators 10 and 14 and the addition comparator 1
1 and 15, the accident feeder detection sections 12 and 16, the AND circuits 13 and 17, and the OR circuit 9 are constructed from analog devices.
上述した本発明による配電線保護リレー装置を
用いれば次のような効果を奏する。 The use of the above-described power distribution line protection relay device according to the present invention provides the following effects.
(1) 集中して１装置によつて配電線の多フイーダ
を保護できるため従来に比べ装置の小型化が可
能である。(1) Since multiple feeders of a power distribution line can be protected with one device in a concentrated manner, the device can be made smaller than before.
(2) 高度な自動点検機能を付加しても装置コスト
に対しきわめて低コストのため、高度な自動点
検機能を付加することが経済面より相対的に可
能となり、高信頼度となる。(2) Even if an advanced automatic inspection function is added, the cost is extremely low compared to the equipment cost, so it is economically possible to add an advanced automatic inspection function, and the reliability is high.
(3) １装置によつて構成できるため、保守，点検
が容易である。(3) Since it can be configured with one device, maintenance and inspection are easy.
第１図は従来の配電線保護リレー方式の一例を
示す構成図、第２図は本発明による配電線保護リ
レー装置の一実施例を示す構成図であつて、図中
１は母線、２は配電線のフイーダ、３は変流器、
４は零相変流器、５は配電線保護リレー装置、６
はアナログ−デイジタル変換部、７は短絡保護判
定部、８は地絡保護判定部、９はオア回路を示
す。
Fig. 1 is a block diagram showing an example of a conventional distribution line protection relay system, and Fig. 2 is a block diagram showing an embodiment of a distribution line protection relay device according to the present invention. Distribution line feeder, 3 is a current transformer,
4 is a zero-phase current transformer, 5 is a distribution line protection relay device, 6
Reference numeral 7 indicates an analog-to-digital conversion section, 7 a short-circuit protection determination section, 8 a ground fault protection determination section, and 9 an OR circuit.
Claims (1)
各フイーダに設置された変流器により検出された
各相電流がすべて入力され各フイーダの各相電流
の絶対値を求める相電流絶対値算出部と、 前記相電流絶対値算出部からの各フイーダの電
流の絶対値の総和が一定値を越えたことを検出す
るフイーダ電流加算比較部と、 前記相電流絶対値算出部からの各相電流から最
大相電流のフイーダを検出する最大相電流フイー
ダ検出部と、 前記フイーダ電流加算比較部と前記最大相電流
フイーダ検出部の出力が入力され最大相電流が流
れるフイーダしや断指令を出力するアンド回路
と、 各フイーダに設置され零相変流器により検出さ
れた零相電流がすべて入力され各フイーダの零相
電流の絶対値を求める零相電流絶対値算出部と、 前記零相電流絶対値算出部からの各フイーダの
零相電流の絶対値の総和が一定値を越えたことを
検出する零相電流加算比較部と、 前記零相電流絶対値算出部からの零相電流から
最大零相電流のフイーダを検出する最大零相電流
フイーダ検出部と、 前記零相電流加算比較部と前記最大零相電流フ
イーダ検出部の出力が入力され最大相電流が流れ
るフイーダにしや断指令を出力するアンド回路、
とからなることを特徴とした配電線保護リレー装
置。[Claims] 1. In a power distribution system equipped with a large number of feeders,
a phase current absolute value calculation unit that receives all the phase currents detected by the current transformers installed in each feeder and calculates the absolute value of each phase current of each feeder; a feeder current addition/comparison unit that detects that the sum of the absolute values of the currents exceeds a certain value; and a maximum phase current feeder detection unit that detects the feeder of the maximum phase current from each phase current from the phase current absolute value calculation unit. an AND circuit that receives the outputs of the feeder current addition and comparison section and the maximum phase current feeder detection section and outputs a command to turn on or off the feeder through which the maximum phase current flows; and a zero-phase current transformer installed at each feeder. a zero-sequence current absolute value calculation unit to which all detected zero-sequence currents are input and calculate the absolute value of the zero-sequence current of each feeder; a zero-sequence current addition and comparison section that detects that the sum exceeds a certain value; and a maximum zero-sequence current feeder detection section that detects the maximum zero-sequence current feeder from the zero-sequence current from the zero-sequence current absolute value calculation section. , an AND circuit that receives the outputs of the zero-sequence current addition and comparison section and the maximum zero-sequence current feeder detection section and outputs a shear cutting command to the feeder through which the maximum phase current flows;
A distribution line protection relay device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1908982A JPS58139639A (en) | 1982-02-09 | 1982-02-09 | Power distributing protecting relay unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1908982A JPS58139639A (en) | 1982-02-09 | 1982-02-09 | Power distributing protecting relay unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58139639A JPS58139639A (en) | 1983-08-19 |
| JPH0334287B2 true JPH0334287B2 (en) | 1991-05-22 |
Family
ID=11989724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1908982A Granted JPS58139639A (en) | 1982-02-09 | 1982-02-09 | Power distributing protecting relay unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58139639A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100766365B1 (en) * | 2006-07-06 | 2007-10-12 | 한국철도기술연구원 | Delta Eye Lock Protection Relay System and Control Method in DC Feed System for Electric Railway |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5857059B2 (en) * | 1978-05-12 | 1983-12-17 | 東京電力株式会社 | Distribution line short circuit protection method |
-
1982
- 1982-02-09 JP JP1908982A patent/JPS58139639A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58139639A (en) | 1983-08-19 |
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