JPH0334856B2 - - Google Patents

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for manufacturing a semiconductor device.

[Technical background of the invention and its problems]

Generally, when two conductive layers, for example, an impurity region formed on the surface of a semiconductor substrate and an Al layer, are connected through a contact hole, a contact hole 4 is opened above the impurity region 2 as shown in FIG. A wiring layer 51 having a margin l equal to the width c of the contact hole 4 is formed over the contact hole 4 . This margin l is usually provided in consideration of misalignment when forming the pattern of the wiring layer 51 to match the contact hole 4 by lithography.

Therefore, the width of the wiring layer 51 is c + 2l around the contact, and the width L outside the area around the contact.
Usually larger than . As a result, when forming other wiring layers 52 and 53 adjacent to the wiring layer 51,
The wiring density is lower around the contact than in areas other than the surrounding area. For this reason, if the wiring layer 51 has a margin l around the contact hole 4, the density of the wiring layer in the semiconductor device will be reduced, and this will hinder the improvement of the degree of integration of the semiconductor device.

In order to solve the above problem, if the wiring layer 51 is formed without taking the margin l in the conventional semiconductor device, as shown in FIG. each becomes a space S, and the density of the wiring layer is improved.

However, in this case, the contact hole 4 and the wiring layer 51 are
If misalignment occurs with the pattern of the resists 71, 72, 7 formed according to the patterns of the wiring layers 51, 52, 53 as shown in FIG.
When the wiring layer other than the portion covered by 3 is etched away, the impurity region 2 at the bottom of the contact hole 4 is also etched, and there is a risk that the impurity region 2 may be destroyed. Furthermore, in this case, since the wiring layer 51 does not completely cover the bottom surface of the contact hole 4, the current density of the wiring layer 51 at the bottom surface of the contact hole 4 increases, which tends to cause increased resistance or disconnection defects due to electromigration. There is a problem.

[Purpose of the invention]

The present invention was made in consideration of the above circumstances, and
It is an object of the present invention to provide a method for manufacturing a semiconductor device that increases wiring density and improves the degree of integration without causing wiring defects or deteriorating reliability.

[Summary of the invention]

In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes the steps of: forming an insulating layer on a first conductive layer; forming a contact hole in a predetermined region of the insulating layer; A step of exposing the layer, a step of depositing a conductive material on the entire surface to form a conductive material film, a step of forming a blocking material film on the entire surface, etching the blocking material film, and etching only the contact hole. forming a first block material by leaving the block material;
A step of applying resist to the entire surface to form a resist film, and patterning the resist film,
forming a second block material corresponding to the pattern of the second conductive layer to be formed; patterning the conductive material film using the first and second block materials as etch stoppers; The method is characterized by comprising a step of forming a conductive layer and a step of removing the second blocking material.

As a result, the second conductive layer completely covers the bottom surface of the contact hole, and there is no need for the second conductive layer to have an allowance for misalignment with the contact hole.

[Embodiments of the invention]

A plan view and a cross section of a semiconductor device according to an embodiment of the present invention are shown in FIGS. 1a and 1b. An impurity region 2 is formed on the surface of a semiconductor substrate 1 . Further, an insulating layer 3 is formed on the semiconductor substrate 1 , and a contact hole 4 is opened at a predetermined location on the impurity region 2 . A wiring layer 51 made of, for example, an Al layer is formed on the inner surface of the contact hole 4 and on the insulating layer 3. At this time, the width of the wiring layer 51 formed on the insulating layer 3 is equal to the width of the contact hole 4.
A block material 61 is embedded in the contact hole on the wiring layer 51.

In the semiconductor device obtained using the manufacturing method of the present invention, the wiring layer 51 and the impurity region 2 are connected to each other on the entire bottom surface of the contact hole 4, so that the wiring layer 51 is not aligned with the contact hole 4. contact hole 4 without having a margin that takes into account misalignment.
Even if the width is set equal to the width of the wire, there is no risk of disconnection or other defects.

Note that here, the impurity region 2 on the surface of the semiconductor substrate 1 is used as the first conductive layer, and the impurity region 2 on the surface of the semiconductor substrate 1 is used as the second conductive layer.
Although the wiring layer 51 made of an Al layer is taken as an example, the examples are not limited to this, and include, for example, an impurity region on the surface of a semiconductor substrate and a polycrystalline silicon layer, a polycrystalline silicon layer and a polycrystalline silicon layer, a polycrystalline silicon layer and an Al layer. , Al layer and
Two conductive layers such as an Al layer may be connected through a contact hole.

Although the blocking material 61 may be removed, it is more convenient to leave it as long as it does not adversely affect the semiconductor device, since the contact portion will be flattened.

FIG. 2 shows a plan view of another example of a semiconductor device manufactured by the manufacturing method of the present invention. In the above embodiment, the width of the wiring layer 51 is equal to the width of the contact hole 4.
The width of the wiring layer 51 is set to be equal to the width of the contact hole 4, and the margin width l that takes into account misalignment with the contact hole 4 is set to zero. However, in this embodiment, the width of the wiring layer 51 is smaller than the width of the contact hole 4.

In the semiconductor device manufactured by the manufacturing method of the present invention, even if the contact hole 4 is wide and has a large area, the width of the wiring layer 51 can be made smaller than the width of the contact hole 4. Therefore, the necessary minimum space S can be taken between each of the adjacent wiring layers 52 and 53.

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. Impurities are added to the surface of semiconductor substrate 1 to form impurity region 2 .
Further, an insulating layer 3 is formed on the semiconductor substrate 1, and a contact hole 4 is opened at a predetermined location on the impurity region 2. An Al layer 50 is deposited on the entire surface, and then a negative resist 60 is applied to flatten the surface (FIG. 3a). This negative resist 60 is applied to RIE (Rea-ctive).
The negative resist 61 is removed by ion etching, leaving the negative resist 61 only in the contact hole 4. This negative resist 61 is then exposed to light (FIG. 3b). Resist is again applied to the entire surface, and resists 71, 72, 73 corresponding to the pattern of the wiring layer remain by lithography. Using the resists 71, 72, 73 and the negative resist 61 in the contact hole 4 as blocking materials, the Al layer is patterned into the wiring layer 51 by etching.
At this time, the width of the wiring layer 51 is set equal to the width of the contact hole 4, and even if there is misalignment between the pattern of the wiring layer 51 and the contact hole 4, the negative resist 61 protects the wiring layer inside the contact hole 4. 51
are not etched away (Figure 3c).
Next, remove the resists 71, 72, 73 (third
Figure d).

As described above, according to this embodiment, even if the pattern of the wiring layer 51 is misaligned with the contact hole 4, the wiring layer 51 and the impurity region 2 are connected over the entire bottom surface of the contact hole 4, so that the wiring layer 51 can have a width that does not exceed the width of the contact hole 4 without having an allowance for misalignment with the contact hole 4.

In this embodiment, the impurity region 2 on the surface of the semiconductor substrate 1 is used as the first conductive layer, and the impurity region 2 is used as the second conductive layer.
Although we have taken as an example a wiring layer consisting of an Al layer, the examples are not limited to this example. The present invention can be applied to the case where two conductive layers such as an Al layer and an Al layer are connected through a contact hole.

Further, in this embodiment, a photosensitive negative resist 61 is used as a blocking material to prevent the wiring layer 51 inside the contact hole 4 from being removed by etching. secondly, it must be resistant to the developer of the resists 71, 72, 73, and thirdly, it must be resistant to etching of the second conductive layer, and function as a blocking material. Any material is fine as long as it is available. For example, a resin material such as polyimide resin or a glass material such as spin-coated glass can be used. Further, this blocking material does not need to be removed unless it adversely affects the semiconductor device, and the contact portion is more conveniently flattened.

Furthermore, in this embodiment, RIE was used to remove the negative resist 60 by etching and leave the negative resist 61 only in the contact hole 4, but this is also possible with CDE (Chemical Dry Etching).
(Wet Etching) may also be used, and in short, any etching method may be used as long as the etching progresses uniformly from the flattened surface and only the inside of the contact hole is left unetched.

〔Effect of the invention〕

As described above, according to the present invention, wiring density can be improved without causing wiring defects or deterioration of reliability, and it can contribute to improving the degree of integration of semiconductor devices.

[Brief explanation of drawings]

1A and 1B are a plan view and a sectional view of a semiconductor device as an example manufactured by the manufacturing method of the present invention, and FIG. 2 is a plan view of another example of a semiconductor device manufactured by the manufacturing method of the present invention. 3 are process diagrams showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 4, 5, and 6 are diagrams showing conventional semiconductor devices. 1... Semiconductor substrate, 2... Impurity region, 3...
Insulating layer, 4...Contact hole, 50, 51, 5
2, 53... wiring layer, 60, 61, 71, 72,
73...Resist.

Claims (1)

[Claims] 1. A step of forming an insulating layer on a first conductive layer; A step of opening a contact hole in a predetermined region of the insulating layer to expose the first conductive layer; A step of depositing a conductive material to form a conductive material film, a step of forming a blocking material film on the entire surface, and etching the blocking material film so that the blocking material remains only inside the contact hole. A step of forming a first block material, a step of applying resist to the entire surface to form a resist film, and a step of patterning the resist film to form a second block material corresponding to the pattern of the second conductive layer to be formed. patterning the conductive material film using the first and second block materials as etch stops to form the second conductive layer; and removing the second block material. A method for manufacturing a semiconductor device, comprising the steps of: