JPH0337215B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a microprogram control system controlled by a microprogram, and in particular, a microprogram sequencer that controls the address of a microprogram memory is suitable for LSI implementation. The present invention relates to a microprogram control system that allows the stack file to have a large capacity.

[Conventional technology]

FIG. 3 is a block diagram of a conventional microprocessor unit controlled by a microprogram.

1 is a microprocessor unit,
The block indicated by the one-dot chain line is the sequence control unit 20 as a microprogram sequencer, which sequentially generates address information of the microprogram memory 9 in which the microprogram is stored.

The microprogram memory 9 receives address information from the sequence control section 20, and
The microinstruction stored at that address is output to the pipeline register 10. The pipeline register 10 is a register that holds the microinstruction currently being executed for a certain period of time, and the output of this pipeline register 10 is sent to the sequence control unit 20, arithmetic unit, etc. (not shown). , control these.

Here, regarding the operation of the sequence control unit 20, microinstructions (including branch operation codes, etc.) are transferred to the pipeline register 1.
0, and the sequence control section 2
0 instruction - sent to decoder 8, multiplexer 6 and register 7, respectively.

The main control of the instruction decoder 8 that receives the microinstruction is the multiplexer 6 that selects the address for the next microinstruction.
A predetermined selection control signal is sent to and controlled by the program counter 4 by controlling the stack file 3 when executing a CALL instruction, RET instruction (RETURN instruction), etc. This is for writing to or reading from file 3.

Here, the multiplexer 6 is supplied with the output of the program counter 4 and the stack file 3, which indicate the address +1 of the microprogram currently being executed, and is further supplied with the output of the stack file 3, which indicates the address of the microprogram currently being executed. A branch address is provided from register 7, and based on these, a selection control signal from instruction decoder 8 is received to select one of these outputs. The output is sent as address information to the address input section of the microprogram memory 9, and is also sent to the incrementer 5, and the result is taken into the program counter 4 as the execution address + 1 address, which is the next address currently being executed. This will show the address of .

Note that register 7 is a register that holds branch address information of microinstructions,
A register input selection signal from instruction decoder 8 is input to multiplexer 6 to select it.

Here, the output of the program counter 4 is sent to the multiplexer 6 and the stack file 3, and when the CALL instruction is executed, the output of the program counter 4 is sent to the multiplexer 6 and the stack file 3.
is written to the stack file 3.

By the way, this stack file 3 is connected with a stack pointer 2 indicating its storage address, and the stack file 3 and stack pointer 2 are controlled for reading and writing by an instruction decoder 8, respectively. will be done.

For example, when a CALL command is issued for a subroutine, the address information that is the return address of the subroutine is transferred from the program counter 4 to the stack file 3, and at this time, the value of the stack pointer 2 is changed to -
Do 1. At the time of the RET command, the value of the stack pointer 2 is increased by 1 in order to retrieve the return address from the stack file 3, address information is read from the stack file 3, and is output to the multiplexer 6.

Here, the contents of the program counter 4 are Pc, the contents of the stack file 3 are F, the contents of the register 7 are R, the contents of the branch address etc. from the microinstruction are D, and the multiplexer is 6 input section Pc, F,
Displayed as R,D.

Note that 11 is an instruction line, 12 is a branch address line, and 13 is a microprogram memory address line.

[Problem that the invention seeks to solve]

Sequence control section 2 with such a configuration
0 has stack file 3 in its sequencer section, and the size of stack file 3 is:
It is small, about 4 to 8 words, and has a problem in this respect.

In order to increase the capacity of the stack file 3, it is conceivable to place the stack file 3 externally, as shown in FIG. At this time, as seen in the sequence control section 21 in FIG.
When the stack file address line 14, the stack file input/output data line 17, and the stack control line (read/write signal line) 15 are provided independently, the number of input/output lines from the sequence control section 21 increases, and the sequence control Part 21
This is a drawback when converting to LSI.

In the figure, 16 is a 3-state driver, and P is a signal for setting this to a high impedance state.

[Purpose of the invention]

The present invention was made in view of the problems and drawbacks of the prior art, and it solves these problems and improves the startup of a microprogram sequencer (sequence control section of a microprocessor unit). To provide a microprogram control system that requires fewer input/output lines even if a stack file is provided externally, and that can provide a large capacity stack file suitable for LSI implementation.

[Means for solving problems]

In order to achieve such an objective, the present invention
The stack file includes a microprogram memory, a stack file, a sequence control unit that sends address information to the microprogram memory, and a pipeline register that holds microinstructions output from the microprogram memory. A stack file is formed outside the sequence control unit, and the sequence control unit outputs an address line and its control line to the stack file, and outputs an input/output data line of the stack file and the microprogram memory. The stack file is shared with the address line of the stack file, and the execution time of the instruction for manipulating the stack file is set to at least two clocks to access the stack file, and when the stack file is manipulated, the pipe is The microprogram control system is characterized in that the sequence control unit transfers data to and from the stack file via an address line to the microprogram memory by locking the output of the line register. It is.

[Effect]

According to the present invention as described above, when operating a stack file, the output of the pipeline register can be locked from the sequence control section, and the pipeline clock signal is thinned out.
It is possible to allocate at least 2 clocks for the execution time of stack operation commands and at least 1 clock for the execution time of stack control commands such as CALL commands and RETURN commands, and to perform data input/output with an externally installed stack file. can.

As a result, the input/output data line of the stack file can be shared with the address line of the microprogram memory, and the sequence control section transfers data to and from the stack file via the address line for the microprogram memory. This eliminates the need for input/output data lines for the stack file, and reduces the number of lines connecting the sequence control section to external circuits.

As a result, a sequence control section suitable for LSI implementation can be realized in a microprocessor unit, etc., and the capacity of the stack file can be increased.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram of a microprocessor unit according to an embodiment to which the microprogram control system of the present invention is applied, and FIGS.
2A and 2B are diagrams each showing a timing chart of the sequence control. Note that the same reference numerals as in FIGS. 3 and 4 are used.

Sequence control section 22 shown in FIG.
The stack file input/output data line 17 of the sequence control unit 21 shown in FIG. When operating the stack file 3, the output of the pipeline register 10 can be locked from the sequence control section 22.

That is, the output of the multiplexer 6 is output to the microprogram memory 9 side via the 3-state driver 16, and the output of the pipeline register 10 is locked by sending a lock signal from the sequence control section 22 to the lock control line 18a. This signal is input to the OR operation circuit 19 to block the rising of the clock signal CLK input to the other input terminal of the OR operation circuit 19, and the pipeline signal input to the pipeline register 10 is input to the pipeline register 10. The operation of the pipeline register 10 is locked by thinning out the clock signal 19a.

Note that the sequence control unit 22, pipeline register 10, etc. operate in synchronization with this clock signal CLK.

Incidentally, due to the above configuration, the multiplexer 6 does not need a terminal F for receiving an address corresponding to the stack file 3.

Now, to briefly explain the operation of this microprogram control system, the microinstructions stored in the microprogram memory 9 are executed according to the address information sent from the sequence control section 22 via the microprogram memory address line 13. It is accessed and taken into the pipeline register 10 in synchronization with the clock signal CLK.

That is, the execution order of microinstructions in the microprogram memory 9 is controlled by address information from the sequence control section 22.

Hereinafter, the stack file 3 is accessed according to the timing charts shown in Figures 2a and 2b.
The execution operation will be explained using the CALL instruction and its RET instruction as an example.

As shown in Figure 2a, when the CALL instruction is executed, in state _T1 of the clock signal CLK as shown in a, the CALL instruction code is output from the pipeline register 10 as shown in b, and this is confirmed. Then, it is decoded by the instruction decoder 8 of the sequence control section 22.

On the other hand, for the pipeline register 10, c
As shown in the figure, the pipeline lock signal that locks the operation of the pipeline register 10 rises together with the state _T1 of the clock signal CLK, and the OR
After passing through the operation circuit 19, as shown in d, the pipeline lock signal is thinned out by one and its output 19a is generated and sent to the pipeline register 10.

As a result, as shown in f, in state T ₁ ,
The value of the program counter 4 is outputted from the sequence control unit 22 as address information for the microprogram memory 9. Then, the output address information is changed to the state of the clock signal CLK by the stack write signal seen at e.
Last rising edge in T ₁ (or state T ₂
is written to the stack file 3 at the first rising edge of the signal (the same applies hereafter).

In the above operation, since the pipeline clock signal 19a (see d) is thinned out in state _T1 , the contents of the pipeline register 10 do not change.

Now, in the next state _T2 , a branch instruction based on the CALL instruction is output as shown in f as address information of the sequence control unit 22, and at the final rise of state _T2 , the branch instruction specified by this branch address is output. The microinstruction stored in the microprogram memory 9 is taken into the pipeline register 10, and the instruction is executed in state _T3 .

Furthermore, as shown in g, the stack pointer is
At the last rising edge of state _T2 , it is decremented and its value goes from N to N-1 in state _T3 .

The above is the operation of the CALL instruction,
As a result, when a subroutine is called and a predetermined process is executed, a RET command is issued to return to the main program at the end.

FIG. 2b shows the operation for this RET instruction.

State T ₁ of clock signal CLK seen in part a
Then, as shown in b, when the RET instruction code (RETURN instruction) is input from the pipeline register 10 to the sequence control unit 22, the CALL
As with the instruction, the pipeline lock signal 19a is output as shown in c and d, and the pipeline clock signal is thinned out.

Then, as shown in e and h, the stack read signal and the 3-state driver ₁ are activated in state T1.
A signal P with 6 set to high impedance is output. As a result, the 3-state driver 16 becomes a high impedance state, and the multiplexer 6
It does not affect the other side, and any influence from it is prevented.

At the same time, as shown in g, stack pointer 2 is incremented and its value becomes N-1.
As shown in f, the contents of address N of stack file 3 are changed from stack file 3 to N.
It is determined after the access time (TAC) and is sent out from the stack file 3 as address information of the microprogram memory 9 in state _T2 .

The microinstruction in the microprogram memory 9 specified by this address is read out and taken into the pipeline register 10 at the final rise of state _T2 .

At this time, the output state of stack file 3 is
_T1 is simultaneously sent to the incrementer 5 and incremented, and then the program counter 4
be taken into account.

In the next state _T3 , by the RET instruction,
The microinstruction specified by the return address output from the stack file 3 will be executed.

In this way, the pipeline clock signal is thinned out using the lock signal 18a of the pipeline register 10, the execution time of the stack operation instruction is set to 2 clocks, and 1 clock is allocated to the execution time of the stack control instructions such as the CALL instruction and the RETUN instruction. hand,
Data transfer (including data exchange) can be performed with stack files located externally.

Moreover, since the stack file is taken out from the sequence control section and the data line of the micromemory is used, its capacity can be freely selected to be large according to the micromemory.

As explained above, the circuit that locks the clock of the pipeline register in the embodiment is a control circuit for performing data transfer with the stack file, and if it performs such control, it is suitable for the embodiment. The present invention is not limited to, and can be realized using various logic circuits.

Also, instructions for operations on stack files are processed in two clocks, which is
The stack file may be determined in accordance with the control of the sequence control unit, and the stack file may be any storage unit with a stack function such as a so-called stack memory. It is something that

[Effects of the Invention] As can be understood from the above explanation, the present invention comprises a microprogram memory, a stack file, a sequence control unit that sends address information to the microprogram memory, and a microprogram memory. The sequence control section has a pipeline register that holds microinstructions output from the
Since data transfer to and from the stack file is performed via address lines for the microprogram memory, there is no need for input/output data lines to the stack file, reducing the number of connection lines between the sequence control section and external circuits. This means that less is required.

As a result, a microprogram sequencer suitable for LSI implementation can be realized in a microprocessor unit, etc., and the capacity of the stack file can be increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microprocessor unit according to an embodiment to which the microprogram control system of the present invention is applied, FIGS. 2a and 2b are diagrams showing the timing chart of its sequence control, and FIG. FIG. 4 is a block diagram of a microprocessor unit to which a conventional microprogram control system is applied. FIG. 4 is an explanatory diagram of the structure shown in FIG. 3 when the stack file is connected to the outside. 1...Microprocessor unit, 2...Stack pointer, 3,...Stack file, 4
...Program counter, 5...Incrementer, 6...Multiplexer, 7...Register, 8
...Instruction decoder, 9...Micro program memory, 11...Pipeline register, 18a...Pipeline clock signal, 1
8b...Clock signal (CLK), 19...OR type operation circuit, 19a...Pipeline clock signal, 20, 21, 22...Sequence control section.

Claims (1)

[Claims] 1 comprising a microprogram memory, a stack file, a sequence control unit that sends address information to the microprogram memory, and a pipeline register that holds microinstructions output from the microprogram memory; A stack file is formed outside the sequence control unit, and the sequence control unit outputs an address line and its control line to the stack file, and outputs an input/output data line of the stack file and the microprogram. The stack file is shared with the memory address line, and the execution time of the instruction for manipulating the stack file is at least two clocks to access the stack file.Furthermore, when the stack file is manipulated, the sequence control section Locking the output of the pipeline register, the sequence control section:
A microprogram control system characterized in that data transfer to and from the stack file is performed via address lines for the microprogram memory.