JPH0337220B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an interrupt control method in a data processing system, and particularly in a system where a CPU and an input/output adapter operate independently and asynchronously, the present invention relates to an interrupt control method in a data processing system. CPU at interrupt request
The present invention relates to an input/output interrupt control method that enables faster input/output processing by shortening the time occupied by the interrupt.

[Conventional technology]

FIGS. 2 and 3 show two examples of conventional typical input/output interrupt control methods. In both figures, 1 is
2 is a main storage device, 3 is a bus, 4 and 5 are input/output adapters, 6 is an input/output device #1, 7 is an input/output device #2, and 8 is interrupt information.

In the example shown in FIG.
When the interrupt request signal is raised to 1, the CPU 1 checks the interrupt mask, accepts it if it is not masked, directly reads the interrupt information from the interrupt information area 8 of the input/output adapter 4, and analyzes the cause of the interrupt. That is, the contents of the cause of the interrupt and the machine number #1 of the input/output unit of the interrupt requesting device are identified, the corresponding control command information is determined, and the information is written to the input/output adapter 4 for control.

Further, in the example shown in FIG. 3, in response to an interrupt request 'from the input/output adapter 4, the CPU 1 notifies interrupt permission', and the input/output adapter 4 responds by
The interrupt information 8 and the machine number #1 of the input/output unit are stored at a predetermined fixed address in the main storage device 2. The CPU 1 analyzes the cause of the interrupt based on this information, sets control command information, and controls the input/output adapter 4.

[Problem that the invention seeks to solve]

As seen in the examples in Figures 2 and 3, in the past, it was necessary to transfer interrupt information from the input/output adapter to the CPU each time an interrupt request was received.
During this time, the CPU was occupied, causing a problem with other processes being delayed.

[Means for solving problems]

In order to solve the above problems, the present invention notifies the input/output adapter in advance of the interrupt information storage address in the main storage device for each input/output device number, and the input/output adapter When the end interrupt is raised from the input/output device of
without immediately raising an interrupt request to the CPU,
Before that, the interrupt information is stored in the previously notified address in the main memory, and then an interrupt request is sent to the CPU.

According to the configuration of the present invention, in a data processing system in which the CPU and the input/output adapter operate asynchronously, the CPU receives interrupt information of the main storage device that is predetermined for each input/output device number for the input/output adapter. The storage area address is notified, and when the input/output adapter makes an interrupt request to the CPU, it first stores the interrupt information in the interrupt information storage area notified in advance, and then
Make an interrupt request to the CPU, in response, make an interrupt request from the CPU, and in response
When an interrupt permission notification is received from the CPU, the relevant input/output device number is notified to the CPU, and the CPU accesses the corresponding interrupt information storage area based on the input/output device number notified from the input/output adapter. The feature is that it extracts the data and performs interrupt processing.

[Action of the invention]

According to the present invention, the CPU does not need to perform processing to capture interrupt information when receiving an interrupt request from an input/output adapter, and only needs to refer directly to a predetermined address in the main storage device using only the model number of the input/output device. The burden of this will be reduced.

〔Example〕

FIG. 1 is a configuration diagram of a system according to an embodiment of the present invention. In the figure, 1 is a CPU, 2 is a main storage device, 3 is a bus, 4 and 5 are input/output adapters, 6 is an input/output device #1, 7 is an input/output device #2,
8 and 8' indicate interrupt information for input/output devices #1 and #2, respectively; 9 and 9' indicate unit control word UCW#1 for input/output devices #1 and #2, respectively;
UCW #2, 10, and 10' are interrupt information storage areas for input/output devices #1 and #2, and 11 is a management table that provides correspondence between input/output device numbers and interrupt information storage area addresses. Further, each unit control word UCW is provided with interrupt information storage address areas 9a and 9a'.

The unit control word UCW is used as control information for the input/output adapter to multiplex control multiple input/output devices under it. stored separately. Each has three control states: ready state, operating state, and interrupt pending state. The ready state is a state waiting for activation from the CPU, and is activated when the CPU issues an input/output command, and transitions to the operational state.

In the operating state of the unit control word UCW, the content of the command specified by UCW, such as data transfer, is executed, and the corresponding input/output device is activated to perform data transfer processing. When the end interrupt is raised from the input/output device due to the end of the data transfer, the state transitions to an interrupt pending state. This state is maintained until the interrupt processing by the CPU is completed, and when the interrupt processing is completed, the device returns to the operable state and returns to the state where it waits for the next activation.

Further, each input/output control word UCW9, 9' has an interrupt information storage address area 9a, 9' as shown in the figure.
a', and the addresses of the interrupt information storage areas 10 and 10' of the main storage device 2 are set by the CPU 1 at the time of IPL (initial program loading), respectively.

The input/output adapter 4 uses the unit control word UCW function described above to control each input/output device 6, 7,
…and the main storage device 2, the CPU
Execute asynchronously and independently from

The input/output adapter 4 responds to the end interrupt from the input/output device and issues an interrupt request to the CPU 1, but prior to that, interrupt information 8, 8', . . .
The interrupt information in the unit control word UCW
Interrupt information storage areas 10, 10', of the main storage device 2 pointed to by the interrupt information storage addresses in 9, 9', .
Transfer to...

The interrupt information includes the command address at the end of data transfer, control flag, remaining byte count, input/output device status, input/output adapter status, etc.

The input/output adapter 4 stores the interrupt information in a designated area of the main storage device 2, and then sends an interrupt request signal to the CPU 1. When there is a response from the CPU 1 indicating acceptance, the CPU 1 notifies the input/output device number of the interrupt request source.

On the other hand, when the CPU 1 detects the interrupt request signal from the input/output adapter 4, the CPU 1 checks the mask and, if it is acceptable, notifies the input/output adapter 4 of acceptance. Next, when the machine number of the input/output device is sent, the management table 11 of the main memory 2 is referred to, the address of that machine number is obtained, and the corresponding address in the interrupt information storage area 10, 10',... Read interrupt information from the area.

Subsequently, the CPU 1 notifies the input/output adapter 4 of receiving the interrupt information. The input/output adapter thereby terminates the operation of the input/output device. In other words, the UCW is made operational.

Next, using the time chart in Figure 4,
A series of operations of the illustrated embodiment system will be schematically explained.

is at IPL and unit control word UCW
The interrupt information storage address is set. UCW becomes operational.

Then, the CPU activates the input/output adapter, UCW #1 becomes operational, and as a result, the input/output adapter activates the input/output device #1.

Then, data transfer between the main storage device and input/output device #1 is executed.

In this case, the input/output adapter that receives the end interrupt from the input/output device #1 puts the UCW #1 into an interrupt pending state and stores it in the area of the main storage device specified by the interrupt information UCW #1.

Now, send an interrupt request from the input/output adapter to the CPU.

Now, send an acceptance notification from the CPU to the input/output adapter. In response, the input/output adapter returns the input/output device number.

Then, the CPU performs a process of reading interrupt information from the main memory.

Then, the CPU notifies the input/output adapter of receiving interrupt information. And the input/output adapter is
Return UCW #1 to operational status.

〔Effect of the invention〕

As described above, according to the present invention, when an interrupt request is made from the input/output adapter to the CPU, the interrupt request signal is raised to the CPU after the interrupt information is transferred.
The CPU can perform other processing until then, and the processing efficiency of the CPU can be improved.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a system according to an embodiment of the present invention.
2 and 3 are explanatory diagrams of the conventional system, and FIG. 4 is a time chart of an example of the operation of the embodiment system shown in FIG. In the figure, 1 is the CPU, 2 is the main memory, 3 is the bus,
4 and 5 are input/output adapters, 6 and 7 are input/output devices #1 and #2, 8 and 8' are interrupt information, and 9 and 9' are unit control words.
UCW#1 and UCW#2, 9a and 9a' are interrupt information storage address areas, 10 and 10' are interrupt information storage areas, and 11 is a management table.

Claims (1)

[Claims] 1. In a data processing system in which the CPU and the input/output adapter operate asynchronously, the CPU notifies the input/output adapter in advance of the interrupt information storage area address of the main storage device determined for each input/output device model number. When making an interrupt request to the CPU, the input/output adapter first stores the interrupt information in the interrupt information storage area that has been notified in advance, then makes an interrupt request to the CPU, and in response, the When an interrupt permission notification is received, the relevant input/output device number is notified to the CPU, and the CPU accesses the corresponding interrupt information storage area based on the input/output device number notified from the input/output adapter and retrieves the interrupt information. An input/output interrupt control method that is characterized by performing interrupt processing.