JPH0342740B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed communication system, and particularly to a control system for a line interface circuit of a terminal device connected to a high-speed communication line.

[Conventional technology]

A method of configuring a line interface circuit of a terminal device connected to a high-speed communication line mainly using a line control protocol LSI is well known. The line control protocol LSI has the function of serially converting transmission data into a signal format compatible with the line control protocol and transmitting it, the function of converting received data to parallel data, the automatic check sequence transmission function and automatic check function, and the transmission/reception operation. It has a function of notifying the computer of the completion of the process, the occurrence of an error, etc. by means of an interrupt, and operates under the control of the computer.

In other words, when initializing the line control protocol LSI and when an interrupt occurs due to the completion of transmission/reception or the occurrence of an error, the control program issues appropriate control parameters according to the cause of the interrupt in order to properly transmit/receive the next data. It is necessary to carry out However, when the terminal device is connected to a high-speed communication line, the operating speed of the computer is slow compared to the high-speed line speed, and it takes time to execute the interrupt processing when the transmission/reception is completed, and the next time the reception is completed. The disadvantage is that the reception preparation operation for receiving the data is slow, and it takes time until the next data is transmitted after the transmission is completed, which impedes high-speed data transmission.

In addition, in order to perform high-speed data transfer between the line control protocol LSI and the transmit/receive data buffer in memory,
In order to perform a DMA transfer (direct memory access), the computer notifies the DMA controller of the information required for the DMA transfer of the next transmitted/received data (for example, the address of the transmitted/received data buffer) when a transmission/reception completion interrupt occurs. It is necessary to keep it. This processing further increases the burden on the computer when an interrupt occurs and further increases the processing time.

[Problem to be solved by the invention]

The purpose of the present invention is to solve the above-mentioned conventional drawbacks and
By adding a circuit between the line control protocol LSI and the computer that performs part of the processing that the computer should perform when an interrupt occurs from the line control protocol LSI, the load on the computer is reduced and the control program An object of the present invention is to provide a high-speed communication interface circuit that can shorten execution time.

[Means to solve the problem]

The present invention relates to a line control protocol LSI that is connected to a high-speed line and that performs serial-to-parallel conversion of transmitted and received data, automatically transmits a check sequence, performs an automatic check, and transmits an interrupt signal upon completion of transmitting and receiving operations and when an error occurs, and a transmitting and receiving data buffer. A high-speed line interface circuit in which a DMA controller for controlling DMA transfer, a computer for controlling these, a memory having a control program storage area and a transmission/reception data buffer area are connected by a data bus, The memory has a parameter area for storing in advance control parameters to be issued to the line control protocol LSI, interrupt factors, and information regarding the transmission/reception data buffer to be notified to the DMA controller; a means for inputting an interrupt signal from a line control protocol LSI to read necessary control parameters from the memory area and issuing them to the line control protocol LSI; The present invention is characterized by comprising an interrupt control circuit that notifies a controller, writes an interrupt cause in the memory area, and sends an interrupt signal to the computer.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. That is, the terminal device 6 and the computer 2
and the line control protocol LSI 1 are connected to the data bus 9, and the sent and received data is sent to the DMA controller 3.
is DMA-transferred to the transmit/receive data buffer under the control of Reference numeral 8 is the DMA request line. The line control protocol LSI 1 performs parallel-serial conversion of transmitted/received data, interrupts when transmission/reception is completed or an error occurs, and operates under the control of the computer 2, as in the past.

However, in this embodiment, the interrupt control circuit 1
0 to data bus 9, line control protocol
Interrupts from the LSI 1 are input to the interrupt control circuit 10 via the interrupt signal line 7, and interrupt signals to the computer 2 are input from the interrupt control circuit 10 to the computer via the interrupt signal line 7'. Output to 2. and,
The memory 4 connected to the data bus 9 includes a control program storage area a that stores control programs;
In addition to a transmission/reception data buffer area b for temporarily storing transmission and reception data, it has a parameter area c for storing control parameters and other information.

FIG. 2 is a diagram showing an example of setting the memory area in the parameter area c. In the control parameter area 11, an EOI (end of interrupt) command, an error reset command, etc. to be issued to the line control protocol LSI 1 when an interrupt occurs are set in advance. The reception DMA information area 12 includes the DMA transfer destination of the reception data,
That is, parameters indicating the address and length of the received data buffer are set. The transmission DMA information area 13 is an area for setting the buffer address and length of transmission data. The reception interrupt cause area 14 and the transmission interrupt cause area 15 are
This is an area used by the interrupt control circuit 10 to notify the computer 2 of the cause of an interrupt occurrence.

Next, the operation at the time of completion of reception in this embodiment will be explained.

A reception completion interrupt occurs from the line control protocol LSI 1, and is sent to the interrupt control circuit 1 via the interrupt signal line 7.
0, the interrupt control circuit 10 outputs the necessary control parameters from the control parameter area 11 of the memory 4, and the control parameters are input to the line control protocol LSI 1 via the data bus 9. This determination of the interrupt cause is made according to the type of interrupt from the line control protocol LSI 1. For example, if it is a vector interrupt, read the interrupt vector, or if it is a single interrupt, when the interrupt is accepted. This can be determined by referring to input data of a predetermined I/O port. In this manner, the interrupt control circuit 10 outputs a control parameter corresponding to the interrupt factor of reception completion in response to the interrupt signal from the line control protocol LSI 1.

As a result, the line control protocol LSI 1 stops generating interrupt signals according to the control parameters.
Furthermore, when an error occurs as an interrupt factor, error reset processing is performed, such as setting internal memory or registers that hold values indicating the contents to initial values.

Furthermore, the interrupt control circuit 10 reads address information of the receive data buffer to which the next received data is to be transferred from the receive DMA information area 12.
After notifying the DMA controller 3 and setting a parameter indicating normal completion of reception in the reception interrupt cause area 14, an interrupt is made to the computer 2 via the interrupt signal line 7'.

After reading the interrupt factor from the reception interrupt cause area 14 and confirming that the reception has been completed normally, the computer 2 prepares buffer information for the next data to be received in the reception DMA information area 12. . This buffer information is information for the interrupt control circuit 10 to notify the DMA controller 3 when the next reception completion interrupt occurs. In this way, by preparing all the various parameters required when a reception interrupt occurs in the parameter area c in advance, the interrupt control circuit 10 can perform prompt processing according to the cause of the interrupt occurrence. can. The processing executed by the computer 2 upon completion of reception is to confirm the completion of reception and to check the reception DMA information area 12.
The program execution time is greatly reduced, and the next data can be received quickly. Regarding the transmission operation, high-speed processing by the interrupt control circuit 10 is possible in the same manner as described above by preparing necessary parameters in the parameter area c.

〔Effect of the invention〕

As described above, in the present invention, a parameter area is provided in the memory, parameters necessary for processing when an interrupt occurs are prepared in advance, and the above parameters are controlled by the interrupt control circuit. Since the configuration is such that an interrupt to the computer and preparation for transmission/reception are executed based on the parameters read from the area, the load on the computer is reduced and high-speed processing becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.
FIG. 2 is a diagram showing an example of the configuration of the parameter area of the above embodiment. 1... Line control protocol LSI, 2... Computer, 3... DMA controller, 4... Memory, 5... High speed line, 6... Terminal device, 7... Interrupt signal line, 8... DMA request line , 9... Data bus, 10... Interrupt control circuit, 11... Control parameter area, 12... Reception DMA information area, 1
3...Transmission DMA information area, 14...Reception interrupt cause area, 15...Transmission interrupt cause area, a...
...control program storage area, b...transmission/reception data buffer area, c...parameter area.

Claims (1)

[Scope of Claims] 1. A line control protocol LSI 1 connected to a high-speed line, which performs serial-parallel conversion of transmitted and received data, automatically transmits a check sequence, automatically checks, completes transmitting and receiving operations, and transmits an interrupt signal when an error occurs.
, a DMA controller 3 that controls DMA transfer of the transmit/receive data buffer, a computer 2 that controls these, and a memory 4 having a control program storage area and a transmit/receive data buffer area.
and a high-speed line interface circuit in which these are connected by a data bus 9, the memory stores control parameters to be issued to the line control protocol LSI, interrupt factors, and notifications to the DMA controller. It has a parameter area for pre-memorizing information regarding the transmitting/receiving data buffer to be transmitted, and inputs an interrupt signal from the line control protocol LSI, reads necessary control parameters from the memory area, and executes the line control protocol. and means for inputting the interrupt signal to notify the DMA controller of information regarding the transmitting/receiving data buffer, writing an interrupt cause in the memory area, and transmitting the interrupt signal to the computer. 1. An interface circuit for a high-speed communication line, comprising a control circuit 10.