JPH0337867B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and is particularly directed to a flip-flop type semiconductor memory device constructed from a MISFET type semiconductor device.

As a semiconductor memory device, there are four
A flip-flop type dynamic memory type semiconductor memory device consisting of MISFET is known from US Pat. No. 3,541,530. This dynamic memory type semiconductor storage device does not store information by constantly supplying current from the power supply, so no wasted power is consumed. Furthermore, the area of the memory cell can also be reduced. However, since stored information is lost due to leakage, it is necessary to periodically refresh the information. Therefore, a complicated refresh peripheral circuit is required.

On the other hand, in static memory semiconductor memory devices, there is a load MISFET and a drive MISFET.
A flip-flop type memory device is known from US Pat. No. 3,560,764, in which two inverter circuits each comprising a MISFET are cross-coupled. This type of memory device does not require the refresh circuit used in the above-mentioned dynamic memory type semiconductor memory device. However, power consumption is large. In order to reduce this power consumption, it is necessary to
It is necessary to reduce the channel conductivity β (channel width W/channel length l) in MISFET. As a result, the channel length l has to be increased. Therefore, for load
The problem arises that the size of the MISFET increases and the integration density deteriorates. Therefore, in order to reduce the load means and improve the integration density,
It is known from Japanese Patent Application Laid-Open No. 11644/1983 to use polycrystalline silicon made with high resistance by ion implantation as a load means instead of MISFET.
However, it is difficult to make the area occupied by a memory cell as small as that of a dynamic memory type memory cell.

Therefore, there has been a desire for a memory device that has a low integration density and is easy to refresh, comparable to a dynamic memory type memory device.

One object of the present invention is that the cell itself works in a static memory manner, that is, the leakage of charge is always compensated for by a high resistance element, and the data line consists of four
An object of the present invention is to provide a semiconductor memory device that operates in a dynamic memory manner, such as a flip-flop type memory cell made of MISFET _S.

Another object of the present invention is to provide a static memory type semiconductor memory device having a cell area approximately equal to that of a flip-flop type memory cell composed of four _MISFETs .

Another object of the present invention is to provide a semiconductor inverter device suitable for a semiconductor memory device and a method of manufacturing the same.

Still another object of the present invention is to provide a highly integrated MIS type semiconductor memory device with a multilayer wiring structure.

In one embodiment of the present invention, four MISFETs _S constitute a dynamic flip-flop type memory cell that holds charge, which is written information, in an information storage means. The information storage means is supplemented through load means made of high resistance polycrystalline silicon connected to the voltage line.

The objects, features, and effects of the present invention will be clearly understood from the following description of preferred embodiments based on the drawings.

In FIG. 1, a portion 1 indicated by a dashed line is a diffusion layer formed by selectively diffusing impurities of a conductivity type opposite to that of the substrate on the surface of a semiconductor substrate, and portions 2a, 2b, and 2c indicated by broken lines are
is a polycrystalline silicon layer, and 2a is the power line (V _DD
Line), 2b is a line connecting one end of transmission FETQ _3, Q ₄ , the source of driving FET Q ₁ , Q ₂ , the gate of driving FET Q ₂ , Q ₁ , and load resistor R ₁ , R ₂ ,
2c is a word line. 3
3a and 3b are polycrystalline silicon layers constituting load resistors R ₁ and R ₂ , and 3a is R ₁ and 3b is R ₂ . This is formed integrally with the polycrystalline silicon layers 2a and 2b, but has a lower impurity concentration and a higher specific resistance than the polycrystalline silicon layers 2a and 2b.

5a, 5b, 5c are aluminum electrode wiring films, and 5a is a true digital line (d
Line), 5b is the ground line (GND Line), 5c
is the bardate line.
6a and 6b are contact portions between the diffusion layer and the electrode wiring portion that constitute the other ends of the transmission FETs Q ₃ and Q ₄ ;
Portions 7a and 7b indicated by dotted lines are drive _FETQ1 ,
This is the contact part between the silicon gate of Q ₂ and the diffusion layer that forms one end of transmission FETs _{Q 3} and Q ₄ .
This is the portion that is directly contacted to the diffusion layer by the polycrystalline silicon layer. This part of the contact technology is called direct contact.

Figure 2 shows the semiconductor memory device (memory cell) shown in Figure 1.
(memory cell) circuit diagram. In the same figure,
All portions shown within the dashed line frame are made of polycrystalline silicon layers formed at the same time. In other words, the power supply voltage line (V _DD
line) is also the part that bonds the wire for connection with the external lead lead (wire line).
All parts except the bonding pad are made of polycrystalline silicon. Junctures Da and Db are direct contact portions 7a and 7b shown in FIG. 1, respectively.

FIG. 3 is a layout diagram in which four memory cells of FIG. 1 are arranged. In the figure, a broken line indicates a polycrystalline silicon layer, a solid line indicates an aluminum (Al) wiring layer, and a two-dot chain line indicates a direct contact portion. The diffusion region has been omitted to simplify the diagram. Furthermore, in the figure, C ₁₁ ,
_C12 is a contact portion between the diffusion layer and the digit line made of Al in the first memory cell, and shares the contact with other memory cells (not shown). Similarly, C ₂₁ and C ₂₂ are contact portions in the second memory cell, C ₃₁ and C ₃₂ are contact portions in the third memory cell, and C ₄₁ and C ₄₂ are contact portions in the fourth memory cell. , these also share contacts with other memory cells (not shown). For the digital line, both contacts with Al are shared by other memory cells, so from the perspective of one memory cell, only one contact is required.
G ₁ , G ₂ , G ₃ , G ₄ are the first, second, third, and
This is a contact portion between the ground line and the diffusion layer (source region) in the fourth memory cell. Since one contact with the ground line is required for one memory cell, as a result, only two contacts are required for one memory cell. R ₁ and R ₂ are load resistances of the first memory cell, R ₃ and R ₄ are load resistances of the second memory cell, R ₅ and R ₆ are load resistances of the third memory cell, and R ₇ , R ₈ indicates the load resistance of the fourth memory cell. As is clear from the figure, when looking at the arrangement of four memory cells, C ₂₁ , C ₂₂ , G ₂ ,
The second memory cells denoted R ₃ , R ₄ are C ₁₁ , C ₁₂ ,
The first memory cells indicated by G ₁ , R ₁ , and R ₄ are arranged in a horizontally shifted manner. Also, C ₃₁ , C ₃₂ ,
The third memory cells designated G ₃ , R ₅ , and R ₆ are arranged with the first memory cell rotated 180° about point "A". Furthermore, C ₄₁ , C ₄₂ , G ₄ , R ₇ ,
A fourth memory cell, designated R ₈ , is arranged with the third memory cell shifted laterally. These four memory cells are further connected to the L ₁ -L ₁ lines and
Vertical direction (or column direction) with line symmetry on L ₂ −L ₂ line
Arranged in Further, they are arranged in a shifted state in the horizontal direction (or row direction) to form a memory matrix.

Next, the MISFET section and load resistance section within the memory cell will be explained.

Figure 4A is a MISFET, which is a LOCOS (Local Oxidation of Silicon) that is particularly easy to use for multilayer wiring.
Show the structure. 1 is a diffusion layer, 8a is a SiO ₂ film for semiconductor surface passivation, 8b is a gate insulating film,
9 is a semiconductor substrate.

Further, FIG. 4B shows a portion of the polycrystalline silicon layer for loading. 2a, 2b, and 2c are low-resistance polycrystalline silicon layer portions that are used as wiring, and 3a is a high-resistance polycrystalline silicon layer portion that is used as a load resistor. 4 is a CVD-SiO ₂ film. The figure shows the state immediately after the impurity is introduced into the polycrystalline silicon layer.

FIG. 5A (when the room temperature is 25° C.) and FIG. 5B (when the room temperature is 70° C.) shows how much current should be supplied through the load means in order to retain the stored information. This shows a correlation diagram between the holding current I _DM and the applied voltage V _DM in two memory cells for four samples a, b, c, and d.
The holding current I _DM and the applied voltage V _DM are respectively
These are the current flowing through the power supply voltage line (V _DD Line) shown in the figure and the voltage supplied to that line.

As is clear from this figure, when the room temperature is 25°C, even in sample a, which requires a large holding current, when the power supply voltage _VDD is 12V, it is about 5 × 10 ^-8 A per memory cell, This allows information to be retained. Therefore, the power consumption per memory cell is only 0.6×10 ⁻⁶ W (0.6 μW).

Note that as the temperature of the device increases, the current required to retain information increases. This is because the current leaking through the junction increases as the temperature rises. FIG. 5B shows the required holding currents for the same samples a, b, c, and d as in FIG. 5A, and a comparison between the two figures will clarify the above.

Incidentally, leakage current increases as temperature rises, but according to the present invention, the specific resistance of the polycrystalline silicon layer used as the load means decreases as temperature rises, so the supply current decreases as the leakage current increases. There is no fear that information retention will become impossible due to an increase in temperature.

Note that the resistance of the portion of the polycrystalline silicon layer constituting the load means is determined by adjusting the amount of impurity implanted by, for example, ion implantation. FIG. 6 is a correlation diagram showing the correlation between the amount of ion implantation and the resistance value R ₀ .
When the ion implantation amount is 10 ¹⁵ /cm ³ or less, 10 ¹⁰ Ω/
□ and the resistance value are approximately constant values, making it easy to control the resistance value. However, it goes without saying that when the holding current is large, it is necessary to increase the amount of ion implantation in order to lower the resistance value.

Next, the method for obtaining the memory cell of the present invention shown in FIG. 1 will be described in Sections 7A to 7E.
This will be explained using FIG. 8 and FIGS. 8 to 8E.

(1) A semiconductor substrate having a specific resistance of 8 to 20 Ωcm is prepared, and a thermal oxide film with a thickness of 1 μm is formed on the surface of this substrate.

(2) The thermal oxide film is selectively etched to expose the surface of the semiconductor substrate where the MISFET is to be formed.

(3) After that, a thickness is applied to the exposed semiconductor substrate surface.
A gate oxide film (SiO ₂ ) 12 with a thickness of 750 to 1000 Å is formed. (See FIGS. 7A and 8A) (4) Parts of the gate oxide film 12 that should be in direct contact with the polycrystalline silicon layer are selectively etched to form direct contact holes 13 and 14. (See Figures 7B and 8B) (5) Silicon is deposited by CVD (Chemical Vapor
Deposition method is used to deposit the thickness
Form a polycrystalline silicon layer of 3000-5000 Å.

(6) Selectively etching the polycrystalline silicon layer 14. Then, the remaining polycrystalline silicon layer 14
Using the mask as a mask, the gate oxide film 12 is selectively etched. (See Figures 7C and 8C) (7) The entire main surface of the semiconductor substrate 10 is coated by CVD.
Deposit a CVD-SiO ₂ film to a thickness of 2000-3000 Å.

(8) The above applies only on the polycrystalline silicon layer that is to be used as a resistor.
The CVD-SiO ₂ film 15 is selectively left.

(9) Using the polycrystalline silicon layer as a mask, diffuse phosphorus into the semiconductor substrate 10 to increase the impurity concentration.
A source region 16 and a drain region 17 of 10 ^{to 20} atoms/cm ³ are formed. At this time, impurities are also introduced into the polycrystalline silicon layer and the gate electrode 1
8. Direct contact 7b, Word line 2
0 and V _DD line 21 is formed. (7th D
8D) (10) Remove the CVD-SiO ₂ film 15 and apply PSG (Phospho-Sili-cate) over the entire main surface of the semiconductor substrate 10.
-Glass) film 20 is formed to a thickness of 7000 to 9000 Å.

(11) After that, Al is deposited on the entire main surface of the semiconductor substrate 10 to form an Al film 21 with a thickness of 1 μm.

(12) Selectively etching the above Al film to create ground lines 22 and digit lines.
23 and 24 are formed. (See FIGS. 7E and 8E) The method for obtaining the memory cell of the present invention has been described above, but the following modifications can be made to this method.

(a) To adjust the resistance values of load resistors R ₁ and R ₂ ,
From the relationship shown in FIG. 6, after the above step (5), impurity ions are implanted into the polycrystalline silicon layer 14.

(b) Although the CVD-SiO ₂ film 15 is formed after step (6), the CVD-SiO ₂ film 15 may be formed over the entire main surface of the semiconductor substrate 10 while leaving the gate oxide film 12. In this case, as shown by S in FIG. 8C, the difference in level between the oxide film 11 and the polycrystalline silicon layer 14 is not large, and the CVD-SiO ₂ film 15 is in a good adhesion state.

(c) Instead of using a method of external deposition like the CVD-SiO ₂ film 15, the surface of the polycrystalline silicon layer 14 may be thermally oxidized, and the thermal oxide film formed on the polycrystalline silicon layer 14 may be used as a mask. . Particularly in this case, since the side surfaces of the polycrystalline silicon layer can be sufficiently covered, introduction of impurities can be sufficiently prevented.

(d) Since the memory cell of the present invention has multilayer wiring, it is preferable to have a LOCOS structure as shown in FIG. 4A, which allows for planarization. Examples of LOCOS structures are described below.

(e) The film to cover the polycrystalline silicon layer where the resistor is to be formed is not limited to the CVD-SiO ₂ film.
An insulating film such as a Si ₃ N ₄ film may be used.

Next, in a complementary MIS type semiconductor memory device,
An example will be explained in which each memory cell is configured with a flip-flop using a high-resistance polycrystalline silicon layer as the load means and a single conductivity type MISFET as the switch means, and the peripheral circuit is configured with a complementary MIS type circuit. do.

FIG. 9 shows a basic circuit diagram using a CMIS (complementary MIS) circuit as a peripheral circuit.

1 is a memory cell, N-channel MISFETM ₁
~ _M4 , and high resistances _R1 and _R2 . That is, one inverter is configured by the N-channel MISFETM ₁ and the high resistance R ₁ , and another inverter is configured by the N-channel MISFETM ₂ and the high resistance R ₂ . A flip-flop, which forms the main part of the memory cell, is constructed by cross-coupling these two inverters.

M ₅ and M ₆ are P-channel type MISFETs that constitute the pre-charge circuit PC, and function as pre-charge transistors for dynamic operation.

_M7 to _M10 are for configuring sense up SA
MISFET, M ₇ and M ₉ are P channels
MISFETM ₈ and M ₁₀ are P-channel MISFETs. _M11 is P channel MISFET for switching
It is.

A pair of data lines l ₁ and l ₂ are connected to the sense amplifier SA, and lines l ₁ ' and l ₂ ', although not shown, are connected to the output of the data input circuit.

In this circuit, _MISFETM5 and _M6 are turned on and off according to the low level and high level of the chip selection signal. By turning on MISFETM ₅ and M ₆ , the data line is
Capacitors (not shown) associated with l ₁ and l ₂ are charged. MISFETM ₃ and M ₄ are turned on by the high level of the word signal. sense amplifier
For SA, the clock signal φ becomes high level.
When MISFETM ₁₁ is turned on, it becomes operational.

When reading data from memory cells, by setting the word signal to high level while the chip selection signal CE is at high level,
MISFETM ₃ and M ₄ are turned on, and the states of data lines l ₁ and l ₂ are set according to the contents of the memory cells.
Thereafter, the clock signal φ becomes high level, so that the sense amplifier SA becomes operable, and the sense amplifier SA performs an amplification operation in accordance with the state of the data line.

Data is written to memory cells using the data line.
This is done by setting the word signal to high level with the states of l ₁ and l ₂ set.

As mentioned above, in the CMIS type semiconductor memory device,
N-channel as a means of driving memory cells
A MISFET is used, high-resistance polysilicon is used instead of a P-channel MISFET as the load means, and a normal CMIS type circuit is used as the memory cell peripheral circuit.

Next, a specific embodiment of such a CMIS type semiconductor memory device will be described below.

Figure 10 shows a 4K bit CMOS static
This is a block diagram of RAM. In the figure, A ₀ to A ₁₁ are terminals to which external address signals are supplied, D _IN and D _OUT are input and output terminals, respectively, and write enable signal terminals and
CE indicates chip enable signal terminal. 50-6
1 is an address buffer circuit, 62 is an input buffer circuit, 63 is a write enable buffer circuit, 64
is a chip enable circuit, 65 is an output buffer circuit, 66 is a _ROW decoder circuit, 67 is a clock generation circuit, and 68 is a memory cell matrix (memory cell matrix).
cell matrix), there are 64 cells in the row and 64 cells in the column. 69 is column input circuit, 7
0 indicates a column decoder circuit.

Next, each circuit section shown in FIG. 10 will be specifically explained.

FIG. 11 shows the row decoder circuit 66, clock generator circuit 67, and memory cell matrix circuit in FIG.
circuit) 68, column input/output circuit and column decoder circuit (column decoder circuit) 70
FIG. In the figure, RD ₁ ,
RD ₂ ... is the column address decoder circuit (row
It is located in the center of the memory cell matrix, that is, between the 32nd and 33rd columns, to increase speed. LD ₁ ...LD ₁₅ , LD ₁₆ are column address decoder circuits
It is. This column address decoder circuit outputs two address output signals, one true and one false (bar). Therefore, from LD ₁ , address output terminals Y ₁ , Y ₂ , from LD ₂ , address output terminals Y ₃ ,
Y ₄ , LD ₁₅ to address output terminals Y ₂₉ , Y ₃₀ and
Address output terminals Y ₃₁ and Y ₃₂ are drawn out from LD ₁₆ . Decoder driver circuits (D ₁ , D _{3 .} . . D ₃₀ , D ₃₂ ) are connected to these address output terminals, respectively.

This decoder driver circuit outputs two address output signals. Therefore, 32 decoder driver circuits can select from column address 1 to column address 64. Then, only one column is selected by the address control signal a5,5. SA ₂ , SA ₆ ,
SA ₆₁ and SA ₆₃ are sense amplifiers, which correspond to the sense amplifier SA in FIG. PC ₂ , PC ₆ , PC ₆₁ ,
PC ₆₃ is a precharge circuit, and M ₅ in Fig. 9,
Compatible with pre-charge circuit PC consisting of _M6 pre-charge transistors. and,
N-channel MISFETM ₂₀ corresponds to M ₁₁ in FIG. Note that the P channel MISFETM ₂₁ is a precharge transistor, which holds the sense amplifier line SAL at a high level (V _DD level) until the information is determined, and the sense amplifier SA ₂ ,
Disable SA ₆ , SA ₆₁ , and SA ₆₃ . Especially if measures are taken to maintain it at a high level,
These sense amplifiers will not be activated by external noise. In the case of Figure 9,
When MISFETM ₁₁ is OFF, the junction J becomes floating, making it easy for noise to enter.
Therefore, there is a possibility of operation in a state where the information on l ₁ and l ₂ is not determined.

Next, specific circuits for obtaining signals input to the circuit shown in FIG. 11 are shown in FIGS. 12 to 19.
As shown in the figure.

FIG. 12 shows the chip enable buffer circuit 64 of FIG. 10, which generates internal signals CE ₁ , CE ₁ , CE ₂ , CE ₃ , φy, and X from an external chip enable signal CE. In addition, the switch in Figure 12
The state of SW indicates the state in which the signals shown in the figure are drawn from each output terminal when the chip enable signal CE is input.

Furthermore, in order to draw out the signals shown in the figure from each output terminal by inputting a chip enable signal, the state of the switch SW can be changed. Such switching of the switch SW is normally realized by slightly changing the wiring within the semiconductor integrated circuit using a technique known as master slicing.

FIG. 13 shows the write enable buffer circuit 63 of FIG. 10, which generates internal signals φ _R , φ _D from external write enable signals. In this case, as in Fig. 12, CE,
The switching is performed by the master slice.

FIG. 14 shows the data inbuffer circuit 62 of FIG. 10, which receives an external data input signal D _IN
Generate internal data signals d _io and _io from .

FIG. 15 shows the address buffer circuits 51 to 54 in FIG. 10, which receive address signals A ₀ from outside.
Generate internal address signals _a0 - _a4 and _a0 - _a4 from ~ _A4 .

FIG. 16 shows the address buffer circuits 55 and 56 shown in FIG.
Internal address control signals _{a 5} , ₅ and internal address signals a ₆ , ₆ are generated from A ₅ , A 6 , respectively.

FIG. 17 shows the address buffer circuits 57 to 61 in FIG.
_A7 ~ _A11 to internal address signals _a7 ~ _a11 and ₇ ~
Generate a ₁₁ .

FIG. 18 shows a timing pulse generation circuit that generates internal signals φ _x , φ _x1 , φ _x2 from internal address signals a ₀ to a ₁₁ , ₀ to ₁₁ and internal signal CE ₃ .

FIG. 19 shows a timing pulse generation circuit that generates internal signals φ _y , A ₁₁ , φ _M , φ _M from internal signals φ _y .
to occur.

External signals are generated as shown in the timing charts shown in FIGS. 20 to 22. In particular, Fig. 20 is a timing chart for a read cycle, Fig. 21 is a timing chart for a write cycle, and Fig. 21 is a timing chart for a write cycle.
Figure 2 shows a timing chart when reading and writing are performed in one cycle.

In FIGS. 20 to 22, t _C is the cycle time, t _AC is the access time, t _CE is the chip enable width, t _P is the chip enable precharge time,
t _AH is address hold time, t _AS is address setup time, t _OFF is output buffer delay time, t _WS is write enable setup time, t _DIH is input data hold time, t _WW is write enable width, t _MOD is the modification time, t _WPL
is → time, t _DS is input data setup time, t _WH is write enable hold time,
t _T is the rise/fall time.

Next, the structural features of the above-mentioned CMIS type semiconductor device and its manufacturing method will be explained.

FIG. 23 is a sectional view of such a CMIS type semiconductor memory device.

103 is an N-type semiconductor substrate, 104 is a P-type semiconductor well, 105 is a thick SiO ₂ film, 106 is a gate insulating film, 107 is a polycrystalline silicon gate electrode, 1
Reference numeral 08 denotes a polycrystalline silicon layer formed at the same time as the gate electrode, which is partially masked by the SiO ₂ CVD film 109, and impurity doping is prevented in the portion 108a, so that the resistance remains high. This polycrystalline silicon layer 108 is used as a high resistance material serving as a load means of the memory cell. 110 is P
Source of channel MISFET, 111 is drain of P channel MISFET, 112 is source of N channel MISFET, 113 is P channel
The drain of the MISFET, 114 is a PSG film for surface passivation, and 115 is an aluminum electrode.

24A to 24J show the method of manufacturing such a semiconductor memory device in the order of steps.

(1) Oxidize the surface of the N ⁺ type semiconductor substrate 103 to form SiO ₂
A film 105 is formed, and the portion of the SiO ₂ film 105 where a well is to be formed is removed by photoetching. Then, in this state, ions are implanted into the well. 116 is a photoresist film. (See FIG. 24A) (2) Next, a P-type semiconductor well 104 is formed by diffusing P-type impurities. (See Figure 24B) (3) Remove the SiO ₂ film 105 formed on the semiconductor surface, then thinly oxidize the surface to form an insulating film 118, and then remove the nitride (Si ₃ N ₄ ) film 11.
7 is deposited on the surface, and then a photoresist film 116 is formed. Then, the nitride film 117 is photoetched using the photoresist film 116 as a mask. (Second
(See Figure 4C) (4) Furthermore, a photoresist film 116 is applied to the area other than the well area. In this state, ions are implanted. (See FIG. 24D) (5) In this state, an isolation film for element isolation is formed by selective oxidation using the nitride film 117 as a mask, and the nitride film 117 used as a mask is removed. Then, the back surface of the semiconductor substrate 103 is also etched. (See Figure 24E) (6) Heat and oxidize the semiconductor surface to form the gate insulating film 10.
6 and then a polycrystalline silicon layer 10
7,108 is formed. Reference numeral 107 constitutes a gate electrode, and reference numeral 108 constitutes a high resistance element serving as a load means for the memory cell. Note that after forming the polycrystalline silicon layers 107 and 108, thin ions are implanted to control the specific resistance of the high-resistance element to a constant value.
(See Figure 24F) (7) Form a mask 119 on the semiconductor well. In this state, window openings for source and drain diffusion of the P-channel MISFET are provided, and P-type impurities are diffused through the window openings to form the source 110 and
A drain 111 is formed. (See Figure 24G) (8) Remove the above mask and cover the P channel section with a mask 119. Note that at this time, a portion of the polycrystalline silicon layer 108 is also covered with a mask. This is because it is necessary to prevent impurities from diffusing in order to maintain a high resistance state. (24th H
(See figure) In this state, window openings for source and drain diffusion are provided, and N-type impurities are diffused through the window openings to form the source 112 and drain 113.

(9) After that, a PSG film 114 is formed. this
The PSG film 114 is photo-etched to form a window opening for electrode extraction. (See Figure 24I) (10) After that, form an aluminum electrode. (Second
(See Figure 4J) The present invention has been described above based on specific examples, and according to the present invention, the following effects can be expected.

(a) The resistor of the high-resistance element made of polysilicon used as the load means has a high specific resistance, so it only requires an extremely small area. The value is set to a value that can supply a minute current sufficient to compensate for the leakage of charge, which is information. For example, a resistance value of approximately 10 GΩ may be sufficient. Note that leakage is caused by a current flowing through a parasitic capacitance junction and a tailing current flowing through a MISFET in an OFF state.

By flowing a small amount of current to supplement this to the information storage means (capacitor) through the polycrystalline silicon high resistance material used as the load means,
Inside the cell, it works using a static memory method that does not require periodic refresh.

On the other hand, outside the cell, Figure 9 or 11
As shown in the figure, dynamic operation is possible in which the precharge circuits (PC, PC ₁ , PC ₄ . . . ) are operated using the chip enable signal. Of course, it is not always necessary to use a precharge circuit to drive the clock, and a static operation may be performed. Even in this case, a static memory type semiconductor memory cell having a cell area approximately equal to that of a flip-flop type memory cell composed of four dynamic memory type MOSFETs can be obtained.

Incidentally, the cell area of the present invention is based on a flip-flop memory cell (6MOS-memory
Compared to Cell), the area ratio is extremely small at 0.38. Furthermore, compared to a 6MOS memory cell using a depletion type MOSFET as a load means, which is known to be able to reduce the cell area, the area ratio of the cell of the present invention is 0.65.
and can be made smaller. Additionally, CMOS
Compared to the conventional memory cell, the area ratio of the present invention is extremely small at 0.31. especially,
In the case of CMOS type memory cells, P channel
In order to provide a well junction between the MOSFET and the N-channel MOSFET, a gap above a certain level must be provided, and this has been a major cause of lowering the degree of integration. However, according to the present invention, one channel type of the complementary MIS type circuit is used as a memory cell.
Using only MISFET, the other channel type
Since MISFETs are not used, it is not necessary to provide wide gaps between MISFET elements, so high integration can be achieved.

(b) Complementary because only a small amount of current flows through the polycrystalline silicon high-resistance material that is the load means, and it can be refreshed sufficiently.
Power consumption can be almost the same as MIS type memory. Of course, a refresh circuit is also not required.

On the other hand, peripheral circuits are complementary.
By using an MIS type circuit, the characteristics of a complementary MIS type circuit can be fully utilized.

(c) Since the polycrystalline silicon layer constituting the load means and the polycrystalline silicon layer for applying the power supply voltage to the load means can be formed integrally, a special area for contacting the two is required. This makes it unnecessary, and the area occupied by the contact region can be reduced.

That is, in a memory matrix (memory array) consisting of a plurality of memory cells, the power supply voltage line and the load means are constructed of an integrated polycrystalline silicon layer, and the power supply voltage line and a pad (pad) of aluminum wiring are constructed. is connected outside the memory matrix. Therefore, the number of connection points (the number of contacts) can be extremely small.

This point is not limited to the memory cells mentioned above, but includes load means connected to the terminal to which the power supply voltage is applied and driver means connected to the ground terminal. It can be applied to all semiconductor devices using inverter elements consisting of (means).

[Brief explanation of drawings]

FIG. 1 is a layout diagram of a semiconductor memory device showing one embodiment of the present invention. FIG. 2 is a circuit diagram of the semiconductor memory device shown in FIG. 1. FIG. 3 is a layout diagram in which four semiconductor memory devices of FIG. 1 are arranged. 4A and 4B are cross-sectional views showing the MISFET section and the load resistance section, respectively. FIGS. 5A and 5B are correlation diagrams between the current required to retain information and the voltage used in a semiconductor memory device. FIG. 6 is a correlation diagram between the amount of impurity implanted into polycrystalline silicon and the resistance. 7A to 7E are plan views showing manufacturing steps for obtaining the semiconductor memory device shown in FIG. 1. FIG. 8A to 8E are cross-sectional views of FIGS. 7A to 7E, respectively. Figure 8A is 7A
It is a sectional view cut along the line AA' in the figure. Figure 8B is the 7th
FIG. FIG. 8C is a sectional view taken along the line C-C' of FIG. 7C. FIG. 8D is a sectional view taken along line D-D' in FIG. 7D. FIG. 8E is a sectional view taken along line E-E' in FIG. 7E. FIG. 9 is a circuit diagram showing another embodiment of the present invention, in which a complementary MISFET (hereinafter referred to as CMIS) circuit is used as a peripheral circuit.
Figure 10 is a block diagram of the 4K bit CMIS Static RAM. FIG. 11 is a circuit diagram showing another embodiment of the present invention, and shows a specific circuit diagram of FIG. 10 shown as a block diagram. FIG. 12 is a chip enable buffer circuit diagram used in the circuit shown in FIG. 11. 13th
This figure is a write enable buffer circuit diagram used in the circuit shown in FIG. 11. Figure 14 is the 11th
FIG. 3 is a data inbuffer circuit diagram used in the circuit shown in the figure. Figure 15 shows external address signals A ₀ to A ₄ used in the circuit shown in Figure 11.
FIG. 3 is an address buffer circuit diagram for buffering up to. FIG. 16 is an address buffer circuit diagram for buffering external address signals A ₅ and A ₆ used in the circuit shown in FIG. 11.
FIG. 17 is an address buffer circuit diagram for buffering external address signals _A7 to _A11 used in the circuit shown in FIG. 11. 1st
FIG. 8 is a timing pulse generation circuit diagram used in the circuit shown in FIG. 11. FIG. 19 is a timing generation circuit diagram similarly used in the circuit shown in FIG. 11. FIG. 20 is a timing chart of a read cycle. FIG. 21 is a timing chart of a write cycle. FIG. 22 is a timing chart when reading and writing are performed in one cycle. Figure 23 is
1 is a cross-sectional view of a CMIS type semiconductor memory device.
FIGS. 24A to 24J are cross-sectional views showing the manufacturing method for obtaining the semiconductor device shown in FIG. 23 in the order of steps. DESCRIPTION OF SYMBOLS 1...Diffusion layer, 2...Low resistance polycrystalline silicon layer, 3...High resistance polycrystalline silicon layer, 9...Semiconductor substrate, _Q1 , _Q2 ...Drive FET, _Q3 , _Q4 ... Transmission FET, R ₁ , R ₂ ...Load resistance.

Claims (1)

[Scope of Claims] 1. An integrated circuit memory device in which a large number of memory cells are arranged in a matrix, comprising: (a) a first power wiring layer extending substantially linearly; and (b) the first (c) first and second memory cells provided on both sides of the power supply wiring layer; (d) a first power supply wiring layer provided on both sides of the second power supply wiring layer and substantially parallel thereto for transmitting complementary signals;
(e) first and second switch means each having one end connected to the first and second data lines and the other end connected to the first memory cell, respectively; (f) One end is connected to the first and second data lines, and the other end is connected to the second memory line, respectively.
third and fourth switch means connected to the cell; and (g) connected to or integrated with the control terminals of the first and second switch means, and provided substantially parallel to the first power supply wiring layer. (h) a second word line connected to or integrated with the control terminals of the third and fourth switch means and provided substantially parallel to the first power supply wiring layer; An integrated circuit memory device comprising: 2. The integrated circuit memory device according to claim 1, wherein at least a portion of the peripheral circuitry corresponding to the large number of memory cells has a complementary MISFET configuration. 3. The integrated circuit memory device according to claim 1 or 2, wherein the second power wiring layer and the first and second data lines include metal members. 4. The integrated circuit memory device according to any one of claims 1 to 3, wherein the first power wiring layer is made of a member containing polycrystalline Si. 5. The integrated circuit memory device according to claim 1, wherein the first and second word lines are made of a member containing polycrystalline Si.