JPH0338598B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization signal generation device, and more particularly to a device for generating a synchronization signal for displaying an image on a raster scan display device.

In general, raster scan display devices display images based on a supplied video signal, and this video signal is used to synchronize the raster in addition to image data for displaying the image. horizontal and vertical synchronization signals.

These horizontal and vertical synchronization signals are
It is regularly inserted into the video signal at a certain period, and this period is uniquely determined by the hardware of the display device.

Therefore, if the hardware configuration of a raster scan type display device is determined, the periods of the horizontal synchronization signal and the vertical synchronization signal will be determined accordingly.

A conventional synchronization signal generation device includes a dot clock oscillation circuit that generates a dot clock, a character clock frequency divider circuit that divides the frequency of the dot clock and outputs a synchronization signal reference clock, and divides the frequency of the synchronization signal reference clock to generate a horizontal A horizontal synchronization signal generation circuit outputs a synchronization signal, a vertical synchronization signal generation circuit divides the frequency of the horizontal synchronization signal and outputs a vertical synchronization signal, and synthesizes the horizontal synchronization signal and the vertical synchronization signal to perform composite synchronization. and a composite synchronization signal generation circuit that generates a signal.

Next, regarding an example of a conventional synchronization signal generator,
This will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of a conventional synchronizing signal generator.

A dot clock generating circuit 1 oscillates and outputs a dot clock a for shifting out image data. The dot clock a is input to a character clock frequency divider circuit 2, and is frequency-divided to become a synchronizing signal reference clock b. The synchronizing signal reference clock b is frequency-divided within the horizontal synchronizing signal generating circuit 3 to become the horizontal synchronizing signal c. The horizontal synchronizing signal c is frequency-divided within the vertical synchronizing signal generating circuit 4 to become the vertical synchronizing signal d. Composite synchronization signal synthesis circuit 5 synthesizes horizontal synchronization signal c and vertical synchronization signal d to generate composite synchronization signal e.

Next, an example of the operation of the conventional example shown in FIG.
This will be explained in detail with reference to the timing chart shown in the figure.

Assume now that the raster scan type display device connected to the synchronization signal generator shown in FIG. 1 has a horizontal synchronization frequency of 13.73 kHz and a vertical synchronization frequency of 57.2 Hz. It is also assumed that this display device has an interface specification that displays 40 characters in the horizontal direction and 200 characters in the vertical direction.

If designed in this way, the frequency division ratio of the vertical synchronization signal generation circuit 4 is the ratio of the horizontal synchronization frequency to the vertical synchronization frequency, so 1/240 (= 13.73kHz ÷ 57.2Hz)
Therefore, the vertical flyback section will be 40 rasters (= 240 rasters and 200 rasters).

Furthermore, if the synchronization signal reference frequency, which is the frequency of the synchronization signal reference clock b output from the character clock frequency dividing circuit 2, is 714kHz, the frequency division ratio of the horizontal synchronization signal generation circuit 3 is equal to the synchronization signal reference frequency and the horizontal synchronization signal. Since it is the ratio of frequencies, it is 1/52 (=714kHz
÷13.7kHz), and the horizontal blanking interval is 12 characters (=52 characters - 40 characters).

If each character displayed on the display device is represented by 8 rasters x 8 dots, then the frequency of the dot clock output from the dot clock oscillation circuit 1 is 5712 kHz (=714 kHz x 8 dots).
dot), character clock frequency divider circuit 2
The frequency division ratio of the frequency dividing circuit 2 is 1/8.

Therefore, as shown in FIG. 2, the synchronizing signal reference clock b output from the character clock frequency dividing circuit 2 is equal to
D40 40 clock and return clock B1-B12
It is composed of 52 clocks consisting of 12 clocks and
The horizontal retrace signal g is generated for the next 12 clocks after counting the synchronization signal reference clock h for 40 clocks.
Further, the horizontal synchronizing signal c is generated every 52 clocks.

Although not shown in FIG. 2, the vertical synchronizing signal d is generated every time 240 pulses of the horizontal synchronizing signal c are counted.

However, in such a synchronization signal generator, the synchronization frequency of the horizontal synchronization signal and the synchronization frequency of the vertical synchronization signal depend on the oscillation frequency of the dot clock, the frequency division ratio of the character clock frequency divider circuit, and the frequency division ratio of the horizontal synchronization signal generation circuit. Since the frequency division ratio of the vertical synchronization signal generation circuit and the vertical synchronization signal generation circuit are fixedly determined, the synchronization frequency cannot be changed, and therefore display devices having different synchronization frequencies cannot be connected.

An object of the present invention is to provide a synchronization signal generator to which display devices having different synchronization frequencies can be connected.

That is, an object of the present invention is to improve the above-mentioned drawbacks, and to improve the oscillation frequency of the dot clock, the frequency division ratio of the character clock frequency divider circuit, the frequency division ratio of the horizontal synchronization signal generation circuit, and the frequency division ratio of the vertical synchronization signal generation circuit. It is an object of the present invention to provide a synchronization signal generator capable of connecting display devices having different synchronization frequencies by changing the synchronization frequency without changing the ratio.

The synchronization signal generator of the present invention includes a dot clock oscillator circuit that generates a dot clock, a character clock frequency divider circuit that divides the frequency of the dot clock and outputs a synchronization signal reference clock, and a a clock number conversion circuit for outputting a predetermined number of reference clocks by stopping, multiplying, or frequency-dividing the synchronization signal reference clock; a horizontal synchronization signal generation circuit that outputs the horizontal synchronization signal, a vertical synchronization signal generation circuit that divides the frequency of the horizontal synchronization signal and outputs the vertical synchronization signal, and synthesizes the horizontal synchronization signal and the vertical synchronization signal to generate a composite synchronization signal. and a composite synchronization signal generation circuit that generates the synchronization signal.

That is, the synchronization signal generation device of the present invention is a synchronization signal generation device for generating a synchronization signal constituting a video signal for displaying an image on a raster scan display device, and a reference clock for generating the synchronization signal. The reference clock is configured to include at least one of means for stopping the reference clock, means for dividing the frequency of the reference clock, and means for multiplying the reference clock.

That is, the synchronization signal generating device of the present invention is characterized by having at least one of means for periodically stopping the synchronization signal reference clock, means for periodically dividing the frequency, and means for periodically multiplying the frequency of the synchronization signal reference clock. configured.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention.

A dot clock oscillation circuit 1 oscillates and outputs a dot clock a for shifting out image data. The dot clock a is input to a character clock frequency divider circuit 2 and frequency-divided to become a synchronization signal reference clock b. As for the synchronizing signal reference clock b, the clock number conversion circuit 6 processes the supplied synchronizing signal reference clock b and outputs a reference clock b'. That is, the synchronizing signal reference clock b is transmitted through the reference clock stop circuit 11 and the reference clock frequency divider circuit 1.
2 and the reference clock multiplier circuit 13.

On the other hand, the timing control circuit 10 inputs the horizontal synchronization signal c and the vertical synchronization signal d, and receives the stop control signal
f ₁ , a frequency division control signal f ₂ and a multiplication control signal f ₃ are generated and supplied to a reference clock stop circuit 11, a reference clock frequency division circuit 12, and a reference clock multiplication circuit 13, respectively.

Timing control circuit 10 also generates multiplexer control signal _f4 and supplies it to clock multiplexer 14 for control.

That is, the reference clock stop circuit 11 outputs the supplied synchronizing signal reference clock b as it is during the period when the stop control signal _f1 is not supplied, and suppresses it during the period when it is supplied and outputs the partially stopped clock _b1 . . Further, the reference clock frequency divider circuit 12 outputs the synchronization signal reference clock b as is during the period when the frequency division control signal _f2 is not supplied, but the frequency division control signal
When _f2 is supplied, a predetermined frequency division is performed and a divided clock _b2 is output. Furthermore, the reference clock multiplier circuit 13 outputs the synchronizing signal reference clock b as is while the multiplier control signal _f3 is not supplied, and when the multiplier control signal _f3 is supplied, it performs a predetermined multiplier. Outputs the double clock _b3 .

The clock multiplexer 14 uses the partially stopped clock b ₁ and the divided clock created in this way.
b ₂ , multiplier clock b ₃ and synchronization signal reference clock b to multiplexer control signal f ₄
The selected clock is selected according to the reference clock b' and outputted as the reference clock b'.

The horizontal synchronizing signal generating circuit 3 divides the frequency of the reference clock b' to generate a horizontal synchronizing signal c'. Also,
The vertical synchronizing signal generating circuit 4 divides the frequency of the horizontal synchronizing signal e' to generate a vertical synchronizing signal d'.

When the stop control signal f ₁ , the frequency division control signal f ₂ , and the multiplication control signal f ₃ are inactive, the synchronization signal reference clock b and the reference clock b' have the same frequency, and the output synchronization signal has There is no change.

Here, if an image is to be displayed on a display device that has a synchronous frequency different from the synchronous frequency obtained by the unique frequency division ratio of the horizontal synchronous signal generation circuit 3 and the vertical synchronous signal generation circuit 4, the synchronous frequency must be Must be changed.

The synchronizing signal generating device of the present invention is realized by changing the frequency of the reference clock b' supplied to the horizontal synchronizing signal generating circuit 3 at a constant repetition period as a means for changing the synchronizing frequency.

The video signal is composed of a display section, a horizontal blanking section, and a vertical blanking section. Of these, the frequency of the reference clock b' is not changed in the display section. As a result, the synchronizing signal reference clock b in the sum of one horizontal display section and one horizontal blanking section and the sum of one vertical display section and one vertical blanking section
There will be a difference in the number of clocks between and b'. Therefore, when changing the vertical synchronization frequency, the frequency of the reference clock b', that is, the number of clocks, is changed by changing the frequency of the reference clock b', that is, the number of clocks, in all vertical blanking intervals to the difference (in this case, directly the difference in the number of pulses of the horizontal synchronization signal). By making a correction change for that period, the horizontal synchronization frequency changes by that section, thereby making it possible to change the vertical synchronization frequency. In this case, constant frequency changes must be made in each vertical blanking interval. As a result, a synchronization signal is obtained in which there is no change in the horizontal synchronization frequency outside the vertical retrace interval, and only the vertical synchronization frequency is changed.

On the other hand, when changing the horizontal synchronization frequency, it can be realized by correcting and changing the frequency of the reference clock b', that is, the difference (in this case, the difference between b and b') of the reference clock b' in all horizontal blanking intervals.

However, in this case, since the vertical synchronization frequency also changes at the same time, in order to control this, it is sufficient to control the frequency of the reference clock b' also during the vertical retrace interval as described above. To change the reference clock b′,
When lowering the frequency, the stop control signal _f1 is active for a certain period of time to stop the synchronizing signal reference clock b, and the frequency division control signal _f2 is active for a certain period of time to stop the synchronizing signal reference clock b. This is realized by at least one of means for dividing the frequency of the synchronizing signal reference clock b by making the frequency control signal _f2 active for a certain period of time.

Also, if you want to increase the frequency, double the control signal.
This is achieved by means of _f3 being active for a certain period of time and multiplying the synchronizing signal reference clock b.

Note that the clock multiplexer 14 is controlled by the multiplexer control signal _f4 , and the output of the reference clock stop circuit ₁₁ is used during the period when the stop control signal f1 is active, and the output from the reference clock stop circuit 11 is used as the reference clock during the period when the frequency division control signal _f2 is active. The output of the clock frequency divider circuit 12 is
During the period when the multiplication control signal _f3 is active, the output of the reference clock multiplication circuit ₁₃ is selected, and during the period when the three control signals f1 to _f3 are inactive, the synchronization signal reference clock b is selected.

Next, an example of the operation of the embodiment shown in FIG.
This will be explained in detail with reference to the timing chart shown in the figure.

In the following explanation, each circuit shown in FIG. 3 other than the clock number conversion circuit 6 will be explained as having the same structure as the circuit described in FIG. 1 and denoted by the same reference numeral.

That is, the dot clock oscillation circuit 1 generates a dot clock a having a frequency of 5712 kHz. The character clock frequency divider circuit 2 has a frequency division ratio of 1/8 and generates a synchronizing signal reference clock b having a synchronizing signal reference frequency of 714 kHz in response to the input of the dot clock a.

In addition, the horizontal synchronization signal generation circuit 3 has a frequency division ratio of 1/52.
The horizontal synchronizing signal e' is output every 52 clocks of the reference clock b'.

Furthermore, the vertical synchronizing signal generating circuit 4 has a frequency division ratio of 1/240, and outputs the vertical synchronizing signal d' every time 240 pulses of the horizontal synchronizing signal c' are supplied. Composite synchronization signal generation circuit 5 synthesizes horizontal synchronization signal c' and vertical synchronization signal d' and outputs composite synchronization signal e'.

The synchronizing signal reference clock b output from the character clock frequency dividing circuit 2 has a synchronizing signal reference frequency.
Since it is 714kHz, it is a pulse that occurs every 1.4μsec (=1/714kHz), and this synchronization signal reference clock b
The image data of one character is read out every time the character is given. Further, the number of clocks is not converted in the horizontal display section and the vertical display section, but if conversion of the number of clocks is necessary, the number of clocks is converted in the horizontal retrace section and the vertical retrace section.

Therefore, in order to read out 40 characters in the horizontal display section, the horizontal display section is 56.0 μsec (=
1.4 μsec x 40 characters).

The horizontal synchronization frequency of the display device connected here is 13.73kHz, which is the same as the explanation in the conventional example shown in Figure 1.
Then, the horizontal synchronization signal c′ is 72.8 μsec (=1/
13.73kHz). Therefore, the horizontal blanking interval is 16.8μsec (=72.8μsec−56.0μsec)
becomes. Therefore, within this horizontal retrace interval, the synchronizing signal reference clock b has 12 pulses (=16.8 μsec/
1.4 μsec), but since this matches the specification for reading out 12 characters in the horizontal retrace interval, there is no need to convert the number of clocks in the horizontal retrace interval.

Further, if the vertical synchronization frequency of this display device is 57.2 Hz, which is the same as explained in the conventional example shown in FIG. 1, the vertical synchronization signal d' needs to be generated every 17.47 msec (=1/57.2 Hz). Here, the vertical display section does not convert the clock number, so it is 14.56 msec (=
72.8 μsec x 200 rasters). Therefore, the vertical retrace interval is 2.91ms (=17.47msec−14.56ms), so the horizontal synchronization signal c' is within this vertical retrace interval.
40 pulses (=2.91ms/72.8μs) need to be supplied, but since this matches the specification of outputting 40 rasters during the vertical retrace interval, the number of clocks must be converted within the vertical retrace interval. is also unnecessary.

Therefore, if the display device has the same horizontal synchronization frequency and vertical synchronization frequency as explained in the conventional example shown in FIG.
Since there is no need to convert the number of clocks, the clock multiplexer 14 uses the synchronization signal reference clock b.
The multiplexer control signal _f4 may be applied so that the reference clock b' is output as is as the reference clock b'.

Next, in the embodiment shown in Fig. 3, as a display device, the horizontal synchronization frequency is 12.75kHz, and the vertical synchronization frequency is 53.1Hz.
This section explains how to connect the following items. Since the horizontal sync frequency is 12.75kHz, the horizontal sync signal
c′ needs to occur every 78.4 μsec (=1/12.75 kHz). Therefore, the horizontal retrace interval is 22.4μsec
(=78.4μsec−56.0μsec), and within this horizontal retrace interval, the synchronization signal reference clock b is 16 pulses (=
22.4 μsec/1.4 μsec), it is sufficient to convert the clock number and output 12 pulses as the reference clock b'.

That is, as shown in FIG. 4, for the display clocks D1 _to D40 as the synchronizing signal reference clock b, the display clocks _D1 ' to _D40 are used as the reference clock b'.
It is sufficient to output D ₄₀ ′ and output retrace clocks B _{1 ′} to _{B 12} ′ for retrace clocks B ₁ to B ₁₆ .

Therefore, in the example shown in FIG.
At the timing when B ₃ and B ₄ are given, the timing control circuit 10 outputs the stop control signal f ₁ to suppress the two clock pulses, and the retrace clock B ₁₀ to
By outputting the frequency division control signal _f2 at the timing when _B13 is applied, the number of clocks is reduced to two outputs for four inputs, reducing the total number of clocks by four. In addition, the clock multiplexer 14
is the partial stop clock b ₁ from the reference clock stop circuit 11 when the stop control signal f ₁ is applied.
The multiplexer control signal selects the frequency divided clock _b2 from the reference clock frequency divider circuit 12 when the frequency division control signal _f2 is applied, and selects the synchronization signal reference clock b at other times. f ₄ is given.

As a result, the reference clock b' is output as shown in FIG. 4, and the horizontal retrace signal g' is output as the retrace clock B ₁
.about.B ₁₆ is being applied, and its output is during the period during which the retrace clocks B ₁ ' to B ₁₂ ' are being applied. In this example, the horizontal synchronizing signal c appears in the interval between retrace clocks _B6 ' and _B8 '.

As a result, 12 pulses are given in the horizontal blanking interval, but the time is 22.4 μsec. Next, since the vertical synchronization frequency is 53.1Hz, the vertical synchronization signal d′ is
It needs to occur every 18.82msec (=1/53.1Hz). Here, the vertical display interval is 15.65msec (=
78.4 μsec x 200 rasters), the vertical retrace interval is 3.14 msec (= 18.82 msec - 15.68 msec) and the vertical synchronization signal d' is 40 rasters (= 3.14 msec/
78.4 μsec), but since this matches the specification for outputting 40 rasters as described above, there is no need to convert the number of clocks in the vertical retrace interval.

Note that if the vertical synchronizing signal d' needs to be supplied for one more raster, that is, 41 rasters, it is supplied for 78.4 μsec. Since it is sufficient to suppress the synchronizing signal reference clock b within the vertical retrace interval, it is sufficient to suppress 52 pulses. Conversely, if it is necessary to supply one less raster, it is sufficient to increase the number by 52 pulses, and in this case, the reference clock multiplier circuit 13 may be operated to generate the multiplier clock _b3 .

By doing this, even if the synchronization frequency of the display device changes, sufficient operation can be achieved by varying the period without changing the pulses within the section.

As described above, the synchronization signal generator of the embodiment shown in FIG. 3 can generate a synchronization signal with a synchronization frequency different from the unique synchronization frequency.
It becomes possible to generate a synchronization signal that allows images to be displayed even on display devices with different synchronization frequencies. Note that the timing control circuit in the embodiments described above may be configured using, for example, a microcomputer.

The synchronization signal generation device of the present invention can change the synchronization frequency without changing the frequency division ratio of the horizontal synchronization signal generation circuit and the vertical synchronization signal generation circuit by adding a clock number conversion circuit. This has the advantage that raster scan type display devices having different synchronization frequencies can be connected.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional synchronizing signal generator, FIG. 2 is a time chart for explaining an example of the operation of the conventional example shown in FIG. 1, and FIG. 3 is an embodiment of the present invention. FIG. 4 is a time chart for explaining an example of the operation of the embodiment shown in FIG. 1...Dot clock oscillation circuit, 2...Character clock frequency dividing circuit, 3...Horizontal synchronization signal generation circuit, 4...Vertical synchronization signal generation circuit, 5...Composite synchronization signal synthesis circuit, 6...Clock number conversion circuit,
10...Timing control circuit, 11...Reference clock stop circuit, 12...Reference clock frequency dividing circuit,
13... Reference clock multiplier circuit, 14... Clock multiplexer, a... Dot clock, b
... Synchronization signal reference clock, b' ... Reference clock, c, c' ... Horizontal synchronization signal, d, d' ... Vertical synchronization signal, e, e' ... Composite synchronization signal, b ₁ ... Part Stop clock, _{b 2} ...Divided clock, b ₃ ...Double clock, f1...Stop control signal, _f2 ...Divide control signal, _f3 ...Divide control signal, _f4 ...Multiplexer Control signals, _D1 to _D40 , _D1 ' to _D40 '...display clock, _B1 to _B16 , _B1 ' to _B16 '...return clock.

Claims (1)

[Scope of Claims] 1. A dot clock oscillation circuit that generates a dot clock for displaying dots on a raster, a character clock frequency divider circuit that divides the frequency of the dot clock and outputs a synchronization signal reference clock, and this synchronization signal. a horizontal synchronization signal generation circuit that generates a horizontal synchronization signal by appropriately frequency-dividing a reference clock; a vertical synchronization signal generation circuit that generates a vertical synchronization signal by further appropriately frequency-dividing this horizontal synchronization signal; and the horizontal synchronization signal. In a raster scan type CRT display device equipped with a composite synchronization signal generation circuit that generates a composite synchronization signal by synthesizing a signal and a vertical synchronization signal, a synchronization signal reference clock output from the character clock frequency dividing circuit is provided. and changing the number of the synchronization signal reference clocks supplied to the horizontal synchronization signal generation circuit only during the horizontal retrace period and/or the vertical retrace period in the display device;
A synchronization signal generating device comprising a clock number conversion circuit that supplies only a synchronization signal reference clock having a predetermined cycle during a horizontal display period and/or a vertical display period in the display device.