JPH0340559B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a control method for a time division multiplex network. Conventionally, in a time division multiplex network such as a time division switch, in order to easily interconnect a large number of subscribers with a small number of time division communication channels, it is necessary to set multiple channels in advance, in other words, time slots. Pulse trains of corresponding phases are prepared, and the addresses of the sender and receiver are stored in a circular storage device in order to allocate channels to the sender and receiver, respectively. Furthermore, when setting the channel, the encoding rate (sampling frequency) is specified so that a certain demodulation quality (speech quality) can be obtained. That is, as shown in FIG. 1, n sampling pulse trains are set for each of the n channels set in advance, and the PAM modulation/demodulation circuits of each sender and receiver are assigned the assigned channels. The corresponding sampling pulses were sent, and PAM modulation and demodulation was performed respectively. However, in a system requiring a large number of time division multiplexed communication channels, the sampling frequency must be increased in order to obtain constant demodulation quality. In this case, time-division multiplexing becomes more sensitive to inductive and capacitive loads on the multiplex due to the higher sampling frequency, which delays the signal waveform on the multiplex and synchronizes the transmitter and receiver. Since the signal is reproduced by taking the same time slot and giving it the same time slot, there is a problem in that if the signal of other channels leaks and the signal waveform is significantly delayed, crosstalk occurs. The present invention has been made in order to solve these conventional difficulties, and the storage device is divided into two parts, and the address data of the receiving side and the address data of the sending side are sequentially stored in the storage devices of different divisions. The address data on the receiving side and the address data on the transmitting side are sequentially reproduced for each section at predetermined times, and the transmitting side and receiving side modulate and demodulate the address corresponding to the reproduced address data. When sending the address data as a sampling pulse to the circuit in accordance with the time when the address data is reproduced, a signal delay in the path from the transmitting side modulation/demodulation circuit to the receiving side modulation/demodulation circuit via a time division multiplex path is accommodated. A control method for a time division multiplexing network is provided in which a receiving side sampling pulse sent to the receiving side modulation/demodulation circuit is delayed by a delay time from a sending side sampling pulse sent to the transmission side modulation/demodulation circuit. That is. DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a time division multiplex network control method according to the present invention will be described below with reference to the drawings. In FIG. 2, storage devices RAM-T and
RAM-R consists of a readable and writable IC memory, RAM-T stores address data on the transmitting side, and RAM-R stores address data on the receiving side. The clock pulse counter CK.COUNT is a register that counts clock pulses, and each time it counts, it specifies the address to be read to RAM-T and RAM-R using a BCD code.
When the data read from RAM-R and output from latch LATCH is reset, it is reset and the count is repeated again. Clock CKG is clock counter CK.
Provides clock pulses to COUNT and generates time slots with different phases to create a delay circuit.
Provides output data of DELAY and RAM-T. Tri-state buffers TSB-1 and TSB-2 that do not interfere with each other are RAM-T and RAM-
When writing address data to R, write address
It has a function to replace Da with the read address by counter CK.COUNT. Decoders TO DEC and RO DEC decode the output data of RAM-T and latch LATCH, respectively, and provide sampling pulses for transmission and reception, respectively, to the time division multiplexed bus BUS by PAM. The delay circuit DELAY is composed of capacitors, resistors, buffers, etc., and is used as a PAM modulation/demodulation circuit on the transmitting side (MDM ₁ to MDM _o on the transmitting side in Figure 2).
PAM on the receiving side via time division multiplex BUS from
Modulation/demodulation circuit (receiving side in Figure 2)
A delay time is generated in the clock CKG corresponding to the signal delay Δt on the path leading to MDM ₁ to MDM _o ),
Give the latch LATCH its delayed time slot. These time division multiplex BUS, PAM modulation/demodulation circuits MDM ₁ to _{MDM o} , control circuits, etc. are mounted on the same circuit board or on adjacent boards. The delay Δt of the signal on the path via the time division multiplex BUS corresponds to the delay time of the receiving side sampling pulse sent to the receiving side PAM modulation/demodulation circuit on this board. The latch LATCH temporarily suspends the data read from RAM-R, and executes RO DEC at the timing of the time slot generated by the delay circuit DELAY.
Give address data to . The control unit CONTROL receives a signal requesting external writing or rewriting of RAM-T and RAM-R, that is, a TS specifying RAM-T,
RS specifying RAM-R, requesting writing
RAM-T, RAM-R,
It has the function of controlling TSB-1 and TSB-2 each time and resetting the clock counter CK.COUNT at the same time. That is, the control unit CONTROL opens TSB-1 unless a signal is given to SR or TS, and closes TSB-1.
2, and set RAM-T and RAM-R to read mode. Also, when a signal is given to RS or TS, buffer TSB-1 is closed and TSB-2 is opened, and when a write signal is given to MW, when a signal is given to RS, buffer TSB-1 is closed and TSB-2 is opened. RAM−
R, when a signal is given to TS
Each RAM-T is switched to write mode and the address data given by Ad is written into the address designated by Da at that time. In addition,
While a signal is given to TS or RS, the counter
Reset CK.COUNT. Multiple subscribers each have their own PAM modem circuit
MDM ₁ …a small number of time division multiplexed paths via MDM _o
Connected via BUS. The PAM modulation/demodulation circuits MDM ₁ ...MDM _o send and receive PAM pulse signals to the multipath BUS by the outputs of the decoders TO DEC and RO DEC, respectively. Next, in the above device, from MDM ₁ (address A) to MDM ₂ (address B), MDM ₂ (address B)
From MDM ₁ (Address A) to MDM ₃ (Address C)
To MDM ₄ (D address), from MDM ₄ (D address)
To MDM ₃ (address C), from MDM ₅ (address E)
The operation when sending each signal to MDM ₆ (address F) will be explained. In this case, first, A is placed at address 0 of RAM-T.
B is written to address 0 of RAM-R, and then
B is written to address 1 of RAM-T and A is written to address 1 of RAM-R, respectively as shown below.
The addresses of the subscribers corresponding to RAM-T and RAM-R are written, and finally
Reset data (for example, 4
For bits, 1111 is written.

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Claims (1)

[Claims] 1 The storage device is divided into two, and the address data on the receiving side and the address data on the sending side are sequentially stored in the storage devices of different sections, and the address data on the receiving side and the address data on the sending side are is sequentially reproduced for each of the above sections at predetermined times, and is sent as a sampling pulse to the transmitting side and receiving side modulation/demodulation circuit of the address corresponding to the reproduced address data in accordance with the time when the address data is reproduced. When transmitting, the delay time corresponds to the delay of the signal in the path from the transmitting modem circuit to the receiving modem circuit via time division multiplexing,
A control method for a time division multiplex network, characterized in that a receiving side sampling pulse sent to the receiving side modulation/demodulation circuit is delayed from a sending side sampling pulse sent to the transmitting side modulation/demodulation circuit.