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JPH0341978B2 - - Google Patents
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JPH0341978B2 - - Google Patents

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Publication number
JPH0341978B2
JPH0341978B2 JP56191267A JP19126781A JPH0341978B2 JP H0341978 B2 JPH0341978 B2 JP H0341978B2 JP 56191267 A JP56191267 A JP 56191267A JP 19126781 A JP19126781 A JP 19126781A JP H0341978 B2 JPH0341978 B2 JP H0341978B2
Authority
JP
Japan
Prior art keywords
reactor
semiconductor layer
substrate
plasma
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56191267A
Other languages
Japanese (ja)
Other versions
JPS5892217A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP56191267A priority Critical patent/JPS5892217A/en
Publication of JPS5892217A publication Critical patent/JPS5892217A/en
Publication of JPH0341978B2 publication Critical patent/JPH0341978B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3402Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411Silicon, silicon germanium or germanium
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/505Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
    • C23C16/509Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Photovoltaic Devices (AREA)

Description

【発明の詳細な説明】 本発明はプラズマ気相法により、再現法、特性
のよい半導体装置を作製する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reproduction method and a method for manufacturing a semiconductor device with good characteristics by a plasma vapor phase method.

本発明はプラズマ気相法により反応炉内に設け
られた基板上にP型およびN型の半導体層を有す
る第1の半導体装置を形成した後、この半導体装
置のNまたはP型不純物が次に作られるPまたは
N型の半導体層中に反応装置の内壁または基板の
ホルダーより再放出され、これが1015〜1018cm-3
の濃度で混入されてしまうことを防止するため、
この各工程の間に前回作られた半導体層上に真性
または実質的に真性(以下I層という)のコーテ
イング用の被膜を形成する工程(この場合は次の
工程の最初に作られる被膜をコーテイングしても
よい)により実質的に過去の履歴を除去してしま
うことを目的としている。
In the present invention, after a first semiconductor device having P-type and N-type semiconductor layers is formed on a substrate provided in a reactor by a plasma vapor phase method, N or P-type impurities of this semiconductor device are It is re-emitted from the inner wall of the reactor or the holder of the substrate into the P- or N-type semiconductor layer produced, and this is 10 15 to 10 18 cm -3
In order to prevent it from being mixed in at a concentration of
During each of these steps, a step of forming an intrinsic or substantially intrinsic (hereinafter referred to as I layer) coating film on the previously formed semiconductor layer (in this case, coating the film formed at the beginning of the next step) The purpose of this is to substantially eliminate past history.

さらにまたは前回作られた半導体層のうち、反
応装置の内壁、基板のホルダー等の表面に付着し
たものをCF4等の反応性気体をプラズマ化するこ
とにより除去してしまう工程を設けることを目的
とする。
In addition, the purpose is to provide a process to remove any previously produced semiconductor layers that have adhered to the inner walls of the reactor, the surfaces of the substrate holders, etc. by converting reactive gases such as CF 4 into plasma. shall be.

かくすることにより再現性よくRUN−TO−
RUNの特性バラツキを少くするとともに、その
得られた特性もきわめてすぐれたものとすること
ができるという特徴を有する。
By doing this, RUN−TO− can be performed with good reproducibility.
It has the characteristics that it can reduce the variation in RUN characteristics and also make the obtained characteristics extremely excellent.

また本発明は反応炉内に設けられた基板上に少
くともひとつの接合特にPIN、PI、NIまたはPN
接合を有する半導体装置において、反応炉の内壁
特にプラズマ原子または反応性気体が衝突する内
壁より不純物特に酸素、アルカリ金属原子が放出
されることを防ぐため、これらの表面にあらかじ
め真性または実質的に真性の半導体層例えば非単
結晶珪素を形成することを目的としている。
The present invention also provides at least one bond, particularly PIN, PI, NI or PN, on the substrate provided in the reactor.
In semiconductor devices with junctions, in order to prevent impurities, particularly oxygen and alkali metal atoms, from being released from the inner wall of the reactor, particularly the inner wall with which plasma atoms or reactive gases collide, these surfaces are coated with intrinsic or substantially intrinsic The purpose is to form a semiconductor layer of, for example, non-single crystal silicon.

本発明はこれらの実質的に除去するためのコー
テイングにより再放出を防ぐため、半導体層を半
導体装置の作製に必要な電磁エネルギの出力Po
例えば5〜100W、温度Ta例えば200〜320℃に対
し、Po−10W(但し最低5Wとする)〜Po+30W
の範囲、またTo−50℃〜To+50℃特に好ましく
はPo、Toと同じまたは概略同じ条件にて作製
し、0.2〜1μの厚さに形成せしめることを特徴と
している。
In order to prevent re-emission by coating to substantially remove these, the present invention provides a semiconductor layer with an output Po of electromagnetic energy necessary for fabricating a semiconductor device.
For example, 5 to 100W, for a temperature Ta of 200 to 320℃, Po-10W (minimum 5W) to Po+30W
It is characterized in that it is produced under the same or approximately the same conditions as Po and To, and preferably in the range of To-50°C to To+50°C, and is formed to have a thickness of 0.2 to 1 μm.

従来プラズマCVD法に関しては、ひとつの反
応炉にてPIN接合等を有する半導体装置の作製が
行なわれていた。しかしこの接合をくりかえし行
なうと、全くわけのわからない劣化、バラツキに
悩まされてしまい、半導体装置としての信頼性に
不適当なものしかできなかつた。
Conventionally, in the plasma CVD method, a semiconductor device having a PIN junction, etc. has been manufactured in a single reactor. However, when this bonding is repeated, it suffers from completely incomprehensible deterioration and variation, resulting in a structure that is unsuitable for reliability as a semiconductor device.

この原因を調べた結果、この最大の原因は、反
応炉内に付着している酸素、アルカリ金属が半導
体層中に混入して、電気伝導度の低下をもたらす
のであり、酸素にあつては−1PPMの混入であつ
ても、暗伝導度10-6(Ωcm)-1を10-8(Ωcm)-1と1/
100にまで下げてしまつていた。
As a result of investigating the cause, we found that the biggest cause of this is that oxygen and alkali metals adhering in the reactor mix into the semiconductor layer, causing a decrease in electrical conductivity. Even if 1PPM is mixed, the dark conductivity of 10 -6 (Ωcm) -1 becomes 10 -8 (Ωcm) -1 and 1/
I had lowered it to 100.

またアルカリ金属にあつても、5PPMの混入に
おいて、P型、I型の伝導度の低下または透明導
電膜の電導度の低下をもたらしてしまつた。
Also, when it comes to alkali metals, the incorporation of 5PPM results in a decrease in P-type and I-type conductivity or a decrease in the conductivity of the transparent conductive film.

これらの混入を防ぐため、反応炉の内壁また基
板のホルダー(ボートともいう)の特にプラズマ
による反応性気体にスパツタされる部分に対し
て、あらかじめ半導体層を0.2〜2μの厚さに形成
させ、コーテイングしてしまうことがきわめて重
要であつた、さらに再現性特性劣化に対しては、
ひとつの半導体装置の作製に対し、その最後の工
程がNまたはP型半導体層を作りまた次の最初の
工程にPまたはN型の半導体層を作ろうとした
時、1015〜1018cm-3の濃度に最初の不純物例えば
リンがP型半導体層中に混入してしまう。このた
めP型半導体層は例えば1018〜1021cm-3の濃度に
ホウ素を添加してP型層としてもその電気伝導度
はリンの混入により再結合中心が増加するためき
わめて特性が悪く、混入がない場合10-2〜10+6
(Ωcm)-1に対し、10-6〜10-4(Ωcm)-1と1/100〜
1/1000しか得られなかつた。
In order to prevent these contamination, a semiconductor layer is formed in advance to a thickness of 0.2 to 2μ on the inner wall of the reactor and on the parts of the substrate holder (also called boat) that will be sputtered by the reactive gas generated by the plasma. It was extremely important to coat the
When manufacturing one semiconductor device, when the last step is to create an N- or P-type semiconductor layer, and the next first step is to create a P- or N-type semiconductor layer, the An initial impurity such as phosphorus is mixed into the P-type semiconductor layer at a concentration of . For this reason, even if a P-type semiconductor layer is made by doping boron to a concentration of, for example, 10 18 to 10 21 cm -3 , its electrical conductivity is extremely poor because the number of recombination centers increases due to the incorporation of phosphorus. 10 -2 to 10 +6 when there is no contamination
(Ωcm) -1 vs. 10 -6 ~10 -4 (Ωcm) -1 and 1/100 ~
I could only get 1/1000.

このためPIN型光電変換装置においては2〜4
%の効率を各ランごとのバヲツキを±200%も有
して得られたにすぎず好ましくなかつた。
Therefore, in a PIN type photoelectric conversion device, 2 to 4
% efficiency with a fluctuation of ±200% for each run, which was not preferable.

しかし本発明方法にあつては、8〜10%の約3
〜5倍の高い変換効率を得ることができるように
なつた。
However, in the method of the present invention, about 3% of 8 to 10%
It has become possible to obtain a conversion efficiency ~5 times higher.

またこの不純物酸素ドーピングの効果を少くす
るため、本発明人の出願になる特許願 半導体装
置作製方法56−55608(原表示53−152887昭和53年
12月10日出願)が知られている。これは例えば
PIN半導体装置を作ろうとする時、各P層、I
層、N層をそれぞれ独立の反応炉を作り、基板を
その層間を移動せしめることにより行わんとする
ものである。この方法にあつては、本発明と同じ
対策を持つことができ、きわめて好ましい電気的
特性を得ることができる。しかしその場合、装置
はひとつの室の方式の3倍であり、製造コストが
2.5〜3倍も高価になつてしまう。さらに多量生
産向きでない等の欠点を有していた。
In addition, in order to reduce the effect of this impurity oxygen doping, a patent application filed by the present inventor: Semiconductor device manufacturing method 56-55608 (original designation 53-152887, 1978)
(filed on December 10) is known. This is for example
When trying to make a PIN semiconductor device, each P layer, I
This is done by creating independent reactors for each layer and N layer, and moving the substrate between the layers. This method can take the same measures as the present invention and can provide extremely favorable electrical characteristics. However, in that case, the equipment would be three times as large as the one-room method, and the manufacturing cost would be lower.
It ends up being 2.5 to 3 times more expensive. Furthermore, it had drawbacks such as not being suitable for mass production.

本発明はかかる反応炉において、特に横型の反
応炉において特に有効である。また多量に基板上
に半導体装置を作ろうとする時特に有効であり、
半導体装置ひとつあたりの装置の減価償却を含め
て、製造コストをたて型反応炉の1/100にできる
という大きな特徴を有している。
The present invention is particularly effective in such reactors, particularly in horizontal reactors. It is also particularly effective when trying to fabricate semiconductor devices on a large number of substrates.
A major feature is that the manufacturing cost, including the depreciation of each semiconductor device, can be reduced to 1/100 of that of a vertical reactor.

すなわち本発明はかかる多量生産用に横型に配
置された反応炉または反応筒(10〜30cmφ 、長さ
1〜5m)用いる方法を中心として記す。
That is, the present invention focuses on a method using a horizontally arranged reactor or reaction tube (10 to 30 cmφ, 1 to 5 m in length) for mass production.

かかる反応筒の外側に一対の反応性気体をプラ
ズマ化する電磁エネルギ供給用の電極と該電極の
外側にこの反応筒および電極を囲んで加熱装置と
を具備し、この反応炉内を炉方向に反応性気体を
流し、この気体の流れにそつて基板を配置せしめ
たものである。
A pair of electrodes for supplying electromagnetic energy for turning a reactive gas into plasma are provided on the outside of the reaction tube, and a heating device is provided outside of the electrodes to surround the reaction tube and the electrodes, and the inside of the reactor is heated in the direction of the furnace. A reactive gas is flowed and the substrate is placed along the flow of the gas.

さらにかかる装置内に一対の電極により発生す
る電磁界に垂直または平行に基板を配置し、これ
を複数段または複数列配置して2〜20cm□ の基板
例えば10cm□ の基板を20段20列計400まいの被形
成面上に一度に被膜特に珪素、炭素炭化珪素また
は珪化ゲルマニユーム、ゲルマニユーム被膜すな
わち4価の元素を中心とした半導体膜を形成せし
めることを中心として記す。
Further, in such a device, substrates are arranged perpendicularly or parallel to the electromagnetic field generated by a pair of electrodes, and these are arranged in multiple stages or in multiple rows to form a total of 20 stages or 20 rows of 2 to 20 cm square substrates, for example, 10 cm square substrates. The description will focus on forming a film, particularly a film of silicon, silicon carbide, germanium silicide, or germanium film, ie, a semiconductor film mainly made of tetravalent elements, on 400 surfaces to be formed at once.

本発明は炭素−珪素結合を有する水素化物また
はハロゲン化物(炭化珪化物気体)よりなる反応
性気体、シラン(SinH2o+2n1)の如き珪化
物気体またはアセチレン等の炭化水素を用いて被
成形面上に非単結晶の炭化珪素、珪素または炭素
を主成分とする被膜を0.05〜1torrの反応炉圧力
で100〜400℃の温度で形成せしめるプラズマ気相
法に関する。
The present invention utilizes a reactive gas consisting of a hydride or halide (carbide silicide gas) having a carbon-silicon bond, a silicide gas such as silane (SinH 2o+2 n1), or a hydrocarbon such as acetylene. This invention relates to a plasma vapor phase method for forming a film mainly composed of non-single crystal silicon carbide, silicon or carbon on a surface at a reactor pressure of 0.05 to 1 torr and a temperature of 100 to 400°C.

本発明はさらにかかる反応性気体に価の不純
物であるB、Al、Ga、Inを含む不純物気体例え
ばジボラン(B2H6)、V価の不純物を含む不純物
気体例えばフオスヒン(PH3)またはアルシン
(AsH3)漸次添加して被形成面を有する基板上
に密接してP型層、さらにI型層およびN型層を
PINの順序にて積層形成せしめ、これをくりかえ
し、安定して作製することを目的としている。さ
らに本発明はフラズマ化する電磁エネルギのパワ
ーにより、アモルフアス構造の半導体(ASとい
う)、5〜100Aの大きさの微結晶性を有するセミ
アモルフアス(半非晶質、以下SASという)ま
たは5〜200Aの大きさのマイクロポリクリスタ
ル(微多結晶、以下PCという)の構造を有する
半導体の如き非単結晶半導体膜を作製せんとする
ものである。さらに強い電磁エネルギを与える場
合、基板表面ではスパツターされた電気的に欠陥
だらけのアモルフアス構造になりやすい。かかる
欠陥構造をなくすため、基板は互いに10〜40mm代
表的には20〜25mm離間し、プラズマ反応に200〜
500Wという高いエネルギが必要な場合であつて
も、被形成面上にはこのスピーシスの実質的なプ
ラズマエネルギを得る距離を基板間の距離で制御
し、実質的に2〜20Wという弱いパワーで被膜化
せしめると同等の特性を有せしめたことを特徴と
する。
The present invention further provides an impurity gas containing valent impurities such as B, Al, Ga, and In, such as diborane (B 2 H 6 ), and an impurity gas containing V-valent impurities, such as phosphin (PH 3 ) or arsine. (AsH 3 ) is added gradually to form a P-type layer, then an I-type layer and an N-type layer closely on the substrate having the surface to be formed.
The purpose is to form layers in the order of PIN and repeat this process to achieve stable production. Furthermore, the present invention uses the power of electromagnetic energy to produce a plasma to produce semiconductors with an amorphous structure (hereinafter referred to as AS), semi-amorphous (semi-amorphous, hereinafter referred to as SAS) with microcrystallinity with a size of 5 to 100A, or The aim is to fabricate a non-single crystal semiconductor film such as a semiconductor having a micro-polycrystal (hereinafter referred to as PC) structure with a size of 200A. If stronger electromagnetic energy is applied, the substrate surface tends to form an amorphous structure full of sputtered electrical defects. To eliminate such defect structures, the substrates are spaced 10-40 mm apart from each other, typically 20-25 mm, and the plasma reaction
Even if a high energy of 500W is required, the distance to obtain the substantial plasma energy of this spies on the surface to be formed can be controlled by the distance between the substrates, and the film can be coated with a substantially weak power of 2 to 20W. It is characterized in that it has the same characteristics when it is made into a material.

このため本発明においては、その出発物質であ
る反応性気体に炭化珪素(SixC1-110<x<1)
を作ろうとした場合、炭素−珪素結合を有する材
料を用いた。すなわち炭素−珪素結合を有する水
素化物またはハロゲン化物例えばテトラメチルシ
ラン(Si(CH34)(単にTMSという)、テトラエ
チルシラン(Si(C2H54)、Si(CH3)xcl4-x(1
x3)Si(CH3)xH4-x(1x3)等の反応
性気体を用いて反応生成物中にSi−C結合を得や
すくしている。
Therefore, in the present invention, silicon carbide (SixC 1-11 0<x<1) is used as the reactive gas as the starting material.
When trying to make , a material with carbon-silicon bonds was used. That is, hydrides or halides having a carbon-silicon bond, such as tetramethylsilane (Si(CH 3 ) 4 ) (simply referred to as TMS), tetraethylsilane (Si(C 2 H 5 ) 4 ), Si(CH 3 )xcl 4 -x (1
x3) A reactive gas such as Si( CH3 ) xH4-x (1x3) is used to facilitate the formation of Si-C bonds in the reaction product.

また珪素を主成分とする被膜を得ようとする時
はSinH2o+2(n1)のシラン、SiF4またはこれ
らの混合気体を用いた。炭素を得ようとする時
は、アセチレン(C2H1)またはエチレン
(C2H4)を主として用いた。こうすることによ
り、珪素(Si)、炭化珪素(SixC1-x0<x<1)
または炭素(C)(これらを合わせるとSixC1-x(0
x1)と示すことができるため、以下炭化珪素
という時はSixC1-x(0x1)を意味するもの
とする)を作製する。
When attempting to obtain a film containing silicon as the main component, silane of SinH 2o+2 (n1), SiF 4 or a mixed gas thereof was used. When trying to obtain carbon, acetylene (C 2 H 1 ) or ethylene (C 2 H 4 ) was mainly used. By doing this, silicon (Si), silicon carbide (SixC 1-x 0<x<1)
or carbon (C) (combining these sixC 1-x (0
x1), hence the term silicon carbide hereinafter refers to SixC 1-x (0x1)).

さらにここに価または価の不純物を添加し
て被形成面よりP型、I型(真性またはオートド
ーピング等を含む人為的に不純物を添加しない実
質的に真性)さらにN型の半導体または半絶縁体
を作製した。
Furthermore, valent or valent impurities are added here to form P-type, I-type (intrinsic or substantially intrinsic without artificially adding impurities, including autodoping, etc.) and N-type semiconductors or semi-insulators from the surface to be formed. was created.

さらにかかる反応性気体を用いると、反応炉を
1気圧以下特に0.01〜10torr、代表的には0.3〜
0.6torrの圧力下にて50W以下の電磁エネルギに
おいても、例えば0.01〜100MHz特に500KHzまた
は13.56MHzにおいて被膜を形成することが可能
である。即ち低エネルギプラズマCVD装置とす
ることができた。
Furthermore, when such a reactive gas is used, the reactor can be heated to 1 atm or less, particularly 0.01 to 10 torr, typically 0.3 to 10 torr.
It is also possible to form a coating at 0.01 to 100 MHz, especially 500 KHz or 13.56 MHz, even at an electromagnetic energy of 50 W or less under a pressure of 0.6 torr. In other words, a low-energy plasma CVD device could be achieved.

さらに50〜500Wという高エネルギプラズマ雰
囲気とすると、形成された炭化珪素は微結晶化
し、その結果P型またはN型において、ホウ素ま
たはリンを0.1〜5%(ここでは(B2H6または
PH3)/(炭化物気体または炭化珪化物気体+珪
化物気体)の比をパーセントで示す)添加した場
合、低エネルギでは電気伝導度は10-9〜10-3(Ω
cm)-1であつたものが10-6〜10+2(Ωcm)-1と約千
倍にまで高めることができた。
Furthermore, if a high-energy plasma atmosphere of 50 to 500 W is applied, the formed silicon carbide becomes microcrystalline, and as a result, in the P type or N type, boron or phosphorus is added by 0.1 to 5% (here, (B 2 H 6 or
When the ratio of PH 3 )/(carbide gas or carbide silicide gas + silicide gas) is added, the electrical conductivity is between 10 -9 and 10 -3 (Ω) at low energies.
We were able to increase the temperature from 10 -6 to 10 +2 (Ωcm) -1 , which was about 1,000 times.

さらにこの高エネルギ法を用いて得られた炭化
珪素は5〜200Aの大きさの微結晶構造を有する
いわゆるSAS構造を有せしめることができた。
かかるSASにおいて、そのまたはN型の不純物
のアクセプタまたはドナーとなるイオン化率を97
〜100%を有し、添加した不純物のすべてを活性
化することができた。
Furthermore, silicon carbide obtained using this high-energy method was able to have a so-called SAS structure having a microcrystalline structure with a size of 5 to 200 A.
In such SAS, the ionization rate of the acceptor or donor of the or N-type impurity is 97
~100% and was able to activate all of the added impurities.

以下に図面に従つて本発明のプラズマ気相法を
説明する。
The plasma vapor phase method of the present invention will be explained below with reference to the drawings.

第1図は本発明を用いたプラズマCVD装置の
概要を示す。
FIG. 1 shows an outline of a plasma CVD apparatus using the present invention.

第1図において被形成面を有する基板1は角型
の石英ホルダーにて保持され、図面では7段2列
計14まいの構成をさせている。基板およびホルダ
ーは反応炉の前方の別室29に入口30より予め
設置され、バルブ32ロータリーポンプ33によ
り真空びきがなされる。さらに開閉とびら34を
開けて、反応炉内に自動送り装置により導入さ
れ、さらにミキサー用混合板35も同時配置され
る。これらは反応炉、別室ともに真空状態におい
てなされ、反応炉内に酸素(空気)が少しでも混
入しないように務めた。さらに開閉とびら34を
閉じたことにより、図面の如く電極9,10の間
に基板が配置された。
In FIG. 1, a substrate 1 having a surface to be formed is held in a square quartz holder, and as shown in the drawing, it has a total of 14 holders in 7 stages and 2 rows. The substrate and holder are placed in advance in a separate chamber 29 at the front of the reactor through an inlet 30, and vacuum is applied by a valve 32 and a rotary pump 33. Furthermore, the opening/closing door 34 is opened and the mixture is introduced into the reactor by an automatic feeding device, and a mixing plate 35 for a mixer is also placed at the same time. These were carried out in a vacuum state in both the reactor and a separate room to prevent even the slightest amount of oxygen (air) from entering the reactor. Further, by closing the opening/closing door 34, the substrate was placed between the electrodes 9 and 10 as shown in the drawing.

各基板は10〜40mm代表的には20〜25mmの間かく
をおいて配列されており、このホルダーによる反
応性気体は反応炉25の前方にミキサ8を設け層
流とし、さらにこれらの反応性気体が基板の間の
空隙に均一に注入するように設けてある。被形成
面は基板の下面または互いに裏面を重ね合わせて
垂直に配置された側面である。
The substrates are arranged at intervals of 10 to 40 mm, typically 20 to 25 mm, and a mixer 8 is installed in front of the reactor 25 to flow the reactive gas from this holder into a laminar flow. The gas is provided to be uniformly injected into the gap between the substrates. The surface to be formed is the lower surface of the substrate or side surfaces arranged vertically with their back surfaces stacked on top of each other.

また図面は反応系を上方よりながめた構造を示
したものであり、基板1は互いに裏面を合わせて
垂直に配置させている。かくの如く重力を利用し
てフレイクを下部に除去することは、量産歩留り
を考慮する時きわめて重要である。さらにこの基
板1を折入させた反応炉25には、この基板に垂
直または平行(特に平行にすると被膜の均一性が
得やすい)に電磁エネルギの電界が第2図Aまた
はB特にBの如くに加わるように一対の電極9,
10を上下または左右に配置して設けた。この電
極の外側に電気炉5が設けられており、基板1が
100〜400℃代表的には300℃に加熱されている。
Further, the drawing shows the structure of the reaction system viewed from above, and the substrates 1 are arranged vertically with their back surfaces facing each other. Removing flakes to the bottom using gravity in this way is extremely important when considering mass production yield. Further, in the reactor 25 into which this substrate 1 is inserted, an electric field of electromagnetic energy is applied perpendicularly or parallelly to the substrate (especially if it is parallel, it is easier to obtain a uniform coating) as shown in FIG. 2 A or B, especially B. a pair of electrodes 9,
10 were arranged vertically or horizontally. An electric furnace 5 is provided outside this electrode, and the substrate 1 is
It is heated to 100-400℃, typically 300℃.

反応性気体は水素またはヘリユームのキヤリア
ガス例えばヘリユームを13より、価の不純物
であるジボラン14より、価の不純物であるフ
オスヒン15より、価の添加物である珪化物気
体のシラン16より導入した。
Reactive gases were introduced from a carrier gas of hydrogen or helium, such as helium 13, from diborane 14, a valence impurity, from phosphin 15, a valence impurity, and from silane 16, a silicide gas, a valence additive.

また炭素−珪素結合を有する反応性気体TMS
20を用いると、初期状態で液体であるためステ
ンレス容器21に保存される。この容器は電子恒
温層22により所定の温度に制御されている。
Also, reactive gas TMS with carbon-silicon bonds
When 20 is used, it is stored in a stainless steel container 21 because it is liquid in the initial state. This container is controlled at a predetermined temperature by an electronic constant temperature layer 22.

このTMSは沸点が25℃であり、ロータリーポ
ンプ12をバルブ11をへて排気させ、反応炉内
を0.01〜10torr特に0.02〜0.4torrに保持させた。
こうすることにより、1気圧より低い圧力により
結果として特に加熱しなくてもTMSを気化させ
ることができる。この気化したTMSを100%の濃
度で流量計を介して反応炉に導入することは、従
来の如く容器21をバブルして反応性気体を放出
するやり方に比較して、その流量制御が精度よく
可能であり、技術上重要である。
This TMS has a boiling point of 25° C., and the rotary pump 12 was evacuated through the valve 11 to maintain the inside of the reactor at 0.01 to 10 torr, particularly 0.02 to 0.4 torr.
In this way, TMS can be vaporized at a pressure lower than 1 atmosphere without any particular heating. Introducing this vaporized TMS into the reactor at 100% concentration through a flow meter allows for more accurate flow control than the conventional method of bubbling the container 21 to release reactive gas. possible and technically important.

実用上流量計がつまつた場合、図面において2
4よりヘリユームを導入した。
In practice, if the flow meter becomes clogged, 2.
Helium was introduced from 4.

また反応筒25またはホルダー2の内壁または
表面に付着した反応生成物を除去する場合は17
よりCE4またはCF4+O2(2〜5%)を導入し、
電磁エネルギを加えてフツ素ラジカルを発生させ
て気相エツチングをして除去した。
In addition, when removing reaction products attached to the inner wall or surface of the reaction tube 25 or holder 2, 17
Introducing CE 4 or CF 4 + O 2 (2-5%),
Fluorine radicals were generated by applying electromagnetic energy and removed by gas phase etching.

さらにこのプラズマ放電においては、反応性気
体が混合室8をへて混合された後、励起室26に
おいて分解または反応をおこさしめ、反応生成物
を基板上に形成する空間反応を主として用いた。
電磁エネルギは電源4より直流または高周波を主
として用いた。
Furthermore, in this plasma discharge, after reactive gases are mixed through the mixing chamber 8, they are decomposed or reacted in the excitation chamber 26, and a spatial reaction is mainly used to form a reaction product on the substrate.
As electromagnetic energy, direct current or high frequency from the power source 4 was mainly used.

このようにして被形成面上に炭化珪素被膜を形
成した。例えば基板温度300℃、高周波エネルギ
の出力25W、シランまたはTMS50c.c./分キヤリ
アガスとしてのHe250c.c.分とした。(反応性気
体/He)5において160A/分の被膜成長速度を
得ることができた。
In this way, a silicon carbide film was formed on the surface to be formed. For example, the substrate temperature was 300° C., the high frequency energy output was 25 W, and the silane or TMS was 50 c.c./min and the carrier gas was He 250 c.c. min. (Reactive gas/He) A film growth rate of 160 A/min could be obtained at 5.

さらにこの被膜形成には、PIN接合、PN接合、
PI、NI接合、PINPIN接合等をその必要な厚さ
に必要な反応生成物を基板上に漸次積層して形成
させた。
Furthermore, this film formation requires PIN junction, PN junction,
PI, NI junctions, PINPIN junctions, etc. were formed by gradually stacking the necessary reaction products on the substrate to the required thickness.

このようにして被形成面上に被膜を形成させて
しまつた後、反応性気体を反応筒より十分にパー
ジした後、開閉とびら34を開け、ミキサ用混合
板35、ジグ3上の基板を別室29に自動引出し
管により反応筒および別室をともに真空
(0.01torr以下)にして移動させた。さらに開閉
とびら34を閉じた後、別室に31よりバルブを
開けて空気を充填し大気圧とした後、外部にジグ
および被膜の形成された基板をとり出した。
After the film has been formed on the surface to be formed in this manner, the reactive gas is sufficiently purged from the reaction tube, and the opening/closing door 34 is opened to remove the mixer mixing plate 35 and the substrate on the jig 3. Both the reaction column and the separate chamber were moved to a separate chamber 29 using an automatic extraction tube under vacuum (0.01 torr or less). Further, after closing the opening/closing door 34, a valve 31 was opened in the separate chamber to fill it with air to bring it to atmospheric pressure, and then the jig and the substrate on which the film was formed were taken out.

以上の実施例より明らかな如く、本発明は反応
性気体をミキサ8にて混合した後、排気口6に層
状(ミクロにはプラズマ化された状態ではランダ
ム運動をしていた)に流し、この流れに平行に基
板を配置して被形成面上にの膜厚が±5%以内の
バラツキで0.1〜3μの厚さに被膜を形成せしめた
ことを特徴としている。
As is clear from the above embodiments, the present invention involves mixing reactive gases in the mixer 8, and then flowing the reactive gases into the exhaust port 6 in a layered manner (microscopically, they were in random motion when turned into plasma). It is characterized in that the substrate is arranged parallel to the flow, and a film is formed on the surface to have a thickness of 0.1 to 3 μm with a variation within ±5%.

さらにこの際プラズマをグロー放電法を利用し
ておこさせるが、その電極を反応筒の外側に配置
せしめ、多量の基板に均一にプラズマがおこるよ
うにしたことを特徴としている。
Further, at this time, plasma is generated using a glow discharge method, and a feature is that the electrode is placed outside the reaction tube so that plasma can be generated uniformly over a large number of substrates.

また被膜の形成に際し、図面の如く7段2列で
はなく、20段20列の如く反応筒を長くする場合、
0.4torrではなくさらに0.2、0.1、0.05torrとより
低圧にすることが、その膜質の均一性特に最前列
と最後列との均一性を得しめる上に重要である。
Also, when forming a film, if the reaction tube is made longer, such as 20 stages and 20 rows, instead of 7 stages and 2 rows as shown in the drawing,
It is important to use a lower pressure of 0.2, 0.1, or 0.05 torr instead of 0.4 torr in order to obtain uniformity of the film quality, especially uniformity between the front row and the rear row.

またこの反応筒内に酸素等の制御できない酸化
物気体の混入を防ぐため、別室を設け、この別室
を介して大気中での作業と結合せしめたことは、
得られた被膜の特性の再現性を得るのにきわめて
重要であつた。
In addition, in order to prevent uncontrollable oxide gases such as oxygen from entering the reactor, a separate chamber was provided, and the work was connected to the atmosphere through this separate chamber.
This was extremely important in obtaining reproducibility of the properties of the resulting coatings.

第2図は第1図の図面における排気口6方向よ
りみた基板1の配置と電極9,10との関係を示
す。図面においてAは基板を水平、電極9,10
による電磁界を水平方向に配置したもので、この
場合一度に導入できる基板の枚数をふやすことが
できる。
FIG. 2 shows the relationship between the arrangement of the substrate 1 and the electrodes 9 and 10 when viewed from the direction of the exhaust port 6 in the drawing of FIG. In the drawing, A indicates that the substrate is horizontal and the electrodes 9 and 10 are
In this case, the number of substrates that can be introduced at once can be increased.

第2図Bは電極9,10による電磁界、基板1
ともに垂直にしたもので、基板の配置数がAの2
倍になる。
Figure 2B shows the electromagnetic field caused by the electrodes 9 and 10, and the substrate 1
Both are vertical, and the number of boards arranged is 2 of A.
Double.

第3図は本発明の半導体装置作製方法の操作手
順チヤートを示したものである。
FIG. 3 shows an operational procedure chart of the semiconductor device manufacturing method of the present invention.

図面において“0”である49は反応炉の真空
引による0.01torr以下の保持を示す。さらに
“1”の40は本発明による反応炉または反応筒
およびホルダーに珪素または炭化珪素のコーテイ
ングを示す。
In the drawing, 49, which is "0", indicates maintenance of 0.01 torr or less by evacuation of the reactor. Furthermore, 40 of "1" indicates coating of silicon or silicon carbide on the reactor or reaction cylinder and holder according to the present invention.

このコーテイングはその詳細を示すと第3図
B,Cである。第3図Bは真空引49により
0.01torr以下にし、10〜30分保持した後、水素を
電磁エネルギにより0〜30分30〜50Wの出力によ
りプラズマクリーニングを行ない、吸着、水分、
酸素を除去した。さらにその水素を除去した後、
51によりヘリユームを同時に30〜50Wの出力に
より10〜30分プラズマ化し、さらに表面の水素を
除去した。この水素プラズマ発生50に対して
は、水素中に1〜5%の濃度でHClまたはClを添
加して行なうと、塩素ラジカルが同時に発生し、
このラジカル石英等ホルダーの内側に存在してい
るナトリユームの如きアルカリ金属をすい出す効
果を有する。このためバツクグラウンドレベルで
のナトリユーム、水分、酸素の濃度を形成された
被膜中にて1014cm-3以下にすることができ、きわ
めて重要な前処理工程であつた。
The details of this coating are shown in FIGS. 3B and 3C. Figure 3B is due to vacuum 49
After keeping the temperature at 0.01 torr or less for 10 to 30 minutes, the hydrogen is plasma cleaned using electromagnetic energy at an output of 30 to 50 W for 0 to 30 minutes to remove adsorption, moisture,
Oxygen was removed. After further removing the hydrogen,
51, helium was simultaneously turned into plasma for 10 to 30 minutes with an output of 30 to 50 W, and hydrogen on the surface was further removed. For this hydrogen plasma generation 50, when HCl or Cl is added to hydrogen at a concentration of 1 to 5%, chlorine radicals are generated at the same time.
This radical quartz has the effect of scooping out alkali metals such as sodium present inside the holder. Therefore, the background level concentration of sodium, water, and oxygen in the formed film could be reduced to 10 14 cm -3 or less, which was an extremely important pretreatment step.

この塩素を添加した場合、さらにこの壁面に残
留吸着した塩素を除去するため51の不活性気体
によるスパツタリングによる除去も有効であつ
た。
When this chlorine was added, sputtering with an inert gas in No. 51 was also effective in removing the chlorine remaining adsorbed on the wall surface.

この後これらの系を真空引した後、珪化物気体
であるシランまたは炭化珪素化物であるTMSを
導入し、プラズマエネルギにより分解して、0.1
〜2μ代表的には0.2〜0.5μの厚さに形成させた。
これらの被膜形成をさせる際、高い電磁エネルギ
が加わる領域すなわち不純物が再放出されやすい
領域に特に厚くつきやすく、二重に好ましい結果
をもたらせた。
After evacuating these systems, silane, which is a silicide gas, or TMS, which is a silicon carbide compound, is introduced and decomposed by plasma energy to 0.1
It was formed to a thickness of ~2μ, typically 0.2-0.5μ.
When these films were formed, they tended to be particularly thick in areas where high electromagnetic energy was applied, that is, areas where impurities were likely to be re-emitted, resulting in doubly favorable results.

かかる本発明の複雑な前処理工程を行わない場
合であつても、第3図Cに示す如く真空引の後、
珪素または炭化珪素を52において同様に0.1〜
2μ形成し、反応炉壁からの酸素、アルカリ金属
の再放出を防ぐことが有効であつた。
Even if the complicated pretreatment process of the present invention is not performed, after evacuation as shown in FIG. 3C,
Similarly, silicon or silicon carbide is 0.1 to 52.
It was effective to prevent the re-release of oxygen and alkali metals from the reactor wall by forming 2μ.

また第3図Aにおいては半導体装置の作製のた
め、基板のコーテイング、系の真空引41さらに
PまたはN型半導体の作製42、I型半導体層の
作製43、N型半導体層の作製44を行い、第1
の半導体装置を作製48した。この半導体装置は
前記したPI、NI、PIN、PN等の接合を少くとも
1つ有するデイバイス設計仕様によつて作らなけ
ればならないことはいうまでもない。
In addition, in FIG. 3A, in order to fabricate a semiconductor device, coating the substrate, evacuation of the system 41, fabricating a P or N type semiconductor 42, fabricating an I type semiconductor layer 43, and fabricating an N type semiconductor layer 44 are performed. , 1st
48 semiconductor devices were manufactured. Needless to say, this semiconductor device must be manufactured according to device design specifications having at least one junction such as PI, NI, PIN, PN, etc. described above.

さらにこの後、この系に対し、反応炉のみまた
はこの反応炉とホルダーを挿入設置された反応系
に対し46に示すI型半導体層または42′に示
す半導体層と同じ半導体層のコーテイングにより
前の半導体装置作製の際用いられた工程44のり
れきが次のランに対して影響を与えないようにし
た。その詳細は第3図B,C,D,Eに示す。
Furthermore, after this, for this system, the reaction system in which only the reactor or the reactor and the holder are inserted is coated with the same semiconductor layer as the I-type semiconductor layer shown at 46 or the semiconductor layer shown at 42'. The debris in step 44 used in manufacturing the semiconductor device was prevented from affecting the next run. The details are shown in FIGS. 3B, C, D, and E.

すなわち第3図Bは前記した前処理と同じく真
空引49水素プラズマ放電50、ヘリユームプラ
ズマ処理51、半導体装置のランの最初の工程の
半導体層を形成する工程52を有する。しかしこ
の50,51がすでにAでの46で行われている
ため、一般にはCの52での0.1〜2μの厚さの半
導体層の作製で十分であつた。
That is, FIG. 3B has the same steps as the pretreatment described above, including evacuation 49, hydrogen plasma discharge 50, helium plasma treatment 51, and step 52 of forming a semiconductor layer, which is the first step in the run of the semiconductor device. However, since these steps 50 and 51 have already been carried out at 46 in A, it is generally sufficient to fabricate a semiconductor layer with a thickness of 0.1 to 2 μm in 52 C.

またこの前の半導体装置の作製40すなわち前
のランでの履歴をなくすため、D,Eに示すプラ
ズマエツチング工程を行つてもよい。すなわち第
3図Bは真空引49CF4またはCF4+O2(約5%)
を第1図での17より導入し、20分〜1時間プラ
ズマエツチング53を行なつた。さらに真空引を
してその後C、Fの残留物を除去するため水素プ
ラズマ処理50を10〜30分、さらにこのI層に
0.05〜0.5μのI型または次の工程の最初のランの
半導体層42′と同様の導電型、成分の半導体層
の作製を行なつた。この方法が最も徹底して再現
性を保証することができた。
Further, in order to eliminate the history of the previous semiconductor device fabrication 40, that is, the previous run, plasma etching steps shown in D and E may be performed. In other words, Figure 3B shows the vacuum 49CF 4 or CF 4 +O 2 (approximately 5%)
was introduced from 17 in FIG. 1, and plasma etching 53 was performed for 20 minutes to 1 hour. After further evacuation, hydrogen plasma treatment 50 was applied for 10 to 30 minutes to remove C and F residues, and then this I layer was further treated with hydrogen plasma for 10 to 30 minutes.
A semiconductor layer of 0.05 to 0.5 μm type I or the same conductivity type and composition as the semiconductor layer 42' of the first run in the next step was prepared. This method was the most thorough and could guarantee reproducibility.

簡単な方法としてはEに示す49の真空引、プ
ラズマエツチング53残部吸着ガスの除去50の
工程を行なつた。
As a simple method, steps 49 of evacuation, plasma etching 53, and removal of the remaining adsorbed gas 50 shown in E were performed.

かくすることにより第1の半導体装置の作製4
8の最後工程44と次の工程48′の最初の工程
42′との間でPまたはN型の不純物が互いに4
2′にて混入する可能性を除去することができた。
In this way, the first semiconductor device is manufactured 4
Between the last step 44 of step 8 and the first step 42' of the next step 48', P or N type impurities are mixed with each other.
2' was able to eliminate the possibility of contamination.

また44での炭素、ゲルマニユーム等の添加物
を42′にて混入することも防ぐことができた。
It was also possible to prevent the addition of additives such as carbon and germanium at 44 to 42'.

かかる本発明の方法によりその効果を評価した
結果を第4図に示す。
FIG. 4 shows the results of evaluating the effects of the method of the present invention.

第4図は本発明方法を用いて作られた光電変換
装置の結果である。この場合基板として金属例え
ばステンレス基板または透光性基板であるガラス
上にITOを500〜2000A、さらにこの上に酸化ス
ズまたは酸化アンチモンを100〜500Aの厚さに形
成させた多重膜の電極を有する基板を用いた。こ
の上にP型炭化珪素(SixC1-x0x1)(例え
ばx=0.3〜0.5)を100〜300Aの厚さにまたこの
上面に真性または実質的に真性のASまたはSAS
の珪素を0.4〜0.7μの厚さに、さらにこの上面に
N型炭化珪素(SixC1-x0x1例えばx=0.3
〜0.5)を100〜300Aの厚さに形成させたPIN構
造を有せしめた。このP、I、N型半導体の仕様
は第3図Aのチヤートにおける42,43,4
4,42′…に対応させた。
FIG. 4 shows the results of a photoelectric conversion device manufactured using the method of the present invention. In this case, the substrate is a metal such as a stainless steel substrate or a translucent glass substrate with a multilayer electrode of 500 to 2000 amps of ITO and further formed with tin oxide or antimony oxide to a thickness of 100 to 500 amps. A substrate was used. On top of this, P-type silicon carbide (SixC 1-x 0x1) (e.g.
silicon to a thickness of 0.4 to 0.7μ, and then N-type silicon carbide (SixC 1-x 0x1 e.g. x = 0.3
~0.5) to a thickness of 100 to 300A. The specifications of this P, I, and N type semiconductor are 42, 43, and 4 in the chart of Figure 3A.
4,42'...

さらにこの後この工程にITOを600〜800Aの厚
さにまたはアルミニユーム金属膜を真空蒸着法で
形成して光電変換装置を作つた。その変換効率を
第4図Aに示す。
Further, in this step, a photoelectric conversion device was fabricated by forming an ITO film to a thickness of 600 to 800 A or an aluminum metal film using a vacuum evaporation method. The conversion efficiency is shown in FIG. 4A.

1cm2のセルの大きさでAM1(100mW/cm2)の
条件にて前処理40をいれない場合71の3%
が、また前処理を行なうと70の値が得られた。
さらに中間の46の工程を加えることによるラン
(製造 )の効率の変化60になり全く加えな
いと61が得らえた。
3% of 71 without pretreatment 40 under AM1 (100 mW/cm 2 ) condition with cell size of 1 cm 2
However, when pretreatment was performed again, a value of 70 was obtained.
Further, by adding 46 intermediate steps, the change in run (manufacturing) efficiency was 60, whereas if no steps were added, 61 was obtained.

60はその効率が11〜9%を得ることができる
のに対し、本発明方法を用いない場合1〜4%し
かなかつた。
60 can obtain an efficiency of 11 to 9%, whereas it was only 1 to 4% when the method of the present invention was not used.

さらにこのセル面積を100cm2にすると、本発明
方法を用いると7〜9%の効率を得ることができ
るのに際し、本発明方法を用いないと0〜3%で
あつた。特にダイオード特性がないものが30%以
上を有し、製造不可能であつた。
Further, when the cell area is set to 100 cm 2 , an efficiency of 7 to 9% can be obtained using the method of the present invention, whereas it was 0 to 3% when the method of the present invention is not used. In particular, 30% or more of them had no diode characteristics, making it impossible to manufacture them.

第4図Bは特に表面程にてP型の半導体を作る
工程でI型の珪素半導体を作つた場合の電気伝導
度の値を示す。
FIG. 4B shows the value of electrical conductivity when an I-type silicon semiconductor is made in the process of making a P-type semiconductor especially at the surface level.

前工程でP型半導体を作り、本発明方法の中間
処理法の前処理を行なわない時、AM1の光照射
による電気伝導度が65である。暗伝導度64と
逆の場合もみられ、またその値も10-6〜10-4で大
きな、バラツキがあつた。他方本発明の前処理を
行なつた場合、光伝導度70、暗伝導度70′が
得られた。また中間処理を行なつた時に光伝導度
62、暗伝導度63が得られた。これらは本発明
におけるドーピング効果防止がいかに重要である
かを明確に示したものである。
When a P-type semiconductor is produced in the pre-process and no pre-treatment is performed in the intermediate treatment method of the method of the present invention, the electric conductivity of AM1 when irradiated with light is 65. There were also cases where the dark conductivity was 64 and the opposite, and the values also varied widely from 10 -6 to 10 -4 . On the other hand, when the pretreatment of the present invention was carried out, a photoconductivity of 70 and a dark conductivity of 70' were obtained. Further, when intermediate treatment was performed, a photoconductivity of 62 and a dark conductivity of 63 were obtained. These clearly show how important it is to prevent doping effects in the present invention.

以上の説明より明らかな如く、本発明は同一反
応筒を用いて光電変換装置または発光素子のみな
らず、電界効果半導体装置、フオトセンサアレー
等の各種の半導体装置を作製する上にきわめて重
要な製造装置および製造方法を提供したものであ
り、これにより従来たて型のプラズマCD装置に
て10cm□ を4まい作ると同じ時間で、100〜500ま
いの基板上に非単結晶半導体膜を作ることがで
き、きわめて多量生産向きである。さらに本発明
の如き電極構造または基板の配置をすることによ
り、PIN構造を有する光電変換装置において10%
以上の変換効率をくりかえし安定して得ることが
でき、その膜質においてもきわめてすぐれたもの
であつた。
As is clear from the above description, the present invention is extremely important in manufacturing not only photoelectric conversion devices or light emitting devices, but also various semiconductor devices such as field effect semiconductor devices and photo sensor arrays using the same reaction tube. The company provides equipment and a manufacturing method that enables the production of non-single crystal semiconductor films on 100 to 500 square substrates in the same amount of time as it takes to produce four 10 cm square squares using a conventional vertical plasma CD device. This makes it extremely suitable for mass production. Furthermore, by arranging the electrode structure or substrate as in the present invention, 10%
The above conversion efficiency could be repeatedly and stably obtained, and the film quality was also extremely excellent.

本発明においては、炭化珪素(SixC1-x0x
1)を中心として記した。しかし反応性気体を
ゲルマンを用いると、SixGe1-x(0x1)を
得ることができ、第1のPIN構造を珪素と炭化珪
素によりさらに第2のPIN構造を珪素と珪化ゲル
マニユームによりPINPIN構造いわゆるタンデム
構造を得ることも可能である。
In the present invention, silicon carbide (SixC 1-x 0x
The main focus is on 1). However, if germane is used as a reactive gas, SixGe 1-x (0x1) can be obtained, and the first PIN structure is made of silicon and silicon carbide, and the second PIN structure is made of silicon and germanium silicide to form a so-called tandem PIN structure. It is also possible to obtain a structure.

本発明は第1図に示す横型のプラズマCVD装
置を中心として示した。しかしその電極の作り方
を誘電型としたり、またアーク放電を利用するプ
ラズマCVD装置であつても本発明は有効である。
またたて型、たて横型のベルジヤー型のプラズマ
CVD装置であつても同様に本発明方法を適用す
ることができる。
The present invention has been mainly described with reference to a horizontal plasma CVD apparatus shown in FIG. However, the present invention is also effective even in a plasma CVD apparatus in which the electrode is made of a dielectric type or uses arc discharge.
Vertical and horizontal bergier type plasmas
The method of the present invention can be similarly applied to CVD equipment.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のプラズマ気相装置である。第
2図は第1図の一部を示す。第3図は第1図の装
置を用い、本発明方法のプラズマ気相法を用いる
チヤートである。第4図Aは第3図のチヤートに
従つて得られた光電変換装置の効率およびBは本
発明方法のドーピング防止効果を示す他の資料で
ある。
FIG. 1 shows a plasma vapor phase apparatus of the present invention. FIG. 2 shows a part of FIG. FIG. 3 is a chart using the plasma vapor phase method of the present invention using the apparatus shown in FIG. FIG. 4A shows the efficiency of the photoelectric conversion device obtained according to the chart of FIG. 3, and B shows other data showing the doping prevention effect of the method of the present invention.

Claims (1)

【特許請求の範囲】 1 プラズマ気相法により反応炉内に配設された
基板上にPまたはN型の半導体層を形成するに際
し、上記半導体層を成形する前に、前記反応炉内
壁または基板ホルダーの表面に、真性または実質
的に真性の半導体層または次に形成すべき導電型
と同じ導電型の半導体層を形成することにより、
前工程で形成された半導体層中のPまたはN型の
不純物、若しくは反応炉内壁よりの酸素、アルカ
リ金属等の不純物が、新たに形成すべき基板上の
半導体層中へ混入するのを防止することを特徴と
する半導体装置作製方法。 2 特許請求の範囲第1項において、反応炉、ま
たは反応炉および反応炉に設置した基板ホルダー
に対する真性または実質的に真性の半導体層の形
成が半導体層の作製温度T0に対しT0−50℃〜T0
+50℃の範囲で行われることを特徴とする半導体
装置作製方法。
[Claims] 1. When forming a P- or N-type semiconductor layer on a substrate disposed in a reactor by plasma vapor phase method, before forming the semiconductor layer, the inner wall of the reactor or the substrate By forming on the surface of the holder an intrinsic or substantially intrinsic semiconductor layer or a semiconductor layer of the same conductivity type as that to be formed next,
Prevents P- or N-type impurities in the semiconductor layer formed in the previous process, or impurities such as oxygen and alkali metals from the inner wall of the reactor, from entering the semiconductor layer on the newly formed substrate. A method for manufacturing a semiconductor device characterized by the following. 2. In claim 1, the formation of an intrinsic or substantially intrinsic semiconductor layer in a reactor, or in a reactor and a substrate holder installed in the reactor is performed at a temperature T 0 −50 relative to the semiconductor layer production temperature T 0 . ℃〜T 0
A method for manufacturing a semiconductor device, characterized in that it is performed in a temperature range of +50°C.
JP56191267A 1981-11-28 1981-11-28 Manufacture of semiconductor device Granted JPS5892217A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56191267A JPS5892217A (en) 1981-11-28 1981-11-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56191267A JPS5892217A (en) 1981-11-28 1981-11-28 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5892217A JPS5892217A (en) 1983-06-01
JPH0341978B2 true JPH0341978B2 (en) 1991-06-25

Family

ID=16271694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56191267A Granted JPS5892217A (en) 1981-11-28 1981-11-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5892217A (en)

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