JPH0341989B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device that uses a MOS transistor with a floating gate as a memory cell to non-volatilely retain data once stored. Regarding programmable ROM (read-only memory).

[Technical background of the invention and its problems]

Conventionally, semiconductor memory devices that hold data in a non-volatile manner have used a so-called double-gate structure MOS transistor in which a floating gate and a control gate are stacked on a channel region as shown in FIG. 5, for example, as a memory cell. As shown in FIG. 6, the gate is connected to a word line, the drain is connected to a data line, and the source is connected to a ground terminal. In the figure, 1 is a semiconductor substrate, 2 and 3 are source and drain regions, 4 is a channel region, 5 is a control gate, 6 is a floating gate, 7, 8, 11, and 12 are oxide films, 9, 1
0 is aluminum wiring, T is as memory cell
In the MOS transistor, W is a word line and D is a data line. In this case, depending on whether or not electrons are injected into the floating gate, the memory is set to “0” or “0”.
1” information is stored and retained in a non-volatile manner.

However, since the conventional memory cell described above has one floating gate and one data line, only one piece of information, either "1" or "0", can be stored in one memory cell. In other words, 1K memory cells were required to have a storage capacity of 1K bits, and 1M memory cells were required to have a memory capacity of 1M bits, and in order to obtain a large capacity memory, the memory chip size had to be large. .

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and includes:
To provide a semiconductor memory device that can store four-value information in one memory cell by storing two pieces of information in one memory cell and encoding/decoding information to and from the memory cell. It is something.

[Summary of the invention]

In order to achieve the above object, the present invention includes a semiconductor substrate of one conductivity type, first and second semiconductor regions of the other conductivity type that are formed separately from each other on this substrate and serve as a source and a drain, respectively; a control gate formed on the channel region between them with an insulating film interposed therebetween; and a control gate formed on the channel region with an insulating film interposed therebetween on the first semiconductor region side and the second semiconductor region side, respectively. A MOS transistor having first and second floating gates formed adjacent to each other through an insulating film is used as a memory cell, the control gate is connected to a word line, and the drain and source are connected to separate data lines. These two data lines are used to write/read data to each of the two floating gates, and the written/read data is connected to the read/write control circuit and data connected to the two data lines. The information is sent and received via the decoding/encoding circuit.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Figure 1 shows the floating gate of the same embodiment.
Although this is a cross-sectional view of a MOS transistor (memory cell) section, this is an example in which it corresponds to that of FIG. 5, so the same reference numerals are used for corresponding parts.
Here, a known normal semiconductor manufacturing process is used up to the formation of the control gate 5 using polysilicon. Thereafter, the polysilicon 5 is oxidized to form an oxide film 7, and then a polycrystalline silicon film doped with N-type or P-type impurities is deposited. Next, in this state, the deposited polycrystalline silicon film is etched away by the thickness thereof using an anisotropic etching method such as RIE (reactive ion etching) method. At this time, since the film thickness in the height direction is effectively thick around the pattern of the control gate 5, an uneven portion of the polycrystalline silicon film is formed as shown by 6a and 6b. Next, the remaining portions other than the upper part of the channel region, that is, the remaining portions formed on the field oxide film, etc., are etched using a normal isotropic etching method to etch the floating gates 6a and 6b.
form. Next, using a known normal semiconductor manufacturing process, impurities are introduced into the source and drain regions, and inter-device wiring patterning is performed using aluminum layers 9 and 10, to obtain a MOS transistor as shown in FIG.

The control gate of the MOS transistor T1 thus formed is connected to the word line W, and the source and drain are connected to the data lines D1 and D2, respectively, as shown in FIG. 2 to form a memory cell MC. Arrange in a matrix. In FIG. 2, FG1 and FG2 are floating gates, corresponding to those 6a and 6b. 21 is a write/read control circuit that exchanges data with the memory cell MC via data lines D1 and D2; 22 is a write/read control circuit that decodes/encodes input/output data and sends data to and from the memory cell MC to the write/read control circuit 21; This is a decode/encode circuit that performs sending and receiving.

When storing information in the above memory cell, first, to store information in the floating gate FG1, the word line W is set to a selected state, for example, at a voltage of 5V, by an address input and a decoder (both not shown), and then the data line D2 is set to a selected state, for example, at a voltage of 5V. The potential of the data line D1 is set to the ground potential, and the potential of the data line D1 is set to a sufficiently higher write voltage, for example, about 10 V, than the ground potential or the data line D2 by write data corresponding to input/output data. Here, when the potential of the data line D1 is the write potential, the MOS
Transistor T1 turns on and data lines D1 to D
Current flows to 2. At this time, MOS transistor T
The electric field applied between the source and drain of No. 1 becomes concentrated and strong near the drain, so impact
Hot carrier is generated by ionization, and a part of it is injected into the floating gate FG1.
On the other hand, when the potential of the data line D1 is the ground potential,
Since no current flows through MOS transistor T1,
No hot carrier occurs and no injection occurs.

When reading information from the floating gate FG1, set the word line W to the selected state, for example 5V, and set the data line 1 to the selected state.
is set to a ground potential, and the data line D2 is set to a read potential of, for example, 5V. At this time, if hot carriers are injected into the floating gate FG1, the MOS transistor T1 will not turn on due to the influence of the hot carriers injected into the floating gate. When there is no injection, there is no effect of the floating gate, so the MOS transistor T1 is turned on, and the data line D2 is connected to D1.
Current flows to. At this time, MOS transistor T1
Since the terminal on the data line D2 side becomes the drain,
Whether or not hot carriers are injected into the floating gate FG2 has no significant effect on the flowing current. This flowing current is detected by the write/read control circuit 21 and data is output.

When storing information in the floating gate FG2 or reading the information, use the data line D1 mentioned above.
The same procedure can be performed by reversing the relationship between and D2.

In order to make this memory cell capable of storing and reading four-value information, one address cycle is time-divided as shown in FIG.
The data transfer time t1 of the floating gate FG2 and the data transfer time t2 of the floating gate FG2 are divided into a data transfer time t1 and a data transfer time t2 of the floating gate FG2.
2, hot carriers may be injected into each of them. That is, when the input/output data is 0, the potentials of the data lines D1 and D2 are applied as explained above so that no hot carriers are injected into both floating gates. When the input/output data is 1, hot carriers are injected into the floating gate FG1 at time t1, and no injection is made into the floating gate FG2 at time t2. Even when the input/output data is 2 and 3, the injections shown in FIG. 4 may be performed at times t1 and t2, respectively. Input data 0-3
On the other hand, as shown in FIG. 4, data for determining whether or not to perform injection is generated by the decode/encode circuit 22 and write/read control circuit 21 in FIG. 2 corresponding to input data 0 to 3, respectively. Also, t
The reason why output data 0 to 3 are determined based on the data read out at times t1 and t2 is that the write/read control circuit 21 and decode/encode circuit in FIG. 2 determine the state of the floating gate FG1 at time t1. This is done by reading the state of the floating gate FG2 at time t2, and outputting the data. That is, in the memory according to the present invention, for one memory cell, (a) the first half t ₁ of one address cycle
(b) One data is written in the second half of one address cycle, _t2 . (stomach)
One piece of data is written in the first half of one address cycle, _t1 , and another data is written in the second half of one address cycle _{, t2} .
Read one data. (a) One piece of data is written in the first half t ₁ of one address cycle, and (b) another piece of data is written in the second half t ₂ of one address cycle. (a) Read one piece of data in the first half of one address cycle, t ₁ , (b) In the second half of one address cycle, t ₂
There are cases where one other piece of data is read out.

Generally speaking, it takes a very long time to bring the word line of a memory cell into a state where data can be written or read. However, in the present invention, when performing each of the above items in one address cycle, each can be performed by selecting the word line W once, so there is no need to select each word line twice as in the past, and the cost is greatly reduced. This makes it possible to reduce the time required to exchange data.

In this way, four-level data can be rapidly exchanged with one memory cell.

〔Effect of the invention〕

As explained above, according to the present invention, two floating gates are provided adjacent to both sides of a control gate.
A MOS transistor is used as a memory cell, two data lines are prepared to connect to the memory cell, and a write/read control circuit connected to the data line is configured to time-divide one address cycle and control the two floating gates. By making it possible to exchange information quickly and adding a circuit to encode/decode input/output data, it becomes possible to exchange four-level data with a single memory cell, and even if the capacity is increased, the chip size will not increase. It is something that can be controlled.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of a transistor used in an embodiment of the present invention, Fig. 2 is a memory circuit diagram using the same transistor, Fig. 3 is a timing chart explaining the above embodiment, and Fig. 4 is a diagram of the above embodiment. FIG. 5 is a sectional view of a transistor used in a memory cell of a conventional programmable ROM, and FIG. 6 is a circuit diagram of a memory cell using the same transistor. 5...Control gate, 6a, 6b, FG1, FG2
...Floating gate, T1...MOS with floating gate
Transistor, W...word line, D1, D2...
Data line, MC...memory cell, 21...write/read control circuit, 22...decode/encode circuit.

Claims (1)

[Claims] 1 As a memory cell for storing data, the first or second floating gates are arranged on both sides of a gate electrode controlled by a word line with an insulating film interposed therebetween. A MOS transistor is provided that is turned on or off depending on whether a carrier is present in the transistor, and two data lines are connected to the drain and source of the transistor, and data is exchanged with the memory cell via the data line. and a decode/encode circuit that decodes/encodes input/output data and causes the write/read control circuit to exchange data with the memory cell, the write/read control circuit A semiconductor memory device characterized in that one address cycle is time-divided and data is transferred to and from one memory cell twice.