JPH0347513B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an information processing device, particularly a data transfer device used in the field of high-speed data transfer such as a bit map display device.

Conventional technology Traditional data transfer uses word-based DMA
(Direct Memory Access) transfer method is commonly used. However, in the case of data transfer in a bitmap display device, one word of data does not necessarily correspond to one pixel. (For example, in the case of a binary image, one pixel is one bit.)
Therefore, a high-speed data transfer device that can specify the amount of data to be transferred in units of bits is required.

Therefore, we have previously proposed a data transfer device that aligns the bit positions of source data and destination data, as shown in FIG. (Patent Application No. 59-100965) In the figure, 201 is a 1-word (n bit) second buffer for storing read source data, and 202 is a buffer for storing new source data in the second buffer 201. When storing, the first buffer 203 of 1 word (n bits) stores the data previously held by the second buffer 201, and inputs the consecutive 2n bits of the first and second buffers. , a barrel shifter that outputs n consecutive bits from the bit position selected by the selection signal POINT, 204 an output buffer that stores the output of the barrel shifter 203, and 205 an output buffer for the bits selected by the signal MASK. Signal MOD between 204 and the corresponding destination data
performs the operation specified by and outputs the result,
For unselected bits, the arithmetic unit outputs the corresponding transfer destination data as is.

The operation of the conventional data transfer device configured as described above will be described below with reference to FIG. 3 as well. In the figure, A is an example of data at the transfer destination, , , are word data, the shaded portion is the data area to be transferred, and SADR is the first bit position at the transfer source. B is an example of data at the transfer destination, , , are word data, the shaded area is the area to which the data in the shaded area in A is to be transferred, and DADR is the first bit position at the transfer destination.

First, the control unit 206 controls SADR (A) and SADR (B).
Generates POINT signal from DADR. For example, the MSB (Most
Significant Bit) at bit position “0”, LSB
(Least Significant Bit) at bit position “n-”
1", the POINT signal should be a signal that selects the bit position of "SADR-DADR" when SADRDADR of the first buffer and "n+SADR-DADR" when SADR<DADR. (For example, n=
If 16SADR="11" and DADR="14", the first
A signal that selects bit position “13” of the buffer.
It is shown at position P in FIG. ) Figure 3 H to H show the input buffer (first and second buffers 202 and 201 shown connected) and output buffer 204 at each step after the POINT signal is determined by the control unit. Indicates the condition. C shows the state in which the transfer data is read into the second buffer 201, and P
n consecutive bits (1 word) starting from the bit position of
output buffer 20 through barrel shifter 203
It is stored in 4. The control unit 206 is the arithmetic unit 205
Furthermore, by generating a signal MASK for controlling a desired bit and a desired arithmetic control signal MOD, data can be transferred in word units. The following D shows a state in which the next data is read into the second buffer 201 and the contents of the old second buffer are stored in the first buffer 202. (The data to be transferred at this time is in the output buffer 204.)
E shows a state in which the next data is read into the second buffer 201 and stored into the first buffer 202. (The data to be transferred at this time is in the output buffer 204.) The conventional method described above is effective if the transfer direction is limited to positive (right to left) on the main scanning line.

However, for certain purposes, it becomes necessary to transfer in the negative direction on the main scanning line. For example, when moving the window (rectangular area on the bit map memory) shown in Figure 4A, if the transfer source data area 1 and transfer destination data area 2 overlap, conventionally only transfer direction B could be performed, so If the transfer in the scanning direction is positive (top → bottom), the valid transfer source data may have been rewritten when transferring at point a, making correct transfer impossible, or the area may be further transferred as shown in c. After subdividing, data is first transferred from the overlapping area (indicated by diagonal lines), and then other areas are transferred.

Problems to be Solved by the Invention In such conventional devices, data read first is fixed on the MSB side and processed, so data transfer on the main scanning line is fixed in the forward direction.
Transfer in the negative direction could not be performed.

The present invention has been made in view of these points,
It is an object of the present invention to provide a data transfer device capable of transferring data defined in bit units in both directions on a main scanning line with a simple configuration.

Means for Solving the Problems In order to solve the above problems, the present invention includes a flag indicating the transfer direction on the main scanning line, and changes the order of data input to the barrel shifter according to the contents of the flag. , the barrel shifter outputs data consistent with transfer in both directions.

Effects According to the above-described configuration, the present invention swaps the reading order using the bus switching circuit during transfer in the negative direction on the main scanning line, combines two consecutive words of the transfer source, and selects one word from among them that corresponds to one word of the transfer destination data. By selecting data, transfer in the negative direction on the main scanning line can also be performed.

Embodiment FIG. 1 is a block diagram showing an embodiment of a data transfer device of the present invention. In FIG. 1, configurations similar to the conventional one are indicated only by the correspondence of numbers with those in FIG. 2, and their explanations are omitted. Figure 1 101 is Figure 2 20
1, 102 to 202, 103 to 203, 1
04 corresponds to 204, and 105 corresponds to 205. In FIG. 1, 107 is a flag indicating the transfer direction on the main scanning line, and 108 is the flag 107.
If the output DIR is a forward transfer signal, the first buffer 102,
The contents of the second buffer 101 are output in the same order, and if DIR is a negative transfer signal, the first buffer 10 is output to the barrel shifter 103.
2. A bus switching circuit that switches the order of the contents of the second buffer 101 and outputs them. In addition to the function of the control unit 206 shown in FIG. This is a control unit that has the function of changing the order of the MASK signals.

The operation of the data transfer device according to an embodiment of the present invention configured as described above will be described below with reference to FIG. 5 as well. (Transfer in the forward direction is the same as the conventional one, so only the transfer in the reverse direction will be explained.) In the same figure, A is an example of data from the transfer source, and ,, are word data, and the shaded portion is data area to be transferred,
SADR' indicates the position of the first bit of the transfer source. B is an example of data at the transfer destination, , , are word data, the shaded area is the area to which the data in the shaded area in A is to be transferred, and DADR' is the first bit position at the transfer destination.

First, the control unit 109 controls the SADR′ of A and the SADR of B.
A POINT signal is generated from DADR′. (This can be done using a method similar to that shown in the conventional example.
In Fig. 5, it is indicated by P'. ) Figure 5 C to F are the control unit 1
After the POINT signal is determined in step 09, the input buffer (the first and second buffers 102 and 101 are shown connected) and the bus switching circuit 108 are provided with a barrel shifter that changes the order of the contents of the input buffer in word units. The state of the input and output buffers 103 and 104 at each step is shown. C shows a state in which transfer data is read into the second buffer 101.
However, in this case, n consecutive bit positions from P'
Since no valid transfer data exists in the bits, no transfer is performed and the next transfer source data is read. 2 shows a state in which the transfer source data is read into the second buffer 101, and the bus switching circuit 10
Continuous n bits from the bit position of P' of the data whose order has been changed by 8 are stored in the output buffer 104 through the barrel shifter 103. The control unit 109 generates a signal MASK for controlling a desired bit and a desired operation control signal MOD to the arithmetic unit 105, thereby making it possible to transfer data in units of words. Below, E shows a state in which data is read into the second buffer 101 and the contents of the old second buffer are stored in the first buffer 102. The data to be transferred at this time is the output buffer 104.
It is in. Since valid data exists in the input buffer 101, the contents of the second buffer 101 are transferred to the first buffer 101.
The state shown in FIG. 1 is transferred to the buffer 102. The data to be transferred at this time is in the output buffer 104.

As described above, according to the present invention, by simply adding a flag indicating the transfer direction to a conventional data transfer device and a bus switching circuit that switches the data reading order depending on the contents of the flag, transfer in not only the positive direction but also the negative direction can be performed. I can do it.

In the case of the example shown in Figure 5, two words of data are read at the start of the transfer, and the second word is read at the end of the transfer.
It became necessary to transfer the contents of the first buffer to the first buffer, but this is because the data to be transferred to the transfer destination spans the data of the transfer source, and the data of the transfer source is This is because it is necessary when transferring data to and from the transfer source.If there is a bit shift between the source data I and the destination data LO as shown in Figure 6, this process is necessary when transferring data in the positive direction, and is unnecessary when transferring data in the negative direction. It is.

Effects of the Invention The data transfer device of the present invention has a simple configuration and a main scanning circuit by providing a flag indicating the transfer direction on the main scanning line and a bus switching circuit that switches the input order of data depending on the contents of this flag. It is possible to transfer data defined in bit units not only in the positive direction but also in the negative direction on the scanning line, and its practical effects are great.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data transfer device according to the present invention, FIG. 2 is a block diagram of a conventional data transfer device, FIG. 3 is an explanatory diagram of the operation of the conventional data transfer device, and FIG. 4 is a conventional data transfer device. 5 is a diagram illustrating the operation of an embodiment of the present invention, and FIG. 6 is a diagram illustrating an example of bit misalignment between transfer source data and transfer destination data. 101...Second buffer, 102...First buffer, 103...Barrel shifter, 104...
Output buffer, 105... Arithmetic unit, 107... Flag, 108... Bus switching circuit, 109... Control unit.

Claims (1)

[Claims] 1. A flag that stores information on the data transfer direction on the main scanning line in a two-dimensional memory space, and two consecutive words of data from the transfer source (2n bits if 1 word is n bits). The first and second buffers held in the read order and the outputs of the first and second buffers are the first and second inputs, and when the flag is in the first state, the first input is the first buffer. 1 output, 2nd
a bus switching circuit that takes the input as a second output, and when the flag is in a second state, the first input as the second output and the second input as the first output; and outputs a selection signal. a control section and a first and second bus switching circuit;
The input is the output of
A data transfer device comprising: a barrel shifter that outputs bits; and a third buffer that holds the output of the barrel shifter, and uses the output of the third buffer as transfer data. 2 The third buffer changes the output of the barrel shifter to the first
This is an arithmetic unit that performs arithmetic operations between the first and second data by taking one word of the corresponding transfer destination as the second input, and the control unit outputs a selection signal for the barrel shifter and also controls the arithmetic unit. 2. The data transfer device according to claim 1, wherein the data transfer device has a structure for outputting a signal, and uses the output of the arithmetic unit as transfer data.