JPH0348653B2 - - Google Patents
Info
- Publication number
- JPH0348653B2 JPH0348653B2 JP58206178A JP20617883A JPH0348653B2 JP H0348653 B2 JPH0348653 B2 JP H0348653B2 JP 58206178 A JP58206178 A JP 58206178A JP 20617883 A JP20617883 A JP 20617883A JP H0348653 B2 JPH0348653 B2 JP H0348653B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- electrode
- emitter
- collector
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
- H10D48/30—Devices controlled by electric currents or voltages
- H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H10D48/34—Bipolar devices
- H10D48/345—Bipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions
Landscapes
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
(イ) 産業上の利用分野
本発明はパワートランジスタ、特にリング状エ
ミツタ領域を有するパワートランジスタの改良に
関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to improvements in power transistors, particularly power transistors having a ring-shaped emitter region.
(ロ) 従来技術
パワーアンプ等を半導体集積回路に組み込む場
合パワートランジスタがチツプの大部分を占める
ため、出来るだけ小面積で高効率のパワートラン
ジスタの実現が望まれている。リング状エミツタ
領域を有するパワートランジスタはベース電極に
面するエミツタベース接合を最も長く取れるの
で、面積的に効率が良く半導体集積回路に組込む
パワートランジスタとしては最適である。(b) Prior Art When a power amplifier or the like is incorporated into a semiconductor integrated circuit, the power transistor occupies most of the chip, so it is desired to realize a highly efficient power transistor with as small an area as possible. Since a power transistor having a ring-shaped emitter region can have the longest emitter-base junction facing the base electrode, it is efficient in terms of area and is optimal as a power transistor to be incorporated into a semiconductor integrated circuit.
従来用いていたリング状エミツタ領域を有する
パワートランジスタを第1図および第2図を参照
して説明する。このパワートランジスタはP型の
半導体基板1上にコレクタ領域となるN型のエピ
タキシヤル層2を設け、エピタキシヤル層2の底
面にはコレクタ領域の取出し抵抗を下げるために
N+型の埋め込み層3を設け、エピタキシヤル層
2表面にはN+型のコレクタコンタクト領域4を
平行に帯状に設け、コレクタコンタクト領域4間
のエピタキシヤル層2表面に帯状にP型のベース
領域5を設け、ベース領域5表面に連続したN+
型のリング状エミツタ領域6を設け、コレクタコ
ンタクト領域4ベース領域5およびエミツタ領域
6に夫々オーミツク接触する点線で示すコレクタ
電極7ベース電極8およびエミツタ電極9設けて
形成される。 A conventionally used power transistor having a ring-shaped emitter region will be explained with reference to FIGS. 1 and 2. In this power transistor, an N-type epitaxial layer 2 serving as a collector region is provided on a P-type semiconductor substrate 1, and a layer is formed on the bottom surface of the epitaxial layer 2 to lower the extraction resistance of the collector region.
An N + type buried layer 3 is provided, an N + type collector contact region 4 is provided in a strip shape in parallel on the surface of the epitaxial layer 2, and a P type base is provided in a strip shape on the surface of the epitaxial layer 2 between the collector contact regions 4. A region 5 is provided, and a continuous N + is formed on the surface of the base region 5.
A ring-shaped emitter region 6 is provided, and a collector electrode 7, a base electrode 8, and an emitter electrode 9 shown by dotted lines are provided in ohmic contact with the collector contact region 4, base region 5, and emitter region 6, respectively.
しかしながら上述した単層配線のリング状エミ
ツタ領域を有するパワートランジスタでは、エミ
ツタ電極9をベース電極8とコレクタ電極7の間
に配置しなければならず、この部分のリング状エ
ミツタ領域6を巾広に形成する必要があつた。こ
の結果エミツタ電極9を設けない巾狭のエミツタ
領域6にはベースバイアスが良くかかりきわめて
活性に働く反面、エミツタ電極9を設けた巾広の
エミツタ領域6にはベースバイアスが良くかから
ず不活性となる。このためにエミツタ領域6であ
りながら良く働らかない部分があり、面積的なロ
スを生ずる。またエミツタ領域6の働き方のアン
バランスから安全動作領域(A、S、O、)もス
トライプ型のパワートランジスタに比べて狭くな
り破壊に弱くなる。 However, in the above-mentioned power transistor having a ring-shaped emitter region of single-layer wiring, the emitter electrode 9 must be placed between the base electrode 8 and the collector electrode 7, and the ring-shaped emitter region 6 in this part must be made wide. It was necessary to form. As a result, the base bias is well applied to the narrow emitter region 6 where the emitter electrode 9 is not provided, making it extremely active, whereas the base bias is not well applied to the wide emitter region 6 where the emitter electrode 9 is provided, making it inactive. becomes. For this reason, there are parts of the emitter region 6 that do not work well, resulting in area loss. Furthermore, due to the unbalanced working of the emitter region 6, the safe operation area (A, S, O,) is narrower than that of a stripe-type power transistor, making it vulnerable to destruction.
(ハ) 発明の目的
本発明は斯点に鑑みてなされ、従来の欠点を大
巾に改善したリング状エミツタ領域を有するパワ
ートランジスタを実現することを目的とする。(c) Object of the Invention The present invention has been made in view of the above points, and an object of the present invention is to realize a power transistor having a ring-shaped emitter region that greatly improves the conventional drawbacks.
(ニ) 発明の構成
本発明に依れば第3図乃至第5図に示す如く、
一導電型の半導体基板11と、基板11上に設け
た逆導電型でコレクタ領域となるエピタキシヤル
層12と、エピタキシヤル層12表面に設けた逆
導電型のコレクタコンタクト領域14と一導電型
のベース領域16および逆導電型のリング状エミ
ツタ領域17と、エピタキシヤル層12表面を被
覆する第1の絶縁膜18と、コレクタコンタクト
領域14にオーミツク接触する第1コレクタ電極
19と、エミツタ領域17にオーミツク接触する
第1エミツタ電極20と、エミツタ領域17に囲
まれたベース領域16にオーミツク接触し第1の
絶縁膜18上を延在されるベース電極21と、第
1コレクタ電極19第1エミツタ電極20および
ベース電極21を被覆する第2の絶縁膜22と、
第1コレクタ電極19および第1エミツタ電極2
0を夫々連結して第2の絶縁膜22上に延在され
る第2コレクタ電極23および第2エミツタ電極
24とより構成されている。(d) Structure of the invention According to the present invention, as shown in FIGS. 3 to 5,
A semiconductor substrate 11 of one conductivity type, an epitaxial layer 12 of the opposite conductivity type provided on the substrate 11 and serving as a collector region, a collector contact region 14 of the opposite conductivity type provided on the surface of the epitaxial layer 12, and a collector contact region 14 of the opposite conductivity type provided on the surface of the epitaxial layer 12. A base region 16 , a ring-shaped emitter region 17 of opposite conductivity type, a first insulating film 18 covering the surface of the epitaxial layer 12 , a first collector electrode 19 in ohmic contact with the collector contact region 14 , and a first collector electrode 19 in ohmic contact with the emitter region 17 . A first emitter electrode 20 in ohmic contact, a base electrode 21 in ohmic contact with the base region 16 surrounded by the emitter region 17 and extending over the first insulating film 18, and a first collector electrode 19. 20 and a second insulating film 22 covering the base electrode 21;
First collector electrode 19 and first emitter electrode 2
The second collector electrode 23 and the second emitter electrode 24 are connected to each other and extend on the second insulating film 22.
(ホ) 実施例
本発明に依れば、P型の半導体基板11と、基
板11上に設けたコレクタ領域として働くエピタ
キシヤル層12と、エピタキシヤル層12底面に
設けたN+型の埋め込み層13と、エピタキシヤ
ル層12表面に帯状に平行に設けられたN+型の
コレクタコンタクト領域14と、コレクタコンタ
クト領域14と埋め込み層13を連結するN+型
のコレクタ導出領域15と、コレクタコンタクト
領域14間のエピタキシヤル層12表面に帯状に
且つコレクタコンタクト領域14と平行に設けら
れたP型のベース領域16と、ベース領域16表
面に設けた等間隔で中空部を有する連続したリン
グ状のエミツタ領域17と、エピタキシヤル層1
2表面を被覆するシリコン酸化膜より成る第1の
絶縁膜18と、コレクタコンタクト領域14およ
びエミツタ領域17にオーミツク接触する第1コ
レクタ電極19および第1エミツタ電極20と、
リング状のエミツタ領域17に囲まれたベース領
域16にオーミツク接触し第1の絶縁膜18上に
第1コレクタ電極19および第1エミツタ電極2
0と短絡しない様に延在されるベース電極21
と、一層目の第1コレクタ電極19第1エミツタ
電極20およびベース電極21を被覆して層間絶
縁を行うポリイミド等より成る第2の絶縁膜22
と、複数の第1コレクタ電極19および第1エミ
ツタ電極20を連結し第2の絶縁膜22上に延在
される第2コレクタ電極23および第2エミツタ
電極24とを具備している。(E) Embodiment According to the present invention, a P-type semiconductor substrate 11, an epitaxial layer 12 provided on the substrate 11 and serving as a collector region, and an N + type buried layer provided on the bottom surface of the epitaxial layer 12. 13, an N + type collector contact region 14 provided parallel to the surface of the epitaxial layer 12 in a strip shape, an N + type collector lead-out region 15 connecting the collector contact region 14 and the buried layer 13, and a collector contact region. 14, a P-type base region 16 provided in a belt shape on the surface of the epitaxial layer 12 and parallel to the collector contact region 14, and a continuous ring-shaped emitter having hollow portions at equal intervals provided on the surface of the base region 16. Region 17 and epitaxial layer 1
a first insulating film 18 made of a silicon oxide film covering two surfaces; a first collector electrode 19 and a first emitter electrode 20 in ohmic contact with the collector contact region 14 and the emitter region 17;
A first collector electrode 19 and a first emitter electrode 2 are in ohmic contact with the base region 16 surrounded by the ring-shaped emitter region 17 and are on the first insulating film 18 .
The base electrode 21 is extended so as not to be short-circuited with 0.
and a second insulating film 22 made of polyimide or the like that covers the first collector electrode 19, first emitter electrode 20, and base electrode 21 of the first layer to provide interlayer insulation.
and a second collector electrode 23 and a second emitter electrode 24 that connect the plurality of first collector electrodes 19 and first emitter electrodes 20 and extend on the second insulating film 22 .
本発明の特徴の1つは電極を2層構造とした点
にある。即ち第1コレクタ電極19第1エミツタ
電極20およびベース電極21は第1層目の電極
(第3図で点線で示す)であり、第2コレクタ電
極23第2エミツタ電極24は第2層目の電極
(第3図で一点破線で示す)である。第1コレク
タ電極19は第3図から明らかな様にコレクタコ
ンタクト領域14上に一定間隔で点在しており、
第1エミツタ電極20はリング状のエミツタ領域
17のベース領域16を露出した部分の間に一定
間隔で点在している。また第1コレクタ電極19
と第1エミツタ電極20は隣接させて同一間隔で
設けている。リング状のエミツタ領域17より中
央に露出したベース領域16に夫々ベース電極2
1をオーミツク接触し且つ第1コレクタ電極19
および第1エミツタ電極20間のすきまを一方向
にストライブ状に第1の絶縁膜18上に延在させ
てすべてのベース領域16を連結を行う。第2コ
レクタ電極23および第2エミツタ電極24は第
2の絶縁膜22上を一方向にストライプ状に延在
し、点在する第1コレクタ電極19および第1エ
ミツタ電極20の連結を行う。これによりベース
電極21と第2コレクタ電極23および第2エミ
ツタ電極24は第5図の如く、第2の絶縁膜22
により電気的に絶縁されている。またベース電極
21の延在方向と第2コレクタ電極23および第
2エミツタ電極24の延在方向は直交あるいはそ
れに近い状態であるのがパターン設計上望まし
い。 One of the features of the present invention is that the electrode has a two-layer structure. That is, the first collector electrode 19, the first emitter electrode 20, and the base electrode 21 are the electrodes of the first layer (indicated by dotted lines in FIG. 3), and the second collector electrode 23 and the second emitter electrode 24 are the electrodes of the second layer. This is an electrode (indicated by a dotted line in FIG. 3). As is clear from FIG. 3, the first collector electrodes 19 are scattered at regular intervals on the collector contact region 14.
The first emitter electrodes 20 are scattered at regular intervals between the portions of the ring-shaped emitter region 17 where the base region 16 is exposed. Also, the first collector electrode 19
and the first emitter electrode 20 are provided adjacently at the same interval. A base electrode 2 is provided on each base region 16 exposed in the center from the ring-shaped emitter region 17.
1 in ohmic contact and the first collector electrode 19
All the base regions 16 are connected by extending the gap between the first emitter electrodes 20 in a stripe shape in one direction on the first insulating film 18 . The second collector electrode 23 and the second emitter electrode 24 extend in a stripe shape in one direction on the second insulating film 22, and connect the first collector electrode 19 and the first emitter electrode 20 which are scattered. As a result, the base electrode 21, the second collector electrode 23, and the second emitter electrode 24 are connected to the second insulating film 22, as shown in FIG.
electrically insulated by Further, in terms of pattern design, it is desirable that the extending direction of the base electrode 21 and the extending directions of the second collector electrode 23 and the second emitter electrode 24 be perpendicular or nearly so.
本発明に依れば、ベース電極21と第2コレク
タ電極23および第2エミツタ電極24を延在方
向を交叉できるので、リング状のエミツタ領域1
7を均等の巾に形成できるのである。この結果リ
ング状のエミツタ領域17は全部が均一に且つ効
率良く働き、総合的には従来より以上に効果を高
め且つ働き方のアンバランスを除去できるのであ
る。 According to the present invention, since the base electrode 21, the second collector electrode 23, and the second emitter electrode 24 can cross in their extending directions, the ring-shaped emitter region 1
7 can be formed to have an even width. As a result, the ring-shaped emitter region 17 all works uniformly and efficiently, making it possible to improve the overall effect more than ever before and eliminate imbalances in the way it works.
更に本発明では第1エミツタ電極20との接続
を行う第2の絶縁膜22に設けるスルーホールの
大きさを調節することにより、第1エミツタ電極
20と第2エミツタ電極24間に直列に抵抗を形
成できる。そしてこの抵抗はエミツタ抵抗として
働き、パワートランジスタの安全動作領域を広げ
るバラスト抵抗の役割を果たせる。またスルーホ
ールの大きさによりエミツタ抵抗値を任意に選択
できる。 Furthermore, in the present invention, by adjusting the size of the through hole provided in the second insulating film 22 that connects with the first emitter electrode 20, a resistance can be created in series between the first emitter electrode 20 and the second emitter electrode 24. Can be formed. This resistor acts as an emitter resistor, and can play the role of a ballast resistor that expands the safe operating area of the power transistor. Furthermore, the emitter resistance value can be arbitrarily selected depending on the size of the through hole.
(ヘ) 発明の効果
本発明に依れば2層配線構造の採用によりリン
グ状のエミツタ領域17の巾を均等に形成でき、
パワートランジスタの効率を従来より向上でき
た。これにより従来より少ない面積でパワートラ
ンジスタを形成でき、集積回路の集積度を向上で
きる。(F) Effects of the Invention According to the present invention, by adopting a two-layer wiring structure, the width of the ring-shaped emitter region 17 can be formed uniformly,
The efficiency of power transistors has been improved compared to conventional ones. As a result, the power transistor can be formed in a smaller area than before, and the degree of integration of the integrated circuit can be improved.
またパワートランジスタのリング状のエミツタ
領域の働き方のアンバランスを除去でき、パワー
トランジスタの安全動作領域を拡大できる。更に
第2の絶縁膜22のスルーホールの形状の選択に
よりバラスト抵抗を組み込むことができ、パワー
トランジスタの安全動作領域をより拡大できる。 Furthermore, it is possible to eliminate the imbalance in the way the ring-shaped emitter region of the power transistor works, and to expand the safe operating area of the power transistor. Furthermore, by selecting the shape of the through hole in the second insulating film 22, a ballast resistor can be incorporated, and the safe operation area of the power transistor can be further expanded.
第1図は従来のリング状エミツタ領域を有する
パワートランジスタの上面図、第2図は第1図の
−線断面図、第3図は本発明のパワートラン
ジスタの上面図、第4図は第3図の−線断面
図、第5図は第3図の−線断面図である。
主な図番の説明11は半導体基板、12はエピ
タキシヤル層、14はコレクタコンタクト領域、
16はベース領域、17はリング状のエミツタ領
域、18は第1の絶縁膜、19は第1コレクタ電
極、20は第1エミツタ電極、21はベース電
極、22は第2の絶縁膜、23は第2コレクタ電
極、24は第2エミツタ電極である。
FIG. 1 is a top view of a conventional power transistor having a ring-shaped emitter region, FIG. 2 is a sectional view taken along the line -- in FIG. 1, FIG. 3 is a top view of the power transistor of the present invention, and FIG. FIG. 5 is a cross-sectional view taken along the line -- in FIG. 3. Description of main figure numbers 11 is a semiconductor substrate, 12 is an epitaxial layer, 14 is a collector contact region,
16 is a base region, 17 is a ring-shaped emitter region, 18 is a first insulating film, 19 is a first collector electrode, 20 is a first emitter electrode, 21 is a base electrode, 22 is a second insulating film, 23 is a The second collector electrode 24 is a second emitter electrode.
Claims (1)
逆導電型でコレクタ領域となるエピタキシヤル層
と、該エピタキシヤル層表面に設けた逆導電型の
コレクタコンタクト領域、および該コレクタコン
タクト領域に挟まれて延在する一導電型のベース
領域と、該ベース領域の表面に設けた、一定間隔
で前記ベース領域を露出する開口部を有し且つ前
記開口部でのエミツタ領域の幅が略等しくなるよ
うな逆導電型のリング状エミツタ領域と、前記エ
ピタキシヤル層の表面を被覆する第1の絶縁膜
と、前記ベース領域の開口部にオーミツク接触し
前記第1の絶縁膜上を延在するベース電極と、前
記コレクタコンタクト領域にオーミツク接触し前
記第1の絶縁膜上を延在する第1コレクタ電極
と、前記リング状エミツタ領域の開口部と開口部
とに挟まれたエミツタ領域にオーミツク接触し前
記第1の絶縁膜上を延在する第1のエミツタ電極
と、前記各電極を被覆する第2の絶縁膜と、前記
第2の絶縁膜上を延在し前記第1コレクタ電極を
連結する2層目の第2のコレクタ電極と、前記第
2の絶縁膜上を延在し前記第1エミツタ電極を連
結する2層目の第2エミツタ電極とを具備し、前
記ベース電極の延在方向と前記第2コレクタ電極
および第2エミツタ電極の延在方向をほぼ直交さ
せたことを特徴とするパワートランジスタ。1 A semiconductor substrate of one conductivity type, an epitaxial layer of the opposite conductivity type provided on the substrate and serving as a collector region, a collector contact region of the opposite conductivity type provided on the surface of the epitaxial layer, and a collector contact region of the opposite conductivity type provided on the surface of the epitaxial layer, and a collector contact region of the opposite conductivity type provided on the surface of the epitaxial layer. It has a base region of one conductivity type that extends between the base regions, and openings provided on the surface of the base region to expose the base regions at regular intervals, and the widths of the emitter regions at the openings are approximately equal. a ring-shaped emitter region of opposite conductivity type; a first insulating film covering the surface of the epitaxial layer; and an emitter region extending over the first insulating film in ohmic contact with the opening of the base region. A base electrode, a first collector electrode in ohmic contact with the collector contact region and extending over the first insulating film, and an ohmic contact with an emitter region sandwiched between openings of the ring-shaped emitter region. and a first emitter electrode extending over the first insulating film, a second insulating film covering each of the electrodes, and a second insulating film extending over the second insulating film connecting the first collector electrode. a second collector electrode in a second layer; a second emitter electrode in a second layer extending on the second insulating film and connecting the first emitter electrode; A power transistor characterized in that the direction and the extending direction of the second collector electrode and the second emitter electrode are substantially perpendicular to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58206178A JPS6098669A (en) | 1983-11-02 | 1983-11-02 | power transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58206178A JPS6098669A (en) | 1983-11-02 | 1983-11-02 | power transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6098669A JPS6098669A (en) | 1985-06-01 |
| JPH0348653B2 true JPH0348653B2 (en) | 1991-07-25 |
Family
ID=16519101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58206178A Granted JPS6098669A (en) | 1983-11-02 | 1983-11-02 | power transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6098669A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09155918A (en) * | 1995-12-07 | 1997-06-17 | Matsushita Electric Ind Co Ltd | Manufacturing method of resin-sealed electronic products |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5165585A (en) * | 1974-12-04 | 1976-06-07 | Hitachi Ltd | |
| JPS57197863A (en) * | 1982-04-12 | 1982-12-04 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1983
- 1983-11-02 JP JP58206178A patent/JPS6098669A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6098669A (en) | 1985-06-01 |
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