JPH0348658B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing a semiconductor device.

[Background technology]

In general, in semiconductor devices, it is desired that element formation regions be completely isolated from each other. Generally speaking, PN
A bonding method is used. However, although isolation of the PN junction in the element formation region is simple, there are problems such as leakage current and generation of parasitic elements. On the other hand, there is a method of insulating and isolating the element formation region using a hydrofluoric acid anodic reaction (hereinafter referred to as "fluoric acid anodic reaction"). This method
As shown in the figure, a silicon substrate 1 and a cathode electrode 2 are placed in a hydrofluoric acid solution 3, and the silicon substrate 1 is connected to the anode of a DC power source, and the cathode electrode 2 is connected to the cathode of a DC power source 4 to form an anode. This is done by passing a current between the cathodes. As a result, the portion of the silicon substrate 1 on the cathode electrode 2 side becomes porous silicon due to the reaction. Such a hydrofluoric acid anodization reaction is
It selectively acts only on the P-type portion of the silicon substrate 1 and does not act on the N-type portion. For example, if N-type regions are formed here and there on the surface of a silicon substrate, if a fluoric acid anodic reaction is performed with the surface where the N-type regions are formed facing the cathode electrode side, N-type regions will appear as shown in Figure 2. Except for the shaped region 5, the other portion on the cathode electrode side becomes a porous silicon portion 6. Next, when this is oxidized, the porous silicon portion 6 is
As shown in the figure, it is oxidized to form a silicon dioxide portion 7. Since this silicon dioxide portion 7 is an electrical insulator, the N-type region 5 is insulated and isolated by this silicon dioxide portion 7. However, when insulating and separating the N-type region 5 in this way, the porous silicon layer formed by the fluoric acid anodization reaction (see Figure 2) and the other parts have different density and coefficient of thermal expansion. Because of this difference, distortion is likely to occur in the substrate 1 when oxidizing it to convert the porous silicon portion 6 into silicon dioxide. Also, a silicon dioxide portion 7 formed by oxidizing the porous silicon portion 6
Since the density and coefficient of thermal expansion of the and other parts are also different, this will have an adverse effect on photo-etching in the subsequent process, and will also have an adverse effect on the elements formed using it. This was a problem.

[Purpose of the invention]

The object of the present invention is to insulate and isolate N-type regions without causing distortion to a silicon substrate.

[Disclosure of the invention]

This invention prepares a P-type silicon substrate in which N-type regions are formed here and there on both sides of the substrate, and performs a hydrofluoric acid anodic reaction on both sides of the P-type silicon substrate to form a P-type silicon substrate. By forming porous silicon from both sides to a depth exceeding the formation depth of the N-type region, and then performing oxidation treatment to convert the porous silicon portion into silicon dioxide,
1. A semiconductor device characterized by obtaining a semiconductor device in which a type region is insulated and isolated, an insulating layer of silicon dioxide is formed on both sides of a P-type silicon substrate, and an N-type region is insulated and isolated by the insulating layer. The gist is the manufacturing method.

That is, the present invention does not form a porous silicon part on one side of a P-type silicon substrate and use it as a silicon dioxide layer, but forms a porous silicon part on both sides to make a silicon dioxide layer. This cancels out the strain on the silicon substrate, making it possible to isolate the N-type region without causing strain on the silicon substrate.

Next, the present invention will be explained in detail based on examples.

FIG. 4 is a block diagram of a P-type silicon substrate used in the present invention. That is, this P-type silicon substrate 10 has an N-type buried layer 11 (formed using epitaxial growth) formed therein. The formation position of this N-type buried layer 11 is determined between N-type regions formed in a subsequent step and on both sides of a connection path formed inside the silicon substrate. Next, as shown in FIG. 5, N
N-type regions 12 are formed by performing type diffusion. This N-type region 12 corresponds to the N-type buried layer 11 formed inside the P-type silicon substrate 10 as described above.
and another N-type buried layer 11. Then, a silicon nitride film 14 is formed on the surface of this N-type region 12 and on the front and back surfaces of a portion 13 that will become a connection path inside the silicon substrate 10. Next, as shown in FIG. 6, this silicon substrate 10 is placed in a container 16 containing a hydrofluoric acid solution 15, and electrodes 17 are placed on both sides thereof. 17a
is an O-ring. In this case, the silicon substrate 10
Both surfaces serve as anodes, and electrode 17 serves as a cathode. By passing a current between the silicon substrate 10 and the electrode 17, the front and back layers of the silicon substrate 10 become porous silicon portions. This is shown in FIG. In FIG. 7, the shaded area 18 is the porous silicon portion, and 13 is the P remaining as a connection path.
shaped part, 19 is an N-type buried layer 11 and an N-type buried layer 11
This is the P-type portion which is the portion in between and remains without being made into porous silicon. Next, after removing the silicon nitride film 14, thermal oxidation is performed to convert the porous siliconized portion 18 into a silicon dioxide portion 18', as shown in FIG. As a result, the N-type region 12 is insulated and isolated by the insulating silicon dioxide portion 18', and the connection path 13 consisting of the P-type portion is also insulated and isolated by the silicon dioxide portion 18'.

As described above, according to this embodiment, silicon dioxide portions 18' are formed on both sides of the silicon substrate 10,
As a result, the N-type region 12 is insulated and isolated, so that the distortion of the silicon substrate 10 is canceled out and no distortion occurs. Furthermore, since the N-type region 12, which is to be used as an element formation portion, is provided not only on one side but also on both sides of the silicon substrate 10, the effect of improving the degree of integration can also be obtained.
Furthermore, if anodization is performed with the N-type buried layer 11 provided inside the P-type silicon substrate 10 as described above, the porous siliconization will only reach the N-type buried layer 11. This results in the formation of a shallow silicon dioxide layer, which allows a large area of N to be formed in the shallow silicon dioxide layer.
This makes it possible to insulate and separate the shaped regions 12. Furthermore, as described above, when the N-type regions 12 that serve as element formation parts are formed on both sides, electrical connections between the front and back surfaces become a problem, but according to this embodiment, there is a connection path inside the substrate. Because it forms 13,
External connections are not required and packaging density can be increased.

FIG. 9 is a block diagram of a semiconductor device obtained according to another embodiment of the present invention. In the figure, A is the MOS transistor part, B is the solar cell part, and C is the solar cell part.
is the wiring part. That is, in this semiconductor device, a MOS type transistor A is formed on one side of a silicon substrate 10 using an N-type region 12 insulated and isolated by a silicon dioxide portion 18', and a silicon dioxide portion is formed on the other side. N isolated by 18'
A solar cell B is formed using the shaped region 12. 30 is the P layer of the MOS transistor A, 31 is the N layer, 32 is the gate electrode, 33 is the drain electrode,
34 is a source electrode. Further, in solar cell B, 35 is a P layer, 36 is a cathode electrode, and 37 is an anode electrode. Further, in the wiring portion C, 38 is an electrode for wiring. 39 is a SiO ₂ film. The other parts are substantially the same as the semiconductor device shown in FIG. In this way, in this semiconductor device, one side of the substrate 10 can be formed as a photodetection section, and the other side can be formed as a logic circuit or an output circuit, so that it is possible to realize a semiconductor device with a small area and high density. Also, the board 10
Since connections between the front and back surfaces of the device are made through internal connection paths, external wiring is not required and the packaging density can be improved. Particularly in this case, since insulation is completely performed by silicon dioxide, the characteristics as designed can be obtained without the generation of parasitic elements or the influence of leakage elements.

〔Effect of the invention〕

As described above, the present invention prepares a P-type silicon substrate in which N-type regions are formed here and there on both sides of the substrate, and performs a fluoric acid anodic reaction on both sides of the P-type silicon substrate to form a P-type silicon substrate. The silicon substrate is made into porous silicon from both sides to a depth exceeding the formation depth of the N-type region, and then an oxidation treatment is performed to convert the porous silicon portion into silicon dioxide, thereby insulating and separating the N-type region, and forming a P-type silicon substrate. In order to obtain a semiconductor device in which an insulating layer of silicon dioxide is formed on both sides of the N-type region and the N-type region is insulated and isolated by the insulating layer, the N-type region that is the element forming part is removed without causing distortion in the substrate. It becomes possible to isolate regions. Furthermore, since N-type regions are formed on both sides of the substrate and can be used as element forming portions, a high degree of integration can be achieved.

[Brief explanation of drawings]

1 to 3 are explanatory diagrams of a conventional example, FIGS. 4 to 8 are explanatory diagrams of an embodiment of the present invention, and FIG. 9 is a configuration of a semiconductor device obtained by another embodiment. It is a diagram. 10...Silicon substrate, 11...N-type buried layer,
12... N-type area, 13... Connection path, 18'...
Silicon dioxide section.

Claims (1)

[Claims] 1. A P-type silicon substrate in which N-type regions are formed here and there on both sides of the substrate is prepared, and a hydrofluoric acid anodic reaction is performed on both sides of the P-type silicon substrate to form P-type regions. The silicon substrate is made into porous silicon from both sides to a depth exceeding the formation depth of the N-type region, and then an oxidation treatment is performed to convert the porous silicon portion into silicon dioxide, thereby insulating and separating the N-type region, and forming a P-type silicon substrate. 1. A method for manufacturing a semiconductor device, comprising obtaining a semiconductor device in which an insulating layer of silicon dioxide is formed on both surfaces of the semiconductor device, and an N-type region is insulated and isolated by the insulating layer. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the formation depth of the porous silicon portion is controlled by forming an N-type buried layer in advance in a P-type silicon substrate. 3 Perform a hydrofluoric acid anodic reaction with a predetermined part of the front surface of the P-type silicon substrate and a corresponding part of the back surface masked, and leave the masked part as a P-type region from the front surface to the back surface. Claim 1 can be used as an electrical connection path.
A method for manufacturing a semiconductor device according to item 1 or 2.