JPH0348684B2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field The present invention is used in color TV receivers, etc.
This invention relates to a peak hold circuit suitable for

(B) Prior Art Generally, when forming a capacitor in an IC, the capacitance value is limited to several tens of PF or less due to IC manufacturing considerations. For this reason, conventionally, the hold capacitor used in peak hold circuits such as ACC circuits (automatic chroma control circuits) has been attached externally to the IC, as shown in Japanese Patent Publication No. 57-14072 (H04N9/46). Although this is a common method, a method as shown in FIG. 3 can be considered in order to form the above-mentioned hold capacitor inside an IC. In the figure, 1 is a well-known ACC detection circuit that is composed of a double-balanced differential amplifier and demodulates color bursts, Q ₁ is a first transistor that is turned on only during the burst period by the output of this detection, and C ₁ is this first transistor. This is a hold capacitor connected between the emitter of the color burst and the ground, and is charged to the peak value of the color burst during the burst period. Q ₂ to Q ₄ are Darlington-connected second to fourth transistors, Q ₅ is a fifth transistor connected to the emitter of the fourth transistor Q ₄ and serves as a constant current source, and 2 is the fourth transistor Q ₄
This is a variable gain control type ACC amplifier whose emitter output is supplied as a control signal.

In the peak hold circuit described above, the second to fourth
Since the input impedance of transistors Q ₂ to _{Q 4} can be increased by Darlington connection, the load on the capacitor C ₁ can be lightened, and the capacitance value of this capacitor can be reduced to several tens of PF or less. It becomes possible to do so.

However, the above circuit still has the following drawbacks even if the input impedance of the second to fourth transistors _Q2 to _Q4 is increased.

That is, the first transistor Q ₁ operates during the burst period t ₀ ~
t ₁ , the capacitor C ₁ is charged with a charge Q _H by the voltage V ₀ during that time, and the first transistor
After t ₁ when Q ₁ turns off, the capacitor has the above charge.
Try to hold Q _H. Here, since a transistor generally has a base-emitter capacitance Cs ₀ and a collector-base capacitance Cs ₁ , the first transistor Q ₁ is in an off state, and one end of the base-emitter capacitance Cs ₀ of this transistor exists. (base side) is at ground potential, the charge Q _H is as follows
The base-emitter capacitance Cs is divided into ₀ so as to satisfy equation (1).

Q _H = C ₁・V ₀ = (C ₁ + Cs ₀ )・(V ₀ −△V)…(1) From the above formula, △V is △V=Cs ₀ /C ₁ +Cs ₀・V ₀ …(2) As shown in FIG. 4, this ΔV appears as a drop in the voltage held in the capacitor _C1 after _t1 , and this becomes a ripple.

Here, the capacitor is external to the IC,
When the capacitance value is relatively large, C ₁ ≫ Cs ₀ ...(3), and the ripple △V hardly occurs, but when the capacitor is made into an IC and has a small capacity of several tens of PF or less, the ripple △V becomes large. Therefore, accurate peak hold operation will be hindered.

(c) Problems to be solved by the invention The present invention has been made in view of the above points,
The present invention provides a peak hold circuit in which ripples do not appear in the voltage held by a hold capacitor even if the hold capacitor is formed within an IC.

(d) Means for Solving Problems The peak hold circuit of the present invention is constructed by connecting the collector of a switching transistor to one end of a holding capacitor.

(e) Effect: The above-described means works to prevent the holding voltage of the hold capacitor from dropping significantly when the switching transistor is turned off.

(f) Embodiment An embodiment in which the present invention is applied to an ACC circuit will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of the circuit of this embodiment, and the same parts as in FIG. 3 are given the same reference numerals and their explanation will be omitted.

The first feature of this embodiment is the hold capacitor
The sixth transistor _Q6 that drives _C1 has its emitter connected to the DC power supply and its collector connected to the capacitor _C1 .

Therefore, the sixth transistor _Q6 functions as a constant current type drive circuit for the hold capacitor _C1 . Moreover, the second feature is that the second to fourth transistors Q ₂ to Q ₄ forming a three-stage Darlington connection
The seventh transistor is connected to the emitter of the second transistor in the first stage.
This is the point where the collector of transistor _Q7 is connected. The base of the seventh transistor _Q7 is grounded together with the collector via the resistor _R1 .
It is always off. In addition, the first to seventh transistors Q ₁ to _{Q 7} , the hold capacitor C ₁ and the resistor
All _R1s are formed within the same IC.

Next, the operation of the above circuit will be explained.

The sixth transistor Q ₆ is connected during the burst period t ₀ to _{t 1}
Turns on by low output from ACC detection circuit 1,
Hold capacitor C ₁ is charged by voltage V ₀ . Here, the sixth transistor Q ₆ has a base-emitter capacitance Cs ₀ and a collector-base capacitance Cs ₁ , and the charge Q _H to be held in the capacitor C ₁ when the sixth transistor is off is the collector-emitter capacitor Cs 0. Divided into base-to-base capacity, but generally
Since Cs ₁ <<Cs ₀ , as shown in FIG. 2, there is almost no drop in the voltage V ₀ held in the capacitor C ₁ and no ripple occurs.

Further, a cut-off current I _CER is constantly flowing through the collector of the seventh transistor Q ₇ connected to the emitter of the second transistor Q ₂ in the first stage of the Darlington connection.

Therefore, the current _IF flowing through the fourth transistor Q ₄ in the final stage is IF = [(I _CER1 − I _CER4 ) × β ₂ + I _CER2 ] × β ₃ + I _CER3 , where β ₁ to β ₃ are the second to The current amplification rate of the fourth transistor, I _CER1 to I _CER3 are the collector currents of the second to fourth transistors, and I _CER4 is the collector current of the seventh transistor.

Since I _CER1 ≒ I _CER4 and I _CER2・β ₃ ≫I _CER3 , IF≒I _CER2 ×β ₂ .

That is, in this embodiment circuit, the second transistor
Since I _CER1 of Q ₂ is canceled by I _CER4 of the seventh transistor Q ₇ , the IF is equivalent to that of two stages even though the Darlington connection has three stages. When calculated using specific values, IF≒0.01μA×300=3μA, and there is almost no increase in the output potential of the fourth transistor _Q4 due to collector current disconnection. Therefore, the current _I0 flowing through the fifth transistor _Q5 may be smaller than that in the conventional example shown in FIG.

Note that the emitter of the third transistor _Q3 also has a seventh
If a transistor similar to transistor _Q7 is connected, IF≒I _CER3 can be established, and IF can be further reduced.

In this embodiment, the base of the sixth transistor _Q6 is connected to the ACC detection circuit 1, but it is also possible to connect the detection circuit 1 to the emitter and the DC power supply to the base.In short, the collector is used for holding. It is sufficient if it is a constant current drive type connected to one end of capacitor _C1 .

(g) Effects of the invention As described above, according to the present invention, even if a hold capacitor can be formed within an IC with a capacitance of several tens of PF, no ripple will appear in the holding voltage of this capacitor, so this capacitor can be formed within an IC. The number of terminals for external IC elements can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a peak hold circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing the holding voltage of the hold capacitor in FIG. 1, and FIG. 3 is a circuit diagram of a conventional peak hold circuit. FIG. 4 is a diagram showing the holding voltage of the hold capacitor shown in FIG. 3. _Q1 to _Q7 ...1st to 7th transistors, _C1 ...hold capacitor.

Claims (1)

[Claims] 1. A signal source, a switching transistor whose input electrode is connected to the signal source, and a switching transistor connected between the output electrode of the switching transistor and a potential point and configured in an integrated circuit. It consists of a hold capacitor and an output terminal connected to a connection point between the hold capacitor and the output electrode, and during a first period when the switching transistor is turned on, a signal is charged to the hold capacitor and the hold capacitor is charged. In the peak hold circuit in which the charge charged in the holding capacitor is held during a second period when the switching transistor is turned off, the switching transistor is of a PNP type and its collector is used as an output electrode. peak hold circuit.