JPH0322085B2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field The present invention is used in color TV receivers, etc.
This invention relates to transistor circuits suitable for

(B) Prior Art Generally, when forming a capacitor in an IC, the capacitance value is limited to several tens of PF or less due to IC manufacturing considerations. For this reason, conventionally, the hold capacitor used in peak hold circuits such as ACC circuits (automatic chroma control circuits) has been attached externally to the IC, as shown in Japanese Patent Publication No. 57-14072 (H04N9/46). Although this is a common method, a method as shown in FIG. 3 can be considered in order to form the above-mentioned hold capacitor inside an IC. In the figure, 1 is a well-known ACC detection circuit which is composed of a double-balanced differential amplifier and demodulates color bursts, Q1 is a first transistor that is turned on only during the burst period by the output of this detection, and C1 is this first transistor. This is a hold capacitor connected between the emitter of the color burst and the ground, and is charged to the peak value of the color burst during the burst period. Q2 to Q4 are the second to fourth transistors connected in Darlington, and Q5 is the fourth transistor.
A fifth transistor 2 serving as a constant current source connected to the emitter of the transistor Q4 is a variable gain control type ACC amplifier to which the emitter output of the fourth transistor Q4 is supplied as a control signal.

In the peak hold circuit described above, the second to fourth
Since the input impedance of the transistors Q2 to Q4 can be increased by Darlington connection, the load on the capacitor C1 can be lightened, and the capacitance value of this capacitor can therefore be reduced to several tens of PF or less. It becomes possible.

However, the above circuit has the following drawbacks.

In other words, the collector current I ^CER (current between the collector and emitter when the base and emitter are short-circuited with a resistor) of the first-stage transistor connected to Darlington is amplified by the second-stage transistor, so the first-stage transistor is off. Also, more current than necessary flows through the final stage transistor.

Therefore, in Fig. 3, if the current flowing through the fourth transistor Q4 in the final stage is IF, then IF = (I ^CER1 × B2 + I ^CER2 × B3 + I ^CER3 I ^CER1・B2＞＞I ^CER2 , I ^CER1 · B2 · B3＞ > I ^CER3 , so IF≒I ^CER1 ×B2+B3 Here, B1 to B3 are the current amplification rates of the second to fourth transistors, and I ^CER1 to I ^CER3 are the collector currents and disconnection currents of the second to fourth transistors. When calculating the IF by inserting specific values into the above formula, it becomes IF≒0.01μA×300×300=0.9mA.

Therefore, if the current I0 of the fifth transistor Q5 for constant current source is I0>>IF, the fourth transistor Q
The output potential of No. 4 hardly rises, but otherwise the output potential rises and normal operation cannot be performed.

Therefore, in order to suppress the rise in the output potential, it is necessary to allow a reactive current of approximately 1 mA to flow through the fifth transistor Q5, leading to an increase in power consumption.

(c) Problems to be Solved by the Invention The present invention has been devised in view of the above-mentioned points, and in order to prevent malfunctions caused by the collector of the Darlington-connected transistor or disconnection, a transistor connected to the final stage transistor is used. The present invention provides a transistor circuit that does not require an extra reactive current to flow through a constant current source.

(d) Means for Solving the Problems The present invention provides a plurality of Darlington-connected transistors, a plurality of Darlington-connected transistors connected to the emitter of one of the plurality of Darlington-connected transistors, and a collector of the Darlington-connected transistor and a disconnection current. The second transistor has a collector whose collector is approximately equal to that of , and a second transistor through which a cut-off current flows.

(E) Effect The present invention cancels out the collector current of the Darlington connected transistor by flowing it between the collector and emitter of the second transistor by the above-described means.

(f) Embodiment An embodiment in which the present invention is applied to an ACC circuit will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of the circuit of this embodiment, and the same parts as in FIG. 3 are given the same reference numerals and their explanation will be omitted.

The first feature of this embodiment is that the sixth transistor Q6 that drives the hold capacitor C1 has its emitter connected to the DC power supply and its collector connected to the capacitor C1.

Therefore, the sixth transistor Q6 functions as a constant current drive circuit for the hold capacitor C1. In addition, the second feature is that the second to fourth transistors Q2 to constitute the third stage Darlington connection.
The point is that the collector of the seventh transistor Q7 is connected to the emitter of the second transistor in the first stage of Q4. The base of the seventh transistor Q7 is grounded together with the collector via the resistor R1, and is always off. In addition, the first to seventh transistors Q1 to Q7 and the hold capacitor C1
All resistors R1 are formed within the same IC.

Next, the operation of the above circuit will be explained.

The sixth transistor Q6 is connected to the burst period t ₀ to _{t 1} ).
is turned on by low output from ACC detection circuit 1,
Hold capacitor C1 is charged with voltage _V0 . Here, the sixth transistor Q6 has a base-emitter capacitance (Cs0) and a collector-base capacitance (Cs1), and the charge that should be held in the capacitor C1 when the sixth transistor is off.
Q _H is divided into the collector-base capacitance, but generally Cs1<<Cs0, so as shown in Figure 2, the voltage held in capacitor C1 (V0)
There is almost no drop in the voltage and no ripples occur.

Furthermore, a cut-off current I ^CER is constantly flowing through the collector of the seventh transistor Q7 connected to the emitter of the second transistor Q2 in the first stage of the Darlington connection.

Therefore, the current IF flowing through the fourth transistor Q4 in the final stage is IF = [(I ^CER1 - I ^CER4 ) x B2 + I ^CER2 ] x B3 + I ^CER3 , where B1 to B3 are the current amplification factors of the second to fourth transistors. , ^ICER1 to ^ICER3 are the collector currents of the second to fourth transistors, and ^ICER4 is the collector current of the seventh transistor.

Since I ^CER1 ≒ I ^CER4 and I ^CER2・B3 ≓ ^{I CER3,} IF≒I ^CER2 ×B2.

That is, in this embodiment circuit, the second transistor Q
Since the I ^CER1 of the second transistor Q7 is canceled out by the I ^CER4 of the seventh transistor Q7, the IF is equivalent to that of two stages even though the Darlington connection has three stages. When calculated using specific values, it becomes IF≒0.01μA×300=3μA, and there is almost no increase in the output potential of the fourth transistor Q4 due to collector current disconnection. Therefore, the current I0 flowing through the fifth transistor Q5 may be smaller than that in the conventional example shown in FIG.

Note that the emitter of the third transistor Q3 also has a seventh transistor.
If a transistor similar to transistor Q7 is connected, IF≈I ^CER3 can be established, and IF can be further reduced.

Furthermore, although this embodiment uses the present invention in a peak hold circuit of an ACC circuit, it is clear that the present invention can be applied to any other transistor circuit using a Darlington connection.

Further, the collector current flowing through the seventh transistor Q7 may be I ^CE0 or I ^CES in addition to I ^CER . That is, the base of the seventh transistor Q7 may be open, or the base and emitter may be short-circuited.

(G) Effects of the Invention As described above, according to the present invention, since the collector current I ^CER of the Darlington-connected transistor can be canceled out without being transmitted to the next stage, the constant current source of the final stage transistor can be canceled out. Power consumption can be reduced without the need to flow extra reactive current.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a peak hold circuit according to an embodiment of the present invention, Figure 2 is a diagram showing the holding voltage of the hold capacitor in Figure 1, and Figure 3 is a circuit diagram of a conventional peak hold circuit. . Q2 to Q4... second to fourth transistors (Darlington connection transistors), Q7... seventh transistor (second transistor).

Claims (1)

[Scope of Claims] 1. A plurality of Darlington-connected transistors, and a collector terminal connected to the emitter of one of the plurality of Darlington-connected transistors and having a collector current substantially equal to the collector current of the Darlington-connected transistor. and a second transistor through which a disconnection current flows, and the transistor circuit is characterized in that the disconnection current flows between the collector of the Darlington connection transistor and between the collector and emitter of the second transistor. 2. The transistor circuit according to claim 1, wherein a plurality of said second transistors are connected to an emitter of one of said Darlington connected transistors.