JPH0348706B2 - - Google Patents

Description

[Detailed description of the invention]

(1) Technical Field of the Invention The present invention relates to a parallel transmission method for dividing one data frame and transmitting the divided data frames in parallel between terminals via a plurality of transmission paths. (2) Technology background Current digital networks use a frequency band of 4 kHz (transmission rate of 64 kbits/
s) is the standard. In such a network, 64 kbit/s data frames are transmitted between terminals via one transmission path. In this case, one or more switching stations exist on the transmission path between the terminals. By the way, in the near future, it is conceivable that large amounts of information such as image signals, for example, information with a frequency band of 4 MHz (transmission speed 100 Mbit/s) will be transmitted using the low-speed transmission path of the digital network mentioned above. , it is necessary to use multiple transmission paths. That is, it is necessary to divide one data frame into a plurality of parts and transmit them in parallel through each transmission path. In the parallel transmission described above, the largest delay is due to the switching center in the middle of the transmission path. Therefore, in parallel transmission of data frames from one terminal to another, it is necessary to compensate for these delays and synchronize the data frames. One possible method for this is to compensate for delays at each receiving terminal all at once, but in this case there is a problem that the burden on each terminal increases and therefore the manufacturing cost increases. (3) Purpose of the Invention The purpose of the present invention is based on the concept of compensating the delay due to the switching station located in the middle of each transmission path at the switching station immediately before the receiving terminal, and compensating only the final small delay error at the receiving terminal. The object of the present invention is to reduce the burden on each terminal, thereby reducing manufacturing costs, and solving the above-mentioned problems. (4) Structure of the invention In order to achieve the above-mentioned object, according to the present invention,
In a parallel transmission method in which a single data frame is divided and transmitted in parallel from a transmitting terminal to a receiving terminal via multiple transmission paths using a network in which multiple exchanges are connected via transmission paths, the divided data is A station number information section is provided for each frame, and the station number information section data of the data frame is counted up or down at an intermediate switching station of each transmission route, and the station number information section data of the data frame is counted up or down at a common final switching station of each transmission route. The data frames are synchronized by delaying each divided data frame by a delay time based on information part data and compensating for delay errors of each divided data frame at the receiving terminal. A parallel transmission method featuring features is provided. (6) Examples of the invention Examples of the invention will be described below with reference to the drawings.
FIG. 1 is a schematic diagram showing a parallel transmission system as an embodiment of the present invention. In FIG. 1, 1 is a transmitting terminal and 2 is a receiving terminal. Reference numerals 3 to 7 are switching offices, and each switching office is connected by a plurality of low-speed transmission lines. Assuming that transmitting terminal 1 transmits a high-speed data frame to receiving terminal 2 by dividing it into three parts,
First, a transmission path is set. For example, as shown in the figure, three transmission paths are set: A: 3→4→5→7, B: 3→4→6→5→7, and C: 3→6→7. When the transmission paths are different in this way, the delay time (transmission time) is different. This delay time mainly depends on the number of exchanges. According to the present invention, a station number information section of several bits is provided in each divided data frame, and each time each data frame passes through an exchange, the number of exchanges is counted and the counted value is stored in the station number information section. I am writing. FIG. 2 is a block circuit diagram corresponding to an input/output pair of a device for counting the number of exchanges through which a data frame passes in each exchange shown in FIG. In addition,
In FIG. 1, the number of input lines and the number of output lines in each exchange are the same, and there is a one-to-one correspondence, and FIG. 2 shows the equipment circuit for this input/output pair. The data frame is supplied to a delay circuit (generally representing various functions) 21, and a detection circuit 22 detects the station number information part of the data frame. This detected value is calculated by +1 by the adder circuit 23. Next, control circuit 2
5 operates the selection circuit 24 to write the calculation result of the addition circuit 23 to the position of the station number information part of the data frame. This causes the number of exchanges to be counted up. Therefore, at the exchange 7 in FIG.
The values of the station number information section for the data frames that transmitted B and C are "4", "5", and "3", respectively.
becomes. Next, in this exchange 7, delay time compensation is performed according to the number of stations "4", "5", and "3". FIG. 3 is a circuit diagram of a device for compensating the delay time of a data frame at the exchange 7 of FIG. 1 in accordance with the number of exchanges through which the data frame has passed. In FIG. 3, each data frame is supplied to a station number information detection circuit 31 for reading out the value of its station number information section. The control circuit 37 is the detection circuit 3
The selection circuits 32 and 36 are operated according to the detected value of 1, so that the data frame passes through any one of the delay circuits 33, 34, and 35 having different delay times. As a result, the delay time is compensated according to the number of exchanges. Note that the number of delay circuits is set according to the possible number of switching stations. At the receiving terminal 2, delay errors in each data frame are compensated. This delay error is smaller than the delay error due to the number of exchanges passed through. FIG. 4 is a block circuit diagram of a device for compensating for delay errors in each data frame at the receiving terminal 2 of FIG. In FIG. 4, each data frame, in this case each of the three divided data frames, is stored in memories 41, 42, and 43, respectively. At this time, the arrival time of each data frame is detected by the delay detection circuit 44, and based on this detection, the delay control circuit 45
Controls data transmission timing of 1, 42, and 43. As a result, the data frames sent out from the memories 41, 42, and 43 are synchronized. Note that in the above embodiment, terminals 1 and 2 are specified as the transmitting terminal and receiving terminal, and the exchange 7 is specified as the final station, but these are all specified for convenience. 2 are equivalent, and exchanges 3 to 7 are also equivalent. In the above description, the value of the station number information part of the data frame is counted up, but a fixed value may be given in advance and counted down. (7) Effects of the Invention As explained above, according to the present invention, delay time compensation is performed at the first stage at the final exchange and at the second stage at the receiving terminal. Since the stage compensation function is common to a plurality of terminals connected to the last exchange, the load on the terminals can be reduced, and therefore the manufacturing cost can be reduced.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing a parallel transmission system as an embodiment of the present invention, and FIG. 2 is a block diagram for an input/output pair of a device for counting the number of exchanges that a data frame passes through in the exchange shown in FIG. 3 is a circuit diagram of a device for compensating the delay time of a data frame at the exchange 7 in FIG. 1 according to the number of exchanges through which the data frame has passed; FIG. 1 is a block circuit diagram of a device for compensating for delay errors in each data frame at a receiving terminal 2 of FIG. 1: Transmitting terminal station, 2: Receiving terminal station, 3 to 7: Switching station, A, B, C: Transmission line.

Claims (1)

[Claims] 1. In a parallel transmission method for dividing one data frame and transmitting it in parallel from a transmitting terminal to a receiving terminal via multiple transmission paths using a network in which multiple exchanges are connected via transmission paths, the divided A station number information section is provided for each data frame, and the station number information section data of the data frame is counted up or down at an intermediate switching station of each transmission path, and at a common final switching station of each transmission path, the station number information section is The data frames are synchronized by delaying each divided data frame by a delay time based on the number information part data and compensating for delay errors of each divided data frame at the receiving terminal. A parallel transmission method featuring: