JPH0349211B2 - - Google Patents
Info
- Publication number
- JPH0349211B2 JPH0349211B2 JP58035883A JP3588383A JPH0349211B2 JP H0349211 B2 JPH0349211 B2 JP H0349211B2 JP 58035883 A JP58035883 A JP 58035883A JP 3588383 A JP3588383 A JP 3588383A JP H0349211 B2 JPH0349211 B2 JP H0349211B2
- Authority
- JP
- Japan
- Prior art keywords
- fet
- gate width
- fets
- fet1
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 3
- 101150015217 FET4 gene Proteins 0.000 description 2
- 101150079361 fet5 gene Proteins 0.000 description 2
- 101100383179 Arabidopsis thaliana CDS5 gene Proteins 0.000 description 1
- 101000980996 Arabidopsis thaliana Phosphatidate cytidylyltransferase 3 Proteins 0.000 description 1
- 101000623713 Homo sapiens Motile sperm domain-containing protein 3 Proteins 0.000 description 1
- 102100023091 Motile sperm domain-containing protein 3 Human genes 0.000 description 1
- 102100033118 Phosphatidate cytidylyltransferase 1 Human genes 0.000 description 1
- 101710178747 Phosphatidate cytidylyltransferase 1 Proteins 0.000 description 1
- 102100033126 Phosphatidate cytidylyltransferase 2 Human genes 0.000 description 1
- 101710178746 Phosphatidate cytidylyltransferase 2 Proteins 0.000 description 1
- 101150058910 RDS1 gene Proteins 0.000 description 1
- 101100219167 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) BUL1 gene Proteins 0.000 description 1
- 101100140267 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RDS2 gene Proteins 0.000 description 1
- 101150070760 cgs1 gene Proteins 0.000 description 1
- 101150008586 cgs2 gene Proteins 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6874—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor in a symmetrical configuration
Landscapes
- Junction Field-Effect Transistors (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、FETスイツチにおいて広帯域化を
図つた広帯域FETスイツチに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a wideband FET switch that achieves a wideband FET switch.
第１図は、従来から用いられているFETスイ
ツチ回路で、スイツチ回路SWとバツフア回路に
より構成されている。
FIG. 1 shows a conventionally used FET switch circuit, which is composed of a switch circuit SW and a buffer circuit.
このスイツチ回路SWは、直列に接続した２つ
FET１，FET２と、FET１，FET２の接続点と
アース間に接続されたFET３により構成されて
いる。 This switch circuit SW consists of two connected in series.
It is composed of FET1, FET2, and FET3 connected between the connection point of FET1 and FET2 and the ground.
又バツフア回路BUFはFET４，FET５のソー
スフオロア回路により構成されている。 Further, the buffer circuit BUF is constituted by a source follower circuit of FET4 and FET5.
動作について説明すると、入力端子INから入
力信号が入力し、端子Ｔ１，Ｔ２に夫々逆相のコ
ントロール信号が入力する。 To explain the operation, an input signal is input from the input terminal IN, and control signals of opposite phases are input to the terminals T1 and T2, respectively.
つまり、入力信号を通す時には、端子Ｔ１にハ
イレベルのコントロール信号を、端子Ｔ２にはロ
ーレベルのコントロール信号を入力し、FET１，
FET２をオンとし、FET３をオフとする。これ
により入力信号がFET１，FET２を介してバツ
フア回路BUFに入力する。一方信号を遮断する
ときには、端子Ｔ１，Ｔ２に上記とは逆のレベル
のコントロール信号を入力し、FET１，FET２
をオフ、FET３をオンとする。 In other words, when passing an input signal, a high level control signal is input to terminal T1, a low level control signal is input to terminal T2, and FET1,
Turn on FET2 and turn off FET3. As a result, the input signal is input to the buffer circuit BUF via FET1 and FET2. On the other hand, when cutting off the signal, input a control signal of the opposite level to the above to terminals T1 and T2, and FET1 and FET2
is off and FET3 is on.
ところで、バツフア回路は通過損失の低減、外
部回路との接続を容易にするため、入力インピー
ダンスの高いFETを用いているが、このFETの
ゲートソース間の容量CGSの影響により、帯域
か劣化するという欠点がある。このことを、第２
図の等化回路を用いて説明する。 By the way, buffer circuits use FETs with high input impedance in order to reduce passing loss and facilitate connection with external circuits, but it is said that the bandwidth deteriorates due to the influence of the capacitance CGS between the gate and source of this FET. There are drawbacks. This is the second
This will be explained using the equalization circuit shown in the figure.
第２図は、第１図のスイツチ回路の等化回路で
ある。 FIG. 2 shows an equalization circuit for the switch circuit shown in FIG.
図において、RDS１はFET１のチヤネル抵抗、
CDS１はFET１のドレイン−ソース間の容量、
CGS１はFET１のゲート−ソース間の容量、
RDS２はFET２のチヤネル抵抗、CDS２はFET
２のドレイン−ソース間の容量、CGS２はFET
２のゲート−ソース間の容量、CDS３はFET３
のドレイン−ソース間の容量、CGS４はFET４
のゲート−ソース間の容量、CDS５はFET５の
ドレイン−ソース間の容量、gmは相互コンダク
タンスである。これらのFETの容量及びコンダ
クタンスの値は、スイツチ回路を構成するFET
のゲート幅WG１又はバツフア回路を構成する
FETのゲート幅WG２に比例したものである。 In the figure, RDS1 is the channel resistance of FET1,
CDS1 is the capacitance between the drain and source of FET1,
CGS1 is the capacitance between the gate and source of FET1,
RDS2 is the channel resistance of FET2, CDS2 is FET
2 drain-source capacitance, CGS2 is FET
2 gate-source capacitance, CDS3 is FET3
The drain-source capacitance of , CGS4 is FET4
, CDS5 is the capacitance between the drain and source of FET5, and gm is the mutual conductance. The capacitance and conductance values of these FETs are the same as those of the FETs that make up the switch circuit.
Configure the gate width WG1 or buffer circuit.
It is proportional to the FET gate width WG2.
図にて示されるような回路構成において、
FET１とFET３で決まる入力側の帯域と、FET
２とFET４で決まる出力側の帯域が異なつた場
合、帯域の狭い一方の帯域が回路全体の帯域とし
て決まつてしまう。即ち、帯域の狭い一方の帯域
がその回路の帯域として支配的になつてしまい、
回路全体の帯域が狭くなつてしまう。 In the circuit configuration shown in the figure,
Input side band determined by FET1 and FET3 and FET
If the output side bands determined by FET 2 and FET 4 are different, one of the narrower bands will be determined as the band of the entire circuit. In other words, one of the narrow bands becomes dominant as the band of the circuit,
The band of the entire circuit becomes narrower.
本発明はこのような欠点を除去し、帯域の広い
FETスイツチを提供することを目的とする。
The present invention eliminates these drawbacks and provides a wide band
The purpose is to provide FET switches.
上記目的は、本発明によれば、ゲート幅が同じ
２つのFET（FET１，FET２）を直列に接続し、
該直列に接続されたゲート幅の同じFET（FET
１，FET２）の接続点とアース間に接続された
同じゲート幅のFET（FET３）から構成し、該直
列に接続されたFET（FET１，FET２）と直列
に接続されたFETの接続点とアース間に接続さ
れたFET（FET３）とは逆相のクロツクによつて
動作するFETスイツチ回路に、FETからなるソ
ースフオロア回路を接続したFETスイツチにお
いて、上記FETスイツチ回路を構成するFETの
ゲート幅WG１と上記ソースフオロア回路を構成
するFETのゲート幅WG２の比WG1／WG2を約
0.1に選定するようにした広帯域FETスイツチに
よつて達成される。
According to the present invention, the above purpose is to connect two FETs (FET1, FET2) with the same gate width in series,
FETs (FETs) with the same gate width connected in series
1. Consists of FETs (FET3) with the same gate width connected between the connection point of FET2) and ground, and the connection point of the series-connected FETs (FET1, FET2) and the series-connected FET and ground. In a FET switch in which a source follower circuit consisting of an FET is connected to a FET switch circuit operated by a clock of opposite phase to that of the FET (FET3) connected in between, the gate width WG1 of the FET constituting the above FET switch circuit is The ratio WG1/WG2 of the gate width WG2 of the FET that constitutes the source follower circuit above is approximately
This is achieved by a wideband FET switch selected to be 0.1.
本発明においては、上記の点に鑑みて、スイツ
チ回路のFETのゲート幅と、バツフア回路の
FETのゲート幅をさまざま変化させ、帯域幅を
測定した。
In the present invention, in view of the above points, the gate width of the FET of the switch circuit and the gate width of the buffer circuit are
We varied the gate width of the FET and measured the bandwidth.
その結果を第３図に示す。 The results are shown in FIG.
図において、横軸はスイツチ回路のゲート幅
（WG１），縦軸は帯域幅（ＧHz）を示す。また、
曲線WG２１は、バツフア回路のFETのゲート幅
を100μｍとした場合、曲線WG２２は同じく200μ
ｍとした場合、曲線WG２３は400μｍとした場合
である。 In the figure, the horizontal axis shows the gate width (WG1) of the switch circuit, and the vertical axis shows the bandwidth (GHz). Also,
Curve WG21 assumes that the gate width of the FET in the buffer circuit is 100μm, and curve WG22 also has a gate width of 200μm.
m, curve WG23 is 400 μm.
図の如く、曲線WG２１，WG２２，WG２３
は放物線となり、それぞれ最大値が存在する。 As shown in the diagram, curves WG21, WG22, WG23
are parabolas, and each has a maximum value.
具体的には、曲線WG２１の場合はWG1が10μ
ｍの時最大となり、曲線WG２２の場合はWG１
が20μｍの時最大となり、曲線WG２３の場合は
WG１が40μｍの時最大となる。 Specifically, in the case of curve WG21, WG1 is 10μ
Maximum when the curve is WG22, WG1
is maximum when it is 20μm, and in the case of curve WG23
It is maximum when WG1 is 40μm.
以上のことから、本発明では、スイツチ回路の
FETのゲート幅WG１とバツフア回路のFETの
ゲート幅幅WG２の比WG1／WG2を0.1に選ぶよ
うにした。 From the above, in the present invention, the switch circuit
The ratio WG1/WG2 of the gate width WG1 of the FET and the gate width WG2 of the buffer circuit FET was selected to be 0.1.
尚、ゲート製造のプロセス等によりWG1／
WG2の値を正確に0.1とする事は難しい。発明者
等の検討によれば、このWG1／WG2の値が0.1±
0.05程度の範囲におさめられれば、実用上問題な
くスイツチ回路を動作させられることが確認され
ている。 In addition, due to the gate manufacturing process, etc., WG1/
It is difficult to set the value of WG2 to exactly 0.1. According to the inventors' study, the value of WG1/WG2 is 0.1±
It has been confirmed that if the value is kept within a range of about 0.05, the switch circuit can be operated without any practical problems.
以上の如く、本発明によればFETのゲート幅
を最適値に設定するので、帯域幅を広くすること
ができる。
As described above, according to the present invention, since the gate width of the FET is set to an optimal value, the bandwidth can be widened.
第１図は従来から用いられているFETスイツ
チ回路を示す図、第２図はその等価回路、第３図
はゲート幅と帯域との関係を示す図である。
FIG. 1 is a diagram showing a conventionally used FET switch circuit, FIG. 2 is an equivalent circuit thereof, and FIG. 3 is a diagram showing the relationship between gate width and band.
Claims (1)
２）を直列に接続し、該直列に接続されたゲート
幅の同じFET（FET１，FET２）の接続点とア
ース間に接続された同じゲート幅のFET（FET
３）から構成し、該直列に接続されたFET（FET
１，FET２）と直列に接続されたFETの接続点
とアース間に接続されたFET（FET３）とは逆相
のクロツクによつて動作するFETスイツチ回路
に、FETからなるソースフオロア回路を接続し
たFETスイツチにおいて、 上記FETスイツチ回路を構成するFETのゲー
ト幅WG１と上記ソースフオロア回路を構成する
FETのゲート幅WG２の比WG1／WG2を約0.1に
設定するようにしたことを特徴とする広帯域
FETスイツチ。[Claims] 1. Two FETs with the same gate width (FET1, FET
2) are connected in series, and the FETs (FET1, FET2) with the same gate width are connected between the connection point of the series-connected FETs (FET1, FET2) and the ground.
3) and the FETs (FETs) connected in series.
1. A FET in which a source follower circuit consisting of an FET is connected to a FET switch circuit operated by a clock with the opposite phase to that of the FET (FET 3), which is connected between the connection point of the FET connected in series with FET 2) and the ground. In the switch, the gate width WG1 of the FET that constitutes the above FET switch circuit and the above source follower circuit constitute
A wide band characterized by setting the ratio WG1/WG2 of the gate width WG2 of the FET to approximately 0.1.
FET switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58035883A JPS59161918A (en) | 1983-03-07 | 1983-03-07 | Wide-band fet switch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58035883A JPS59161918A (en) | 1983-03-07 | 1983-03-07 | Wide-band fet switch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59161918A JPS59161918A (en) | 1984-09-12 |
| JPH0349211B2 true JPH0349211B2 (en) | 1991-07-26 |
Family
ID=12454401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58035883A Granted JPS59161918A (en) | 1983-03-07 | 1983-03-07 | Wide-band fet switch |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59161918A (en) |
-
1983
- 1983-03-07 JP JP58035883A patent/JPS59161918A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59161918A (en) | 1984-09-12 |
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