JPH035107B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilevel pulse generation circuit applied to driving a CCD.

When driving a CCD, which is one type of solid-state imaging device, three-level pulse signals P ₁ and P ₂ as shown in FIG. 1 are required. Conventionally, a pulse generating circuit having the configuration shown in FIG. 2 has been used. In the figure, 1 and 2 indicate drivers, and for the sake of simplicity, only the output transistors of the drivers 1 and 2 are shown. The driver 1 operates with power supply voltages V _cc2 and V _cc1 (V _cc2 >V _cc1 ), and its input terminal 3 is supplied with a pulse signal P ₃ shown in FIG. The period of this pulse signal _P3 becomes one field. As a result of this input pulse signal _P3 , a pulse signal P4 appears at the output terminal 4 of the driver 1, with V _cc1 at a low level and V _cc2 at a high level, with the opposite polarity to the input pulse, as shown in Figure ₃ . . On the other hand, a pulse signal indicated by P ₅ or P ₆ in FIG. 3 is applied to the input terminal 5 of the driver 2. Pulse signal P ₁ shown in Figure 1
is generated at the output terminal 6 of the driver 2 to drive the capacitive load 7, the pulse signal
P ₅ is supplied to the input terminal 5, and a pulse signal P ₆ is supplied to the input terminal ₅ when generating the pulse signal P 2 shown in FIG. Pulse signal P ₅
is supplied to the input terminal 5, the previous stage driver 1 is activated during the low level section of this pulse signal _P5 .
Since the output pulse P ₄ of is superimposed, OV, V _cc1 ,
A pulse voltage of three levels of _Vcc2 is generated at the output terminal 6. The pulse signals P ₅ and P ₆ have a repeating period of a horizontal period.

Such a conventional multi-level pulse generation circuit is
As is clear from the above explanation, there is a problem in that the power supply voltage of the maximum value among the multi-value levels is required, and the scale of the power supply circuit becomes large.

The present invention aims to eliminate the drawbacks of the conventional multi-level pulse generating circuit, and requires only a low level of power supply voltage.

An embodiment of the present invention will be described below with reference to FIGS. 4, 5, and 6. This embodiment is designed to generate three-level pulses, and the first stage driver 1 is connected to the power supply voltage.
Provided between the power supply terminal 8 to which V _cc1 is supplied and the ground.
Further, the power supply terminal of the driver 2 at the first stage is connected to the output terminal 4 of the driver 1 via a capacitor 9 having a capacitance sufficiently larger than that of the load 7. The power supply voltage V _cc2 applied to the power supply terminal 10 is supplied to the power supply terminal of this driver 2 via a diode 11. A capacitive load 7 such as a CCD is connected to the output terminal 6 of this driver 2, and is coupled to a connection point between a capacitor 9 and a diode 11 via a diode 12. The input terminal 3 of the driver 1 is supplied with the pulse signal P ₃ shown in FIG. 6 as in the conventional case, and the input terminal 5 of the driver 2 is supplied with the pulse signal P ₅ or P ₆ .

One embodiment of the invention described above can be represented by the equivalent circuit shown in FIG. In the same figure,
_S1 indicates a switch circuit corresponding to the first stage driver, and _S2 indicates a switch circuit corresponding to the next stage driver. During the period in which the pulse signal _P3 is at a high level, the switch circuit _S1 is connected to the ground side, the capacitor 9 is charged to the power supply voltage _Vcc2 , and the driver 2 is connected between the power supply voltage _Vcc2 and the ground level. It's working. Next, when the pulse signal P ₃ becomes low level, the switch circuit S ₁ is connected to the power supply terminal 8 side, and the power supply voltage for the driver 2 (switching circuit S ₂ ) becomes (V _cc2 +V _cc1 ), Driver 2 is connected to the ground level and (V _cc2 +
V _cc1 ). Then again the pulse signal P ₃
becomes high level, the diode 12 from the load 7
A current path is formed through which the capacitor 9 passes, and since the value of the capacitor 9 is large, the output potential instantly returns to _Vcc2 . Therefore, the three-level pulse signal shown in FIG.
Drive by _P1 can be performed.

FIG. 7 shows an example of a driver that can be used in the present invention. Since both drivers 1 and 2 have the same configuration, driver 1 will be explained as an example. In FIG. 7, reference numeral 13 indicates a differential amplifier, and the differential amplifier 13 is constructed by a pair of transistors 14A and 14B whose emitters are commonly connected, and a constant current source 15 connected to the common emitter connection point.
is configured. This one transistor 14
A's base is connected to the input terminal 3, its collector is connected to the power supply terminal 8, and a fixed DC voltage source 16 is connected to the base of the other transistor 14B.
is connected. A resistor 17 is inserted between the collector of the transistor 14B and the power supply terminal 8, and the collector is connected to the base of the PNP transistor 18.

The emitter of this transistor 18 is the power supply terminal 8
, and its collector is connected to the collector of the NPN transistor 19. transistor 1
The base of 9 is connected to the input terminal 3 via a resistor 20 and grounded via a resistor 21, and its emitter is also grounded. A common connection point between the collectors of these complementary transistors 18 and 19 is connected to a common connection point between the bases of output transistors 22 and 23. transistor 22,
A resistor 24 is inserted between the base common connection point of 23 and the emitter common connection point, that is, the output terminal 4.

An input pulse with an amplitude of 5 V is supplied to the input terminal 3 of the driver described above, for example, at the horizontal scanning frequency of a television. When this input pulse rises to 5V from OV, since the value of the DC voltage source 16 is about 2.5V, the transistors 14A and 19
is turned on, and transistors 14B and 18 are turned off. Therefore, transistor 22 is turned off,
The transistor 23 turns on, and the output terminal 4
is grounded.

When the input pulse falls to OV, transistor 1
4A and 19 are turned off, and transistors 14B and 19 are turned off.
18 is turned on. Therefore, transistor 22
is on, transistor 23 is off,
Output terminal 4 is connected to power supply terminal 8. In this way, the potential at the common collector connection point of transistors 18 and 19 and the output terminal 4 is equal to the power supply voltage V _cc1
The polarity changes to the opposite polarity of the input pulse at an amplitude of . Normal output pulse amplitude is 10V to 20V.

In the above configuration, the magnitude of the constant current source 15 of the differential amplifier 13 is determined by the minimum source amplitude necessary to turn on and off the transistor 18 (transistor 18
For example, it is set to /mA, which generates a pulse whose voltage drop is slightly larger than the base-emitter voltage drop of . Therefore, if no load current is flowing,
That is, when charging or discharging of the capacitive load connected to the output terminal 4 is completed, the current flowing through the circuit can be reduced, and power consumption can be reduced. Of course, in the present invention, drivers other than the configuration shown in FIG. 7 may be used.

Further, in the case of forming three-level pulses (V _cc1 =V _cc2 =V _cc ), it is sufficient to use only one type of power supply voltage V _cc as shown in FIG. 8. Furthermore, when two types of power supply voltages are required, the stator of the variable resistor 25 is inserted between the power supply terminal 8 and the ground, as shown by the broken line in FIG. A configuration in which it is connected to an anode may also be used. 26 is a decoupling capacitor.

FIG. 9 shows another embodiment in which the present invention is applied to a four-level pulse generation circuit. Here, 0,
Four values of V _cc , 2V _cc , and 3V _cc are formed, and therefore one type of power supply voltage V _cc is used. First, as in FIG. 8, the output terminal 4 of the driver 1 is connected to the power supply terminal of the driver 2 via the capacitor 9. Pulse signals P 3 and P 5 shown in FIGS. 10A and 10B are supplied to the input terminal ₃ of the driver 1 and the input terminal ₅ of the driver 2, respectively. Further, the output terminal 6 of the driver 2 is connected to the power supply terminal of the third driver 28 via a capacitor 27. The pulse signal shown in FIG. 10C is applied to the input terminal 29 of this driver 28.
P ₇ is supplied, and a capacitive load 7 is connected to its output terminal 30. The power terminal of the driver 28 and the power terminal of the preceding driver 2 are connected via a diode 31, and the power terminal of the driver 28 and its output terminal 30 are connected via a diode 32. Ru.

In the configuration of the other embodiment of the invention described above,
In the interval t ₁ (see FIG. 10) where the pulse signal P ₃ is at a high level and the pulse signals P ₅ and P ₇ are at a low level, the charging voltage of the capacitors 9 and 27 causes the driver 2 to
The level of the output pulse signal of No. 8 becomes 2V _cc . Next, in interval t ₂ where pulse signal P ₅ is at a high level,
Since capacitor 27 is discharged, the output level becomes _Vcc . In the next period _t3 in which the pulse signal _P7 is at a high level, the output terminal 30 is grounded. Also, as shown at t ₄ in Figure 10,
When all the pulse signals supplied to each driver become low level, the output level reaches the maximum value of 3V _cc . In this way, as shown in FIG.
A pulse signal P ₁ of value level can be generated at the output terminal 30 .

In this way, using (n-1) drivers,
By connecting the output terminal of the driver at the previous stage to the power supply terminal of the driver at the next stage via a capacitor, a pulse signal of n-value level can be generated.

As can be understood from the description of the embodiments described above, in the present invention, when generating a pulse signal of the n-value level, unlike the conventional configuration, the power supply voltage of the maximum level among the n-value levels is not required. Instead, as in the above embodiment, 3 of O, V _cc2 (V _cc1 + V _cc2 )
As is clear from the case where the value is generated, the level of the power supply voltage can be lowered. Further, since a lower power supply voltage can be formed by resistor division, it is sufficient to have a power supply voltage at the higher level of V _cc1 or V _cc2 . Furthermore, according to the present invention, when the level differences in the output levels are at equal intervals, it is sufficient to use one power supply voltage corresponding to the level differences, so that the circuit configuration can be further simplified.

[Brief explanation of drawings]

1, 2, and 3 are waveform diagrams and connection diagrams used to explain a conventional multilevel pulse generation circuit, and FIGS. 4 and 5 are connection diagrams and equivalent equivalents of an embodiment of the present invention. A circuit diagram, FIG. 6 is a waveform diagram used to explain the operation of an embodiment of this invention, FIG. 7 is a connection diagram of an example of a driver that can be used in this invention, and FIG. 8 is a diagram showing an example of a driver that can be used in this invention. A connection diagram of an example of a partially changed configuration, and FIGS. 9 and 10 are connection diagrams of other embodiments of the present invention and waveform diagrams used to explain the operation thereof. 1, 2, 28...driver, 3, 5, 29...
...Driver input terminal, 4,6,30...Driver output terminal, 7...Capacitive load.

Claims (1)

[Claims] 1 A first driver having at least two drivers, the output terminal of which is connected to either one of the first power supply terminals or the other according to an input pulse signal, and the output of this first driver. It consists of a capacitor inserted between the terminal and one of the power supply terminals of the second driver, and a unidirectional conduction element inserted between one of the power supply terminals of the second driver and the second power supply terminal. , a multi-level pulse generation circuit in which a capacitive load is connected to the output terminal of the second driver.