JPH0351301B2 - - Google Patents
Info
- Publication number
- JPH0351301B2 JPH0351301B2 JP60011001A JP1100185A JPH0351301B2 JP H0351301 B2 JPH0351301 B2 JP H0351301B2 JP 60011001 A JP60011001 A JP 60011001A JP 1100185 A JP1100185 A JP 1100185A JP H0351301 B2 JPH0351301 B2 JP H0351301B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor device
- semiconductor
- resin
- molding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置にかかるものであり、特に
モールド成形によつて半導体素子に加えられる応
力負荷に対して改良構造を有する半導体装置に関
するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a semiconductor device having an improved structure against stress loads applied to semiconductor elements by molding. be.
半導体素子がモールド成形される半導体装置と
しては、例えば第３図に示すものがある。この図
において、半導体素子１は、まずフレーム２に固
着され、次に、ワイヤ３によつて各々対応するリ
ード部２１に布線されて組立てられる。そして、
その後トランスフアモールド法等により、エポキ
シ樹脂４等で成形封止される。
An example of a semiconductor device in which a semiconductor element is molded is shown in FIG. In this figure, a semiconductor element 1 is first fixed to a frame 2, and then wired to corresponding lead parts 21 with wires 3 to be assembled. and,
Thereafter, it is molded and sealed with epoxy resin 4 or the like by a transfer molding method or the like.
ところで、かかる成形封止において、成形後の
樹脂は、硬化後の冷却とともに通常収縮が生じ、
半導体素子１に対して大きな圧力を及ぼす。この
ため、半導体素子１の周縁部に欠陥が発生し、半
導体装置としての機能に支障が生ずるおそれがあ
る。
By the way, in such molding and sealing, the resin after molding usually shrinks as it cools after curing.
A large pressure is exerted on the semiconductor element 1. Therefore, defects may occur in the peripheral portion of the semiconductor element 1, which may impede the function of the semiconductor device.
また、モールド用の樹脂４と半導体素子１は通
常熱膨張係数が一桁以上異なるため、半導体装置
の使用中すなわち動作中の温度変化により、いわ
ゆる熱応力が生ずることとなる。これらの応力
は、半導体素子１の周縁部が大きく、また、半導
体素子１の主表面に生ずる応力は大きくなる。 Further, since the molding resin 4 and the semiconductor element 1 usually differ in coefficient of thermal expansion by an order of magnitude or more, so-called thermal stress occurs due to temperature changes during use, that is, operation, of the semiconductor device. These stresses are greater at the peripheral edge of the semiconductor element 1, and the stress occurring at the main surface of the semiconductor element 1 is greater.
本発明は、かかる従来技術の欠点に鑑みてなさ
れたものであり、成形樹脂による半導体素子への
応力負荷を低減することができる半導体装置を提
供することを目的とする。 The present invention has been made in view of the drawbacks of the prior art, and it is an object of the present invention to provide a semiconductor device that can reduce stress loads on semiconductor elements due to molded resin.
本発明は、樹脂材によつてモールド成形される
半導体素子の主表面の周縁部に軟質材からなる絶
縁性の環状冠帯を設けたことを特徴とするもので
ある。
The present invention is characterized in that an insulating annular crown band made of a soft material is provided at the periphery of the main surface of a semiconductor element molded with a resin material.
本発明によれば、半導体素子の周縁部に設けら
れた軟質材により樹脂材の熱変形による応力負荷
が吸収され、半導体素子に対する応力負荷が低減
される。
According to the present invention, the stress load due to thermal deformation of the resin material is absorbed by the soft material provided at the peripheral portion of the semiconductor element, and the stress load on the semiconductor element is reduced.
以下、本発明にかかる半導体装置を添付図面に
示す実施例に基づいて詳細に説明する。
Hereinafter, a semiconductor device according to the present invention will be described in detail based on embodiments shown in the accompanying drawings.
第１図には本発明にかかる半導体装置の一実施
例が示されている。また、第１図の破線部分が拡
大して第２図に示されている。なお、前述した従
来技術と同様の構成部分については同一の符号を
用いることとする。 FIG. 1 shows an embodiment of a semiconductor device according to the present invention. Further, the broken line portion in FIG. 1 is enlarged and shown in FIG. 2. Note that the same reference numerals are used for the same components as in the prior art described above.
第１図及び第２図において半導体素子１には、
その主表面にコート層５が形成されている。この
コート層５は基本的には半導体素子１の主表面の
周縁部のみに形成すればよいが、製造上の容易さ
からすれば主表面の全体に形成してよく、これに
よつて半導体素子１の機能に格別の障害が生ずる
ことはない。 In FIGS. 1 and 2, the semiconductor element 1 includes:
A coating layer 5 is formed on its main surface. Basically, this coat layer 5 only needs to be formed on the periphery of the main surface of the semiconductor element 1, but from the viewpoint of ease of manufacture, it may be formed on the entire main surface. There is no particular problem with the function of item 1.
次に半導体素子１の主表面の周縁部には、必要
とすれば切欠きを設けて、その部分に環状冠帯５
１が形成されている。この環状冠帯５１は、例え
ばシリコン樹脂等の絶縁性軟質材が使用される。
この環状冠帯５１は、スピンコート法あるいはス
クリーン印刷法等を用いてコート層５と同時に形
成される。形成後、ウエハ上の多数の半導体素子
を分割するダイシング工程により切断されて、各
半導体素子１毎に環状冠帯５１が形成されること
となる。５２はダイシング時に形成されたダイシ
ング面である。このように、環状冠帯５１は半導
体素子１と一体構成され、その後に樹脂４による
モールド工程が行われるようになつている。した
がつて、モールドは第３図の従来例の場合と同様
に、極めて簡単に例えば１挙動で実施できる利点
がある。 Next, a notch is provided at the peripheral edge of the main surface of the semiconductor element 1, if necessary, and an annular crown band 5 is formed in that part.
1 is formed. This annular crown band 51 is made of an insulating soft material such as silicone resin, for example.
This annular crown band 51 is formed simultaneously with the coating layer 5 using a spin coating method, a screen printing method, or the like. After formation, the wafer is cut by a dicing process to divide a large number of semiconductor elements on the wafer, and an annular crown band 51 is formed for each semiconductor element 1. 52 is a dicing surface formed during dicing. In this way, the annular crown band 51 is constructed integrally with the semiconductor element 1, and then a molding process using the resin 4 is performed. Therefore, the mold has the advantage that it can be implemented very easily, for example, in one motion, as in the case of the conventional example shown in FIG.
次に上記実施例の作用について説明すると、環
状冠帯５１は、軟質材によつて形成されているた
め、モールド用の樹脂４による応力負荷を吸収す
ることができる。従つて半導体素子１に対する応
力負荷が低減されることとなる。 Next, the operation of the above embodiment will be explained. Since the annular crown band 51 is made of a soft material, it can absorb the stress load caused by the molding resin 4. Therefore, the stress load on the semiconductor element 1 is reduced.
なお、半導体素子１の大きさは、どのようなも
のであつてもよいが、特にLSIなどの比較的大型
のものに対しては、特に効果が大きい。 Note that the size of the semiconductor element 1 may be any size, but the effect is particularly great for a relatively large size such as an LSI.
以上説明したように、本発明による半導体装置
によれば、半導体素子の周縁部に軟質材からなる
環状冠帯を設けることとしたので、モールド材に
よる応力負荷を低減することができ、半導体素子
の機能が損なわれるおそれがなく信頼性の向上を
図ることができるという効果がある。
As explained above, according to the semiconductor device according to the present invention, since the annular crown made of a soft material is provided at the peripheral edge of the semiconductor element, the stress load caused by the molding material can be reduced, and the stress of the semiconductor element can be reduced. This has the effect that reliability can be improved without fear of loss of functionality.
第１図は本発明にかかる半導体装置の一実施例
を示す断面図、第２図は第１図の破線部分を拡大
して示す拡大図、第３図は従来の半導体装置の一
例を示す断面図である。
図において、１は半導体素子、２はフレーム、
３はワイヤ、４は樹脂、５はコート層、２１はリ
ード部、５１は環状冠帯、５２はダイシング面で
ある。なお、各図中同一符号は、同一又は相当部
分を示すものとする。
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is an enlarged view showing the broken line portion in FIG. 1, and FIG. 3 is a cross-sectional view showing an example of a conventional semiconductor device. It is a diagram. In the figure, 1 is a semiconductor element, 2 is a frame,
3 is a wire, 4 is a resin, 5 is a coating layer, 21 is a lead portion, 51 is an annular crown band, and 52 is a dicing surface. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
止してなる半導体装置において、 前記半導体素子はその主表面側の周縁部に軟質
絶縁材からなる環状冠帯を有することを特徴とす
る半導体装置。[Scope of Claims] 1. A semiconductor device in which a semiconductor element is sealed by molding a resin material, characterized in that the semiconductor element has an annular crown band made of a soft insulating material at the peripheral edge on the main surface side thereof. semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60011001A JPS61171156A (en) | 1985-01-25 | 1985-01-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60011001A JPS61171156A (en) | 1985-01-25 | 1985-01-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61171156A JPS61171156A (en) | 1986-08-01 |
| JPH0351301B2 true JPH0351301B2 (en) | 1991-08-06 |
Family
ID=11765886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60011001A Granted JPS61171156A (en) | 1985-01-25 | 1985-01-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61171156A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4675146B2 (en) * | 2005-05-10 | 2011-04-20 | パナソニック株式会社 | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS413776Y1 (en) * | 1964-03-03 | 1966-02-28 |
-
1985
- 1985-01-25 JP JP60011001A patent/JPS61171156A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61171156A (en) | 1986-08-01 |
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