JPH035172B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a device that generates a heartbeat sound synchronized with the heartbeat cycle and then changes the generation cycle of the heartbeat sound over time, and further relates to a device that changes the generation cycle of the heartbeat sound as time passes. The generation cycle of heartbeat sounds is changed in response to changes in heart rate.

(Prior Art) Conventionally, as described in Japanese Patent Application Laid-Open No. 54-98651, a pulse wave, that is, a heartbeat is detected by a pulse wave detection device, and a heartbeat sound corresponding to this detection signal is generated. Measuring devices are known.

By the way, the heart rate under normal conditions is 70-80 beats per minute.
It is known that this number decreases to about 50 to 60 times per minute during sleep or in a relaxed state of mind, and increases to about 90 to 100 times per minute when excited or mentally tense. It is said that it is possible to control one's own heartbeat and mental state by concentrating on a certain sound.

(Problems to be Solved by the Invention) The present invention is a further development of the conventional heart rate measuring device described above, and its purpose is to provide a device that can easily control the mental state of the user. It is in.

(Means for Solving the Problems) In order to solve the above problems, the present invention generates a heartbeat sound synchronized with the heartbeat cycle, then changes the generation cycle of the heartbeat sound by a predetermined amount, and then uses the The present invention is characterized in that the generation cycle of the heartbeat sound is changed by a predetermined amount every time the heartbeat cycle of the person matches.

(Embodiments) Preferred embodiments of the present invention will be described below based on the drawings. FIG. 1 shows an embodiment in which a heartbeat sound generating device according to the present invention is combined with a watch with an alarm function.

The oscillation circuit 2, the frequency dividing circuit 4, the waveform shaping circuit 6, the motor 8, the wheel train 10, and the pointer display 12 constitute a conventionally well-known analog timepiece. The reference mechanism 14 is built into the wheel train 10, and supplies the AND gate 16 with an alarm start signal that remains "H" for about 20 minutes when the set time arrives. The AND gate 16 is also supplied with the output of a ring stop switch 18, and when an alarm start signal is generated when the switch 18 is closed, a heartbeat signal is supplied to the sound generation circuit 19 from a heartbeat signal generation circuit 82, which will be described later.
The sound generation circuit 19 is a circuit that converts a heartbeat signal into a heartbeat sound.

The heartbeat detection circuit 20 detects a heartbeat and generates a detection signal corresponding to the heartbeat, and is composed of a heartbeat detection section 22 and a waveform shaping circuit 24.
The heartbeat detection unit 22 uses, for example, a photoplethysmogram detection method, which shines infrared light emitted by a light emitting diode onto the fingertip, and detects reflected light whose intensity is modulated by blood flow.
The transmitted light is detected by a phototransistor. The waveform shaping circuit 24 shapes the signal from the heartbeat detection section 22 into a square wave with a constant pulse width, and outputs it as a detection signal. These output waveforms are shown in FIG.

The heartbeat measuring circuit 26 measures the cycle of the above-mentioned detection signal every time a certain number of the detection signals are output, and obtains the number of heartbeats occurring per minute from the cycle.
The counter 28 is supplied with the detection signal outputted to output B, and when it counts a certain number (for example, "4"), a carry signal causes the flip-flop (hereinafter referred to as
(referred to as FF) 30 is inverted. This FF3
The output L of 0 is the clock signal φ ₃ from the frequency divider circuit 4.
(10 KHz) and is supplied to the AND gate 32, and if the output L is "H", the clock signal φ ₃ is supplied to the period counter 34.
Since the output of the FF 30 is inverted every time the detection signal is output four times, the period counter 34 counts the reference signal φ ₃ only during the period in which the detection signal is output four times, and this count value is the detection signal. This represents the time required for outputting four times. Then, the arithmetic circuit 36 converts the period counter 3
The time required for one heartbeat is determined from the output signal of step 4, and this is further converted into the number of heartbeats occurring per minute.

The initial value setting circuit 42 is a circuit that stores the initial heart rate from the heart rate measuring circuit 26, and when the output of the AND gate 44 rises, the output signal of the arithmetic circuit 36 is stored in the latch circuit 46. In other words, the AND gate 44 contains the output M of the FF 30 and the FF that will be in the set state for 10 seconds from the start of operation of this device.
48 output N is supplied, and when the output M is first inverted to "H" after the start of operation, the arithmetic circuit 36
The output signal of is stored in the latch circuit 46.

The count circuit 50 is a circuit that starts counting operation after the initial value setting circuit 42 performs the storage operation. The counter 52 counts the clock signal supplied from the AND gate 54, and the output P of the FF 58 is supplied to the AND gate 54 along with the clock signal selected by the switching gate 56.
The switching gate 56 is supplied with the clock signal φ ₁ (1/4 Hz) and the clock signal φ ₂ (1 Hz) from the frequency dividing circuit 4, and the output D is supplied to the switching control terminal. Then, if the output D is "H", the clock signal φ ₁ is selectively output, and if the output D is "L", the clock signal φ ₂ is selectively output.

The operation control circuit 60 is a circuit that outputs control signals for controlling the operations of the heart rate measuring circuit 26, the initial value setting circuit 42, and the counting circuit 50.
The single pulses generated from the one-shot circuits 62 and 64 are both supplied to an OR gate 66, and the single pulse generated at the output F of the OR gate 66 is supplied as a control signal to start heart rate counting.
38 and 48 set terminals S.

Here, the output J of the FF 38 becomes "H" and the output K becomes "L", and the heartbeat detection circuit 20 starts the detection operation, and the heartbeat measurement circuit 26 also starts the measurement operation. Further, the output N of the FF 48 becomes "H", and the AND gate 44 is opened.

Further, the single pulse generated at the output F prompts the operation of the timer circuit 68, and a single pulse is generated at the output G again after 10 seconds have elapsed. This output G is supplied to the reset terminal R of the FF48 and the set terminal S of the FF58, and the output N of the FF48 is set to "L" to close the AND gate 44, and the output P of the FF58 is set to "H" to perform the counting operation of the count circuit 50. start. The one-shot circuit 62 has an output C.
Outputs D are supplied to the one-shot circuits 64, respectively.

Further, the output C is inverted and supplied to the OR gate 70, and the output E of the OR gate 70 is used as a control signal to reset the counter 52 and is sent to the reset terminal R of the counter 52, the heartbeat detection circuit 20, and the heartbeat measurement circuit 26. A control signal for stopping the operation of the FF 38 is supplied to the reset terminal R of the FF 38.

Further, the comparison circuit 72 is a circuit that compares an output signal from an arithmetic circuit 80 and a code signal from the encoder 74, which will be described later.When the output D is "H", the arithmetic circuit 80 When the value of the output signal from D becomes large, a single pulse is generated at the output H, and when the output D is "L", conversely, when the value of the output signal becomes small, a single pulse is generated at the output H. In this embodiment, the encoder 74
If the output D is "H", the code signal is "80",
It is set to be "50" if the output D is "L". The single pulse generated at the output H is supplied to the reset terminal R of the FF 58 as a control signal for stopping the counting operation of the counting circuit 50. Further, the output H is supplied to the other input terminal of the AND gate 76, which is an inverted version of the output D, and when the output D is "L", the single pulse generated at the output H is used to input the timer circuit 78. is operated, and after one minute has elapsed, a single pulse is generated at the output I and the single pulse is supplied to the OR gate 70.

The arithmetic circuit 80 is a circuit that can add and subtract the heart rate stored in the initial value setting circuit 42 and the count value of the count circuit 50, and if the output D is "H", it adds the heart rate and the count value. And the output D is
If "L", the count value is subtracted from the heart rate.
The calculated value of the calculation circuit 80 is supplied to the comparison circuit 72 and the frequency division ratio converter 84 in the heartbeat signal generation circuit 82.

The heartbeat signal generation circuit 82 is a circuit that generates a heartbeat signal for generating a heartbeat sound with a cycle corresponding to the calculation value of the calculation circuit 80. A programmable counter 86 consisting of 8 bits and a frequency dividing circuit 88 consisting of 8 stages divide the clock signal φ ₄ (32768Hz) from the frequency dividing circuit 4, and the frequency division ratio of the programmable counter 86 is as follows. Frequency division ratio converter 84
The output of the lower 4 bits of the frequency divider circuit 88 is set by the frequency division ratio setting signal from the AND gate 90.
supplied to The frequency division ratio converter 84 is an arithmetic circuit 80
The calculated value is converted into a frequency division ratio setting signal for setting the frequency division ratio necessary for counting the period corresponding to the calculated value, and the relationship between the two is expressed by the following relationship. In other words, the value of the calculated value is N1,
If the value of the frequency division ratio setting signal is N2, the relationship is approximately expressed as N2 = 32768Hz/256÷N1/60sec.

FF92 starts or ends the operation of the heartbeat signal generating circuit 82, and the set terminal S is supplied with an output G, and the reset terminal R is supplied with an output E. The output R of the FF 92 is supplied to the reset terminal R of the programmable counter 86, and the output Q together with the clock signal _φ4 is supplied to the clock input φ of the programmable counter 86 via an AND gate 94.

On the other hand, a pulse signal with a duty ratio of 1/16 corresponding to the period setting signal is generated at the output of the AND gate 90, and this output is further supplied to the AND gate 96. The AND gate 96 is also supplied with an audible frequency signal φ ₅ (for example, 2048 Hz) from the frequency dividing circuit 4, and supplies an output S from which a heartbeat signal is generated to the sound generation circuit 19.

The follow-up monitoring circuit 98 is a circuit that compares the calculated value from the arithmetic circuit 80 and the heart rate from the heart rate measuring circuit 26, and if they do not match, stops the counting operation of the counting circuit 50 until they match. The latch circuit 100 stores the heart rate from the calculation circuit 36 every time the output M rises to "H", and supplies the stored value to the comparison circuit 102. Comparison circuit 102
In addition, the calculated value from the calculation circuit 80 is also supplied,
Let's compare the two. When the two match, a match signal that remains "H" is output to the output T for a certain period of time after the mismatch, and the output T is supplied together with the output D to the OR gate 104, and the output U of the OR gate 104 is sent to the count circuit 50. and gate 54
is supplied to. Therefore, when the output D is "H", the output U is also "H", so the AND gate 54 is always open, and therefore the counting operation of the count circuit 50 is never stopped. However, when the output D is "L", the output U becomes "H" only by the coincidence signal when the calculated value from the calculation circuit 80 and the heart rate from the heart rate measurement circuit 26 match.
Therefore, if the calculated value and the heart rate do not match, the counting operation of the counting circuit 50 is stopped.

This embodiment is constructed as described above, and the operation of this embodiment will be explained below with reference to FIGS. 3 and 4.

At time _t1 , when the ring stop switch 18 is closed, the output E becomes "L", so the counter 52,
FFs 38 and 92 are released from reset and a single pulse from one shot circuit 62 is generated at output F, setting FFs 38 and 48. Therefore, the heartbeat detection circuit 20 and the heartbeat measurement circuit 26 start operating.

At time _t2 , when a predetermined detection signal is output from the heartbeat detection circuit 20, the output L of the FF 30 is
From "H" to "L", output M goes from "L" to "H"
Since the count value of the period counter 34 is reversed, the counting operation of the period counter 34 is stopped, and the number of heartbeats occurring in one minute, which is converted based on the count value of the counter 34, is stored in the latch circuits 46 and 100. Note that at this point, the count value of the counter 52 is "0", so the calculated value from the calculation circuit 80 and the heart rate from the latch circuit 100 match, and therefore the output T
and U is "H".

Then, at time t ₃ , which is 10 seconds after time t ₁ , a single pulse is output from the timer circuit 68 to the output G, so even if the FF 48 is reset and the output M rises to "H" thereafter, the latch remains unchanged. The contents of circuit 46 cannot be changed. Further, since FFs 58 and 92 are set, the operation of the count circuit 50 and heartbeat signal generation circuit 82 is started. Here the output D
Since the clock signal φ 2 is “L”, the counter 52 is supplied with the clock signal φ ₂ . Then, when the clock signal φ ₂ is supplied to the counter 52, the calculated value is subtracted by the calculation circuit 80, so that the heart rate from the latch circuit 100 does not match. Therefore, a certain period of time (for example, 1 to 2
seconds), the outputs T and U are inverted to "L" as shown at time _t4 , and as a result, the count circuit 50
The counting operation will be stopped.

Furthermore, in the heartbeat signal generation circuit 82, the arithmetic circuit 80
A heartbeat signal with a period corresponding to the calculated value of is generated.
For example, if the calculated value is "70", this is converted to "110" by the frequency division ratio converter 84 and preset in the programmable counter 86. Therefore, a heartbeat signal with a period of 0.86 seconds is generated at the output S, and as a result, a heartbeat sound is generated by the sounding circuit 19 at the same period.

On the other hand, the heart rate measurement circuit 26 constantly performs measurement operations, and every time a predetermined detection signal is output, FF3
The latest heart rate is stored in the latch circuit 100 each time the output of 0 is inverted and the output M rises to "H". Then, as shown at time _t5 , when the calculated value from the calculation circuit 80 and the heart rate from the latch circuit 100 match, the outputs T and U become "H" and the counting operation of the counting circuit 50 is restarted. . Therefore, the count value of the counter 52 increases, and conversely, the calculated value from the arithmetic circuit 80 decreases, which again becomes inconsistent with the heart rate. Therefore the outputs T and U
becomes "L" again after a certain period of time, and during this time the counting operation of the count circuit 50 is performed.

Therefore, the calculated value from the calculation circuit 80 naturally decreases, and therefore the generation cycle of the heartbeat signal generated from the heartbeat signal generation circuit 82 becomes longer. For example, if the calculated value is "60", a frequency division ratio of "128" is set in the programmable counter 86, the period of the heartbeat signal is 1 second, and the period of the heartbeat sound is also 1 second.

Similarly, each time the user's heart rate matches the calculated value from the calculation circuit 80, the period of heartbeat sound generation becomes longer.

Then, at time _t6 , when the calculated value from the calculation circuit 80 becomes "50" or less, a single pulse is output to the output H of the comparison circuit 72, so the FF 58 is reset and the counting operation of the counting circuit 50 is stopped. . Therefore, the generation cycle of the heartbeat sound does not change thereafter. The operation of the timer circuit 78 is also prompted by the single pulse of the output H, and at time _t7 after one minute has passed, the FFs 38 and 92 are reset,
The heartbeat detection operation, heartbeat measurement operation, and heartbeat sound generation operation are stopped, and the contents of the counter 52 are also cleared.

On the other hand, when the set time arrives at time _t8 , the output D becomes "H" due to the alarm start signal from the reference mechanism 14, and the one-shot circuit 6 is connected to the output F.
A single pulse from 4 is generated. Therefore, the initial heart rate of the initial value setting circuit 42 is stored in the same manner as the operation from time _t1 to time _t2 . It should be noted that at time _t8 , the outputs T and U have already become "H", so it is understood that the operation of the follow-up monitoring circuit 98 is disabled thereafter.

At time _t10 , a single pulse from the timer circuit 68 is output to the output G, and the counting circuit 50 and the heartbeat signal generating circuit 82 start operating. If the heart rate stored in the initial value setting circuit 42 at time t ₉ is, for example, "50", then at time t ₁₀ the division ratio setting signal becomes "154", so the output S has approximately 1.2 A heartbeat signal with a period of seconds is generated. Also, since the output D is "H" at this time, the clock signal φ ₁ is supplied to the counter 52, and the arithmetic circuit 80 adds the heart rate stored in the initial value setting circuit 42 and the count value of the counter 52. act. For example, the clock signal _φ1 is 1/2Hz.
If it is set to , the value of the frequency division ratio setting signal will become smaller every two seconds. Therefore, as the frequency division ratio preset in the programmable counter 86 becomes smaller, the generation period of the heartbeat signal generated at the output S and the generation period of the heartbeat sound generated from the sound generation circuit 19 become shorter. For example, time
After 30 seconds have passed since t ₁₀ , the count value of the counter 52 is "15", the calculated value from the calculation circuit 80 is "65", and the division ratio setting signal is "118", so the output S is generated. The period of the pulse signal is approximately 0.92
Similarly, the heartbeat sound generation period is approximately 0.92 seconds. It will be understood that the generation cycle of the heartbeat sound gradually becomes shorter in the same manner.

Then, at time _t11 , when the calculated value from the calculation circuit 80 becomes "80" or more, a single pulse is output to the output H of the ratio comparison circuit 72, so the FF 58 is reset and the counting operation of the counting circuit 50 is stopped. Ru. Therefore, the generation cycle of the heartbeat sound does not change thereafter.

Then, at time t ₁₂ , the ring stop switch 1
8, the output E becomes "H", so the FFs 38 and 92 are reset, the heartbeat detection operation, the heartbeat measurement operation, and the heartbeat sound generation operation are stopped, and the contents of the counter 52 are also cleared.

(Effects of the Invention) As described above, according to this embodiment, the heartbeat sound generating device according to the present invention is combined with a watch with an alarm function, and after setting the alarm, a heartbeat sound with a period slightly longer than that of the user's heartbeat can be generated. When the user's heartbeat follows the cycle of the heartbeat sound, the cycle of the heartbeat sound is slightly lengthened again, thereby gradually decreasing the user's heartbeat and relaxing the user's mental state. Therefore, it is possible to induce a comfortable sleepiness in the user. Also, when the set time arrives, a heartbeat sound synchronized with the heartbeat cycle is generated, and then the generation cycle of the heartbeat sound is shortened as time passes.
It acts to gradually increase the user's heart rate and bring the user's mental state to a normal state, so it can induce a comfortable awakening.

In this embodiment, the operation of the follow-up monitoring circuit 98 is disabled when the set time arrives, but it is of course possible to enable this operation, and the output T may be directly supplied to the AND gate 54.

As explained above, according to the present invention, the user's heart rate can be gradually and reliably changed, and the user's mental state can be relaxed or tense easily. can.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a timepiece with an alarm function to which a heartbeat sound generator according to the present invention is applied. 2, 3 and 4 are time charts showing the operation of FIG. 1. 14...Guide mechanism, 16...And gate, 1
8...Sound stop switch, 19...Sound generation circuit, 2
0... Heartbeat detection circuit, 26... Heartbeat measurement circuit, 4
2...Initial value setting circuit, 60...Operation control circuit,
80... Arithmetic circuit, 82... Heartbeat signal generation circuit,
98...Following monitoring circuit.

Claims (1)

[Scope of Claims] 1. A heartbeat sound generating device comprising: a heartbeat detection circuit that detects a heartbeat and outputs a detection signal thereof; and a sound generation circuit that converts the detection signal into a sound as a heartbeat signal, wherein the detection signal is a heart rate measuring circuit that measures the heart rate per predetermined time based on the heart rate; and at least two types of external signals are input; outputs an operation start signal in response to the input of the second external signal, and varies the upper or lower limit set value of the heart rate per predetermined time set in advance in response to the second external signal; an operation control circuit that outputs an operation end signal when the heart rate of the heart rate becomes larger or smaller than the upper or lower set value; and a heartbeat cycle received from the heartbeat measurement circuit as an initial value in response to the operation start signal. an initial value setting circuit that counts the reference signal from after the storage operation of the initial value setting circuit until the time when the operation end signal is generated; an arithmetic circuit that adds or subtracts at predetermined time intervals in response to a signal; and a heartbeat signal generation circuit that outputs a heartbeat signal with a period corresponding to the heart rate per predetermined time calculated by the arithmetic circuit to the sound generation circuit. and a follow-up monitoring circuit that further outputs a coincidence signal that operates the counter circuit when the calculated heart rate per predetermined time and the heart rate per predetermined time output by the heart rate measurement circuit match. A heartbeat sound generating device characterized by comprising: 2. In claim 1, the operation control circuit outputs a stop signal after a certain period of time after the operation end signal is generated, and in response to the stop signal, the heartbeat signal generation circuit stops outputting the heartbeat signal to the sound generation circuit. A heartbeat sound generator characterized by: