JPH035173B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a device that generates a heartbeat sound synchronized with the heartbeat cycle and then changes the generation cycle of the heartbeat sound over time, and further relates to a device that changes the generation cycle of the heartbeat sound as time passes. After the heart rate reaches a preset value, the heartbeat sound generation operation is automatically stopped.

(Prior Art) Conventionally, as described in Japanese Patent Application Laid-Open No. 54-98651, a pulse wave, that is, a heartbeat is detected by a pulse wave detection device, and a heartbeat sound corresponding to this detection signal is generated. Measuring devices are known.

By the way, the heart rate under normal conditions is 70-80 beats per minute.
It is known that this number decreases to about 50 to 60 times per minute during sleep or in a state of mental relaxation, and increases to about 90 to 100 times per minute when excited or mentally tense. It is said that it is possible to control one's own heartbeat and mental state by concentrating on a certain sound.

Therefore, if you use such an entrance device while sleeping,
It can easily relieve tension, allowing you to sleep comfortably.

(Problems to be Solved by the Invention) The present invention is a further development of the conventional heart rate measuring device described above, and its purpose is to effortlessly control the mental state of the user and use it, for example, when falling asleep. The purpose is to relieve the user's tension and allow him or her to sleep comfortably, and also to eliminate the need for the user to have to stop the operation of the device after falling asleep.

(Means for Solving the Problems) In order to solve the above problems, the present invention generates a heartbeat sound synchronized with the heartbeat cycle, and then gradually changes the generation cycle of the heartbeat sound. The present invention is characterized in that the heartbeat sound generation operation is automatically stopped after the generation cycle becomes equal to or less than a preset value.

(Embodiments) Preferred embodiments of the present invention will be described below based on the drawings. FIG. 1 shows an embodiment in which a heartbeat sound generating device according to the present invention is combined with a watch with an alarm function.

The oscillation circuit 2, the frequency dividing circuit 4, the waveform shaping circuit 6, the motor 8, the wheel train 10, and the pointer display 12 constitute a conventionally well-known analog timepiece. The reference mechanism 14 is built into the wheel train 10, and supplies the AND gate 16 with an alarm start signal that remains "H" for about 20 minutes when the set time arrives. The AND gate 16 is also supplied with the output of a ring stop switch 18, and when an alarm start signal is generated when the switch 18 is closed, a heartbeat signal is supplied to the sound generation circuit 19 from a heartbeat signal generation circuit 82, which will be described later.
The sound generation circuit 19 is a circuit that converts a heartbeat signal into a heartbeat sound.

The heartbeat detection section 20 detects heartbeats and generates a detection signal corresponding to the heartbeats, and is composed of a heartbeat detection section 22 and a waveform shaping circuit 24. The heartbeat detection unit 22 employs, for example, a photoplethysmogram detection method, in which infrared light emitted by a light emitting diode is applied to a fingertip, and a phototransistor detects reflected light and transmitted light whose light intensity is modulated by blood flow. The waveform shaping circuit 24 shapes the signal from the heartbeat detection section 22 into a square wave with a constant pulse width, and outputs it as a detection signal. These output waveforms are shown in FIG.

The heartbeat measuring circuit 26 measures the cycle of the above-mentioned detection signal every time a certain number of the detection signals are output, and obtains the number of heartbeats occurring per minute from the cycle.
The counter 28 is supplied with the detection signal outputted to output B, and when it counts a certain number (for example, "4"), a carry signal causes the flip-flop (hereinafter referred to as
(referred to as FF) 30 is inverted. This FF3
The output N of 0 is the clock signal φ ₃ from the frequency divider circuit 4.
(10 KHz) and is supplied to the AND gate 32, and if the output N is "H", the clock signal _φ3 is supplied to the period counter 34.
Since the output of the FF 30 is inverted every time the detection signal is output four times, the period counter 34 counts the reference signal φ ₃ only during the period in which the detection signal is output four times, and this count value is the detection signal. This represents the time required for outputting four times. Then, the arithmetic circuit 36 converts the period counter 3
The time required for one heartbeat is determined from the output signal of step 4, and this is further converted into the number of heartbeats occurring per minute.

The initial value setting circuit 42 is a circuit that stores the initial heart rate from the heart rate measuring circuit 26, and when the output Q of the AND gate 44 rises, the calculation circuit 36
The output signal of is stored in the latch circuit 46. In other words, the AND gate 44 is in a set state for 10 seconds from the output O of the FF 30 and the start of operation of this device.
The output P of the FF 48 is supplied, and the output signal of the arithmetic circuit 36 is stored in the latch circuit 46 when the output O is first inverted to "H" after the start of operation.

The count circuit 50 is a circuit that starts counting operation after the initial value setting circuit 42 performs the storage operation. The counter 52 counts the clock signal supplied from the AND gate 54, and the output R of the FF 58 is supplied to the AND gate 54 together with the clock signal selected by the switching gate 56.
A clock signal φ ₁ (1/4 Hz) and a clock signal φ ₂ (1 Hz) from a frequency dividing circuit 59 are supplied to the switching gate 56, and an output D is supplied to the switching control terminal. Then, if the output D is "H", the clock signal φ ₁ is selectively output, and if the output D is "L", the clock signal φ ₂ is selectively output.

The operation control circuit 60 is a circuit that outputs control signals for controlling the operations of the heartbeat measurement circuit 26, the initial value setting circuit 42, the counting circuit 50, and the heartbeat signal generation circuit 82, which will be described later. The single pulses generated from the one-shot circuits 62 and 64 are both supplied to an OR gate 66, whose output F
The single pulse generated at is supplied to the set terminals S of the FFs 38 and 48 as a control signal for starting heart rate counting.

Here, the output L of the FF 38 becomes "H" and the output M becomes "L", and the heartbeat detection circuit 20 starts the detection operation, and the heartbeat measurement circuit 26 also starts the measurement operation. Further, the output P of the FF 48 becomes "H", and the AND gate 44 is opened.

Further, the single pulse generated at the output F prompts the operation of the timer circuit 68, and a single pulse is generated at the output G again after 10 seconds have elapsed. This output G is supplied to the reset terminal R of FF48 and the set terminal S of FF58, and the output P of FF48 is set to "L" to close the AND gate 44, and the output R of FF58 is set to "H" to perform the counting operation of the count circuit 50. start. The one-shot circuit 62 has an output C.
Outputs D are supplied to the one-shot circuits 64, respectively.

Further, the output C is inverted and supplied to the OR gate 70, and the output E of the OR gate 70 is used as a control signal to reset the counter 52 and is sent to the reset terminal R of the counter 52, the heartbeat detection circuit 20, and the heartbeat measurement circuit 26. A control signal for stopping the operation of the FF 38 is supplied to the reset terminal R of the FF 38.

Furthermore, the comparison circuit 72 is a circuit that compares an output signal from an arithmetic circuit 80, which will be described later, and a code signal from the encoder 74. When the output D is "H", the arithmetic circuit 80 compares the value of the code signal from the encoder 74. When the value of the output signal from D becomes large, a single pulse is generated at the output H, and when the output D is "L", conversely, when the value of the output signal becomes small, a single pulse is generated at the output H. In this embodiment, the code signal of the encoder 74 is set to be "80" when the output D is "H" and "50" when the output D is "L". The single pulse generated at the output H is supplied to the reset terminal R of the FF 58 as a control signal for stopping the counting operation of the counting circuit 50.

The output H is also supplied to the set terminal S of the FF75. The FF 75 stores that the calculated value from the arithmetic circuit 80 has reached a preset value, and supplies its output I along with the inverted output D to the AND gate 76. Further, the AND gate 76 is supplied with an output V from a follow-up monitoring circuit 98, which will be described later, and when the AND gate 76 is open and a single pulse is generated at the output V, a single pulse is also generated at the output J. When a single pulse is generated at the output J, the timer circuit 78 is activated, and after one minute has elapsed, a single pulse is generated at the output K, and the single pulse is supplied to the OAND gate 70.
Reset FF75.

The arithmetic circuit 80 is a circuit capable of adding and subtracting the heart rate stored in the initial value setting circuit 42 and the count value of the count circuit 50, and when the output D is "H", the heart rate and the count value are calculated. The output D is
If "L", the count value is subtracted from the heart rate.
The calculated value of the calculation circuit 80 is supplied to the comparison circuit 72, the frequency division ratio converter 84 in the heartbeat signal generation circuit 82, and the comparison circuit 102 in the follow-up monitoring circuit 98.

The heartbeat signal generation circuit 82 is a circuit that generates a heartbeat signal for generating a heartbeat sound with a cycle corresponding to the calculation value of the calculation circuit 80. A programmable counter 86 consisting of 8 bits and a frequency dividing circuit 88 consisting of 8 stages divide the clock signal φ ₄ (32768Hz) from the frequency dividing circuit 4, and the frequency division ratio of the programmable counter 86 is as follows. Frequency division ratio converter 84
The output of the lower 4 bits of the frequency divider circuit 88 is set by the frequency division ratio setting signal from the AND gate 90.
supplied to The frequency division ratio converter 84 is an arithmetic circuit 80
The calculated value is converted into a frequency division ratio setting signal for setting the frequency division ratio necessary for counting the period corresponding to the calculated value, and the relationship between the two is expressed by the following relationship. In other words, the value of the calculated value is N1,
If the value of the frequency division ratio setting signal is N2, the relationship is approximately expressed as N2 = 32768Hz/256÷N1/60sec.

FF92 starts or ends the operation of the heartbeat signal generating circuit 82, and the set terminal S is supplied with an output G, and the reset terminal R is supplied with an output E. The output T of the FF 92 is supplied to the reset terminal R of the programmable counter 86, and the output S together with the clock signal _φ4 is supplied to the clock input φ of the programmable counter 86 via an AND gate 94.

On the other hand, a pulse signal with a duty ratio of 1/16 corresponding to the period setting signal is generated at the output of the AND gate 90, and this output is further supplied to the AND gate 96. The AND gate 96 is also supplied with an audible frequency signal φ ₅ (for example, 2048 Hz) from the frequency dividing circuit 4, and supplies an output U from which a heartbeat signal is generated to the sound generation circuit 19.

The tracking monitoring circuit 98 compares the calculated value from the calculating circuit 80 and the heart rate from the heart rate measuring circuit 26, and generates a coincidence signal at the output V when they match.
The latch circuit 100 stores the heart rate from the arithmetic circuit 36 every time the output O rises to "H", and supplies the stored value to the comparison circuit 102. Comparison circuit 1
In addition, the calculated value from the calculation circuit 80 is also supplied to 02, and the two are compared. When the two match, a single pulse as a mismatch signal is generated at the output V and supplied to the AND gate 76 mentioned above.

In this embodiment, the aforementioned operation control circuit 60
The follow-up monitoring circuit 98 constitutes a heartbeat sound stop circuit.

The present embodiment is constructed as described above, and its operation will be explained below with reference to FIGS. 3 and 4.

At time _t1 , when the ring stop switch 18 is closed, the output E becomes "L", so the counter 52,
FFs 38 and 92 are released from reset and a single pulse from one shot circuit 62 is generated at output F, setting FFs 38 and 48. Therefore, the heartbeat detection circuit 20 and the heartbeat measurement circuit 26 start operating.

At time _t2 , when a predetermined detection signal is output from the heartbeat detection circuit 20, the output N of the FF 30 is
From "H" to "L", output O goes from "L" to "H"
Since the count value of the period counter 34 is reversed, the counting operation of the period counter 34 is stopped, and the number of heartbeats occurring in one minute, which is converted based on the count value of the counter 34, is stored in the latch circuits 46 and 100. Note that at this point, the count value of the counter 52 is "0".

Then, at time t ₃ , which is 10 seconds after time t ₁ , a single pulse is output from the timer circuit 68 to the output G, so even if the FF 48 is reset and the output O rises to "H" thereafter, the latch remains unchanged. The contents of circuit 46 cannot be changed. Further, since FFs 58 and 92 are set, the operation of the count circuit 50 and heartbeat signal generation circuit 82 is started. Here the output D
Since the clock signal φ 2 is “L”, the counter 52 is supplied with the clock signal φ ₂ . When the clock signal φ ₂ is supplied to the counter 52, the calculation value is subtracted by the calculation circuit 80.

In the heartbeat signal generation circuit 82, the arithmetic circuit 8
A heartbeat signal with a period corresponding to the calculated value of 0 is generated. For example, if the calculated value is "70", this is converted to "110" by the frequency division ratio converter 84 and preset in the programmable counter 86. Therefore, a heartbeat signal with a period of 0.86 seconds is generated at the output S, and as a result, a heartbeat sound is generated by the sounding circuit 19 at the same period.

Of course, since the counting operation in the counting circuit 50 continues, the calculated value from the arithmetic circuit 80 naturally decreases, and therefore the generation cycle of the heartbeat signal generated from the heartbeat signal generation circuit 82 becomes longer. For example, if the calculated value is "60", a frequency division ratio of "128" is set in the programmable counter 86, the period of the heartbeat signal is 1 second, and the period of the heartbeat sound is also 1 second.

Similarly, it will be understood that the generation cycle of heartbeat sounds becomes longer as time passes.

On the other hand, the heart rate measurement circuit 26 constantly performs measurement operations, and every time a predetermined detection signal is output, the FF30
The latest heart rate is stored in the latch circuit 100 each time the output O rises to "H".

Then, at time _t4 , when the calculated value from the calculation circuit 80 becomes "50" or less, a single pulse is output to the output H of the comparison circuit 72, so the FF 58 is reset and the counting operation of the counting circuit 50 is stopped. Thereafter, the generation cycle of the heartbeat sound will no longer change.
At the same time, FF75 is set and output I is "H"
Therefore, the AND gate 76 becomes open. Thereafter, at time _t5 , when the heart rate from the heart rate measurement circuit 26 and the calculated value from the calculation circuit 80 match, the follow-up monitoring circuit 98 detects this and generates a single pulse at the output V. Therefore, a single pulse is also generated at output J via AND gate 76, which is open, thereby resetting FF 75 and prompting timer circuit 78 to operate. Then, at time _t6 after one minute has elapsed, the single pulse generated at output K is generated at output E via OR gate 70, and FF3
8 and 92 are reset, the heartbeat detection operation, heartbeat measurement operation, and heartbeat sound generation operation are stopped, and the contents of the counter 52 are also cleared.

On the other hand, when the set time arrives at time _t7 , the output D becomes "H" due to the alarm start signal from the reference mechanism 14, and the one-shot circuit 6 is connected to the output F.
A single pulse from 4 is generated. Therefore, the initial heart rate of the initial value setting circuit 42 is stored in the same manner as the operation from time _t1 to time _t2 . and time t ₉
When this happens, a single pulse from the timer circuit 68 is output to the output G, and the counting circuit 50 and the heartbeat signal generation circuit 82 start operating.

If the heart rate stored in the initial value setting circuit 42 at time _t8 is, for example, "50", then the time
At _t9 , the frequency division ratio setting signal becomes "154", so a heartbeat signal with a period of about 1.2 seconds is generated at the output S.
Also, since the output D is "H" at this time, the counter 5
2 is supplied with the clock signal _φ1 , and the arithmetic circuit 8
0 acts to add the heart rate stored in the initial value setting circuit 42 and the count value of the counter 52. For example, if the clock signal _φ1 is set to 1/2Hz, the value of the frequency division ratio setting signal is 2.
It will become smaller every second. Therefore, as the frequency division ratio preset in the programmable counter 86 becomes smaller, the generation period of the heartbeat signal generated at the output S and the generation period of the heartbeat sound generated from the sound generation circuit 19 become shorter. For example, after 30 seconds have passed from time _t9 , the count value of the counter 52 is "15", the calculated value from the calculation circuit 80 is "65", and the division ratio setting signal is "118", so the output is The period of the pulse signal generated at S is approximately 0.92 seconds, and similarly the period of generation of the heartbeat sound is approximately 0.92 seconds. It will be understood that the generation cycle of the heartbeat sound gradually becomes shorter in the same manner.

Then, at time _t10 , when the calculated value from the calculation circuit 80 becomes "80" or more, a single pulse is output to the output H of the comparison circuit 72, so the FF 58 is reset and the counting operation of the counting circuit 50 is stopped. . Therefore, the generation cycle of the heartbeat sound does not change thereafter.

Then, at time _t11 , when the ring stop switch 18 is opened, the output E becomes "H", so the FF38
and 92 are reset, the heartbeat detection operation, heartbeat measurement operation, and heartbeat sound generation operation are stopped, and the contents of the counter 52 are also cleared.

(Effects of the Invention) As described above, according to the present embodiment, the heartbeat sound generating device according to the present invention is combined with a watch with an alarm function, and after setting the alarm, the heartbeat sound synchronized with the heartbeat cycle is generated. By lengthening the generation cycle of the heartbeat sound over time, it gradually reduces the user's heartbeat and relaxes the user's mental state, so it is possible to induce a comfortable sleepiness in the user, and the heartbeat sound After the calculated value corresponding to the occurrence cycle of has decreased to a preset value, especially in this embodiment, the heart rate of the user matches the calculated value, and it is sensed that the user's mental state has completely relaxed. Since the heartbeat sound generation operation is automatically stopped afterwards, it is possible to surely relax the mental state, and it is also possible to prevent the user from having to stop the heartbeat sound generation operation when the user is in a relaxed state. It does not make the user worry, and therefore it is possible for the user to fall asleep with peace of mind.

In addition, when the set time arrives, a heartbeat sound synchronized with the heartbeat cycle is generated, and then the cycle of the heartbeat sound is shortened as time passes, gradually increasing the user's heartbeat and normalizing the mental state. Because it works to put you in a state of , it can induce a comfortable awakening.

Although this embodiment has been described in which the present device is incorporated into an alarm clock, it is of course possible to provide an external switch in place of the ring stop switch 18 and operate it independently.

As described above, according to the present invention, the mental state is gradually relaxed by generating a heartbeat sound synchronized with the heartbeat cycle and further changing the generation cycle of the heartbeat sound over time. can be made more intense, tense, or closer to normal.
It is possible to easily control the user's mental state, and when falling asleep, the heartbeat sound generation operation is automatically stopped after the user's mental state has relaxed, so the user does not have to worry about any unnecessary necessities. It is possible to make the patient sleep with peace of mind without having to worry about it.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a timepiece with an alarm function to which a heartbeat sound generator according to the present invention is applied. 2, 3 and 4 are time charts showing the operation of FIG. 1. 14...Guide mechanism, 16...And gate, 1
8...Sound stop switch, 19...Sound generation circuit, 2
0... Heartbeat detection circuit, 26... Heartbeat measurement circuit, 4
2...Initial value setting circuit, 60...Operation control circuit,
80... Arithmetic circuit, 82... Heartbeat signal generation circuit,
98...Following monitoring circuit.

Claims (1)

[Scope of Claims] 1. A heartbeat sound generating device comprising: a heartbeat detection circuit that detects a heartbeat and outputs a detection signal thereof; and a sound generation circuit that converts the detection signal into a sound as a heartbeat signal, wherein the detection signal is a heart rate measuring circuit that measures the heart rate per predetermined time based on the heart rate; a follow-up monitoring circuit that outputs a matching signal when the heart rate and the heart rate per predetermined time of the heartbeat signal match; and at least two types of external devices. input the signal, output an operation start signal in response to input of the first external signal or input the second external signal when the first external signal is input, and output the operation start signal in response to the input of the second external signal. When the heart rate per predetermined time of the heartbeat signal becomes larger or smaller than the upper or lower limit set value, an operation end signal is generated. and an operation control circuit that outputs a stop signal when the coincidence signal is received after the operation end signal is generated, and a heart rate per predetermined time from a heart rate measurement circuit in response to the operation start signal as an initial value. an initial value setting circuit for storing, a count circuit for counting the reference signal from after the storage operation of the initial value setting circuit until the time when the operation end signal is generated, and a second
an arithmetic circuit that adds or subtracts at regular time intervals in response to an external signal; and a heartbeat signal having a period corresponding to the heart rate per predetermined time calculated by the arithmetic circuit, and outputs the heartbeat signal to the sound generation circuit and outputs the stop signal to the stop signal. A heartbeat sound generating device comprising: a heartbeat signal generation circuit that stops outputting the heartbeat signal in response.