JPH0352093B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an arithmetic device, and particularly to an arithmetic device for calculating the mantissa part of a floating point arithmetic operation.

2. Description of the Related Art In general, a normalized floating-point number is composed of a sign indicating its sign, an exponent part, and a mantissa part having a normalized absolute value. When the mantissa part is all "0" as a result of such an operation between a floating point number and another floating point number, the sign, exponent part, and mantissa part are all "0" (hereinafter referred to as normalized 0). ) is often required as the result of an operation.

In such a case, detect whether all the mantissa operation results are “0” at the time when the operation result is determined,
If all are "0", normalized 0 is taken as the calculation result.

FIG. 3 shows a conventional arithmetic device that performs the above-described processing.

The first one, designated by the reference numeral 1' in FIG.
The operations from the operand storage register to the mantissa operation result storage register indicated by the reference numeral 11' are performed in the same manner as the elements with the corresponding reference numerals in an embodiment of the present invention, which will be described later. The operation result of the mantissa part of the two operands is stored in the operation result storage register 11'.

After the calculation result of the mantissa part is determined uniquely in this way, the 0 detection circuit 12' detects that all the calculation results are "0".
If they are all "0", "1" is stored in the zero detection result storage flip-flop 17'.

Problems to be Solved by the Invention However, in the above-mentioned conventional example, the operation result cannot be expressed as "0'' detection has already started, so there is a drawback that the computation time is long.

The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the conventional technology, and therefore, the purpose of the present invention is to calculate |A+B| or |A-B| and the result of the calculation is all "0". It is an object of the present invention to provide a novel arithmetic device that can shorten the computation time of absolute value computation by overlapping the operation of detecting the above.

Means for Solving the Problems In order to achieve the above object, the arithmetic device according to the present invention performs an arithmetic operation on a carry input “1” from a lower order, and detects a value “0” corresponding to the result of this operation. a first detection circuit, a second detection circuit that performs an operation on a carry input "0" from the lower order, and detects the complement of each digit of the value corresponding to the operation result as "0"; , a first selection circuit that selects one of the outputs of the second detection circuit in response to the carry generated by the calculation result, and a calculation of the carry input "0" from the lower order, and based on the calculation result. The third one detects “0” of the corresponding value.
a detection circuit, and the output of this third circuit or the first detection circuit.
and a second selection circuit configured to select the output of the selection circuit according to an operation instruction.

Embodiment Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, one embodiment of the present invention includes a first operand storage register 1, an inverter 2, a selection circuit 3, a second operand storage register 4, an operation instruction storage flip-flop 5, and an arithmetic unit 6 with a carry input "1". , a carry input "0" arithmetic unit 7, an inverter 8, selection circuits 9, 10, 15, 16, 0 detection circuits 12, 13, 14, an operation result storage register 11, and a 0 detection result storage flip-flop 17.

Now, in this embodiment, the calculation of the first operand expressed as an absolute value and the second operand expressed as an absolute value is performed as follows.

Now, set the first operand to A and the second operand to B.
Then, A≧0 and B≧0. The operation we will perform from now on is addition A+ under the conditions of A≧0 and B≧0.
B or subtraction A-B to obtain the positive/negative information of the result, and the absolute value of the addition result |A
+B| or the absolute value |AB| of the subtraction result, and detecting that |A+B| and |AB| are all "0".

First, the first operand A is stored as is in the first operand storage register 1. On the other hand, when the operation instruction signal 100 is "0" indicating addition, the second operand B is selected as it is by the selection circuit 3, and when the operation instruction signal 100 is "1" indicating subtraction, the inverter selects the second operand B. 2 and each digit is “1”,
The inverted value of "0", that is, the complement B of "0" is selected and stored in the second operand storage register 4.

In this way, A and B stored in register 1 and register 4 are added by arithmetic unit 6 and arithmetic unit 7. However, the arithmetic unit 6 performs addition when there is a carry to the minimum digit (carry input "1"), that is, it performs addition of A+B+1 for addition and A++1 for subtraction.

On the other hand, the arithmetic unit 7 side performs addition when there is no carry to the minimum digit (carry input "0"),
In other words, when adding, A+B, when subtracting, A+
, and the inverter 8 inverts the "1" and "0" of each digit of the addition result to create its complement (that is, + for addition, A+ for subtraction).

A+B+1 or A++1 thus obtained
The output 6000 that should give , and the output 8000 that should give (+) or (A+) are led on the one hand to the respective inputs of the selector 9, and on the other hand, they are respectively guided to the respective inputs of the selector 9, which respectively indicate that A+B+1 or A++1 are all "0". 0 detection circuit 12 to detect
and (+) or (A+) are all “0”
is led to a 0 detection circuit 13 that detects that
The respective results of 0 detection in this manner are led to respective inputs of the selection circuit 15. Also, A+B
The output 7000 to give A+ is led on the one hand to the 0 detection circuit 14 and on the other hand to one input of the selection circuit 10. The output of the selection circuit 9 is led to the other input of the selection circuit 10. The output of the 0 detection circuit 14 is sent to the selection circuit 1.
6, and the output of the selection circuit 15 is guided to the other input. In the calculation instruction storage flip-flop 5, “0” is stored during addition.
“1” is stored during subtraction.

Now, when performing addition, the second operand B is stored in the second operand storage register 4 as described above.
is stored as is, and the arithmetic unit 7 outputs the result of the above-mentioned A+B operation to the signal line 7000,
The 0 detection circuit 14 detects whether all are "0" and outputs "1" to the signal line 14000 if all are "0" and "0" if not all "0". When the output 5000 of the operation instruction storage flip-flop 5 is "0", addition is instructed, and the selection circuit 10 connects the signal line 7000 and the selection circuit 16 connects the signal line 140.
00 respectively and select operation result storage register 1.
1 and 0 detection storage flip-flops 17 respectively.

When performing subtraction, the complement B of the second operand B is stored in the second operand storage register 4 as described above. When arithmetic unit 7 performs operation A+, an overflow occurs and a carry is output from the most significant digit, and this carry output is guided to selectors 9 and 15 via signal line 7001. As a result, the selector 9 outputs A++1 of the output 6000 of the computing unit 6 when the carry is output to the carry output 7001.
and if the carry does not output to the carry output 7001, select (A+) of the output 8000 from the inverter 8, and send the selected output of these to the signal line 9000 to the selector 10. Enter via. The selector 10 instructs subtraction when the output 5000 of the operation instruction storage flip-flop 5 is "1", selects the signal line 9000, and stores it in the operation result storage register 11.

On the other hand, the selector 15 similarly outputs the carry output 7001.
When the carry outputs to the carry output 7001, the 0 detection result of A++1 from the 0 detection circuit 12 is selected, and when the carry does not output to the carry output 7001, the 0 detection result is selected.
The 0 detection result of (A+) from the detection circuit 13 is selected, and the output of the selected one of these is input to the selector 16 via the signal line 1500. The selector 16 selects the signal line 1500 when the signal line 5000 is "1" and stores it in the 0 detection result storage flip-flop 17.

By the above processing, carry output 7001 during subtraction
outputs the positive/negative information of the operation result of A-B (indicates positive if there is a carry output, negative if there is no carry output), and the output 1100 of register 11 is the absolute value of the addition result |A+B| or the subtraction result absolute value of |A
-B|, and output 1700 of register 17
outputs the 0 detection result of the absolute value |A+B| of the addition result or the 0 detection result of the absolute value |A-B| of the subtraction result. In this way, the addition of A+B or A
This means that all the results necessary for subsequent processing have been obtained in the subtraction of -B.

Next, an example in which the operation that overlaps between the arithmetic unit and the 0 detection circuit is performed is shown on the arithmetic unit side of the carry input "0" (the arithmetic unit 7, inverter 8, and 0 detection circuit 13 in FIG. 1). 14) will be exemplified.

In this example, the bit width of the data to be calculated is divided into two (for example, in a 16-bit width calculation, the upper 8 bits and the lower 8 bits are divided into 2 parts).
(divided into equal parts), and the operation on the lower digit side and the operation on the upper digit side are performed simultaneously and in parallel. However, the calculation on the high-order digit side has both the calculation when there is a carry from the low-order digit side and the calculation when there is no carry from the low-order digit side, regardless of the carry from the low-order digit side. When a carry actually appears from the lower digit, the correct one is selected depending on the presence or absence of an actual carry and is used as the final output. Such a method can greatly reduce calculation time.

FIG. 2 is a block diagram specifically showing the configuration of the arithmetic unit 7, the inverter 8, and the 0 detection circuits 13 and 14, which operate as described above. The calculator 72 is an arithmetic unit on the upper digit side when there is no carry from the lower digit side, and the arithmetic unit 73 is an arithmetic unit on the upper digit side when there is a carry from the lower digit side. 82 and 8
3 are inverters that take the complements of the outputs of the arithmetic units 71, 72, and 73, respectively, and 0 detection circuits 131 and 132.
is a circuit that detects whether all of the complements of the calculation results are "0" when the calculation is performed assuming that there is no carry from the lower digits beforehand, and when the calculation is performed assuming that there is a carry from the previous digit, respectively, and a 0 detection circuit. 141 and 142 are circuits for detecting whether the calculation results are all "0" when there is a carry or not, and switchers 74, 75, 76, 133 and 143 respectively detect from the lower digits. If there is a Carry 7100, select and output each calculation result on the side that was calculated assuming that there was a Carry, and if there is no Carry 7100, select and output the calculation results on the side that was calculated as if there was no Carry. This is a selection circuit that selects and outputs each calculation result.

The operation of the portion shown in FIG. 2 will be easily understood by referring to the following description and FIG.

Note that in the above example, the total bit width of the data to be computed is divided into two equal parts, and the upper digits are computed in parallel with and without carry from the lower digits. , instead of this, the number of divisions is increased further, and for all but the lowest digits,
It is also possible to perform parallel calculations in advance with and without carry from the least significant digit, and select the correct combination from the results based on the carry output from the least significant digit. can.

Effects of the Invention As explained above, the present invention overlaps the operation of |A+B| or |A-B| with the operation of detecting that the operation results are all "0", thereby detecting the absolute value. This has the effect of shortening the computation time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an example block diagram for explaining a part of the embodiment in detail, and FIG. 3 is a block diagram showing a conventional example. be. 1...First operand storage register, 2, 8...
...Inverter, 3, 9, 10, 15, 16... Selection circuit, 4... Second operand storage register, 5...
Arithmetic instruction storage flip-flop, 6...Arithmetic unit with carry input "1", 7...Carry input "0"
Arithmetic unit, 12, 13, 14...0 detection circuit, 1
1...Arithmetic result storage register, 17...0 detection result storage flip-flop, 71, 72, 73...
Arithmetic unit, 81, 82, 83... Inverter, 131,
132, 141, 142...0 detection circuit, 74,
75, 76, 133, 143... selection circuit.

Claims (1)

[Claims] 1. In an arithmetic device having a function of performing floating point arithmetic, a first detection circuit that performs an arithmetic operation on a carry input "1" from a lower order and detects that all values corresponding to the result of this arithmetic operation are "0"; ,
a second detection circuit that performs an operation on the carry input “0” from the lower order and detects that the complements of each digit of the value corresponding to the operation result are all “0”;
A first selection circuit that selects the output of either the first or second detection circuit in response to a carry generated by the calculation result, and a carry input "0" from a lower order are operated. a third detection circuit that detects that all values corresponding to the calculation results are "0"; this third detection circuit and the first detection circuit;
and a second selection circuit configured to select one of the outputs of the selection circuits in response to an operation instruction signal.