JPH0150930B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic device, and particularly to an arithmetic device for performing arithmetic operations on the mantissa part of floating point arithmetic operations.

Generally, a normalized floating-point number is composed of a sign indicating its sign, an exponent part, and a mantissa part having a normalized absolute value.

In such floating point number operations, it is often necessary to subtract the absolute value of one floating point number from the absolute value of another floating point number and normalize the result.

In this case, first shift the mantissa of the number with the smaller exponent part to the right until the exponent of the number with the larger exponent part is equal to the exponent of the number with the smaller exponent part, and then shift the mantissa of the number with the smaller exponent part to the right. Performs subtraction in the specified order between the absolute values of the parts.

In this subtraction, the sign of the obtained result is determined, its absolute value is determined, and an operation is performed to normalize this absolute value.

To perform this normalization, the number of “0”s (hereinafter referred to as leading 0) from the most significant digit is counted until a “1” bit appears in the first digit of the number representing the absolute value resulting from the subtraction. need to be counted.

In the conventional device, as will be explained in detail later, the operation of counting the number of leading 0s is started after the above-mentioned absolute value subtraction is completed and the absolute value of the result is uniquely determined. The disadvantage is that the calculation time is long.

SUMMARY OF THE INVENTION An object of the present invention is to provide an arithmetic device which eliminates the above-mentioned conventional drawbacks.

The device of the present invention is an arithmetic device having a function of performing absolute value calculation and normalizing the result of the calculation, and calculates a carry input "1" from the lower order and returns a leading "0" of the value corresponding to the result of this calculation. A circuit for counting, a circuit for calculating the carry input “0” from the lower order and counting the leading “0” of the complement of each digit of the value corresponding to the result of this calculation, and an output of either of these two circuits. and a selection circuit configured to select a carry in response to a carry generated by the calculation result.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In this embodiment, the first operand storage register 1,
Second operand storage register 2, arithmetic unit 3 with carry input “1”, arithmetic unit 4 with carry input “0”, inverter 5, selectors 6, 10, operation result storage register 7, leading 0 count circuit 8, 9 and count number holding register 11.

Now, in this embodiment, subtraction of subtracting the second operand expressed in absolute value from the first operand expressed in absolute value is performed as follows.

Now, set the first operand to A and the second operand to B.
Then, they are A0 and B0.

The calculation we will perform from now on is to perform subtraction A-B under the conditions of A0 and B0, obtain information on the positive and negative of the result, and the absolute value of the subtraction result |A-
The two tasks are to obtain B| and to obtain the number of leading 0s appearing in this |AB|.

The first operand A is stored in the first operand storage register 1 as is. On the other hand, the second operand B is the inversion of “1” and “0” in each digit,
That is, the complement of B is stored in the second operand storage register 2.

A and thus stored in register 1 and register 2 are added by arithmetic unit 3 and arithmetic unit 4, respectively.

However, when there is a carry to the minimum digit (carry input "1"), the arithmetic unit 3 performs addition with A, that is, addition of A++1.

On the other hand, on the side of the arithmetic unit 4, when there is no carry to the minimum digit (carry input "0"), addition of A+,
That is, ordinary addition of A+ is performed, and the inverter 5 inverts the "1" and "0" of each digit of the addition result to create its complement (that is, (+)).

The output that should give A++1 obtained in this way
The power output 5000 that gives 3000 and (+) is
On the one hand, they are led to the respective inputs of the selector 6, and on the other hand, to a leading 0 count circuit 8, which counts the leading 0 of A++1, and a leading 0 count circuit 9, which counts the leading 0 of (+), respectively. , the respective leading zero numbers thus counted are led to respective inputs of the selector 10.

Now, when arithmetic unit 4 performs the above-mentioned operation A+, an overflow occurs and a carry is output from the most significant digit, and this carry output is led to selectors 6 and 10 via line 4000. As a result, the selector 6 selects A++1 of the output 3000 of the arithmetic unit 3 when the carry is output to the carry output 4000, and selects the output 5000 from the inverter 5 when the carry is not output to the carry output 4000. of (+
B) is selected, and the output of the selected one of these is stored in the calculation result storage register 7.

On the other hand, the selector 10 similarly selects the output that counts the leading 0 of A++1 from the count circuit 8 when the carry output is output to the carry output 4000, and when the carry output is not output to the carry output 4000, the selector 10 selects the output that counts the leading 0 of A++1 from the count circuit 8. From circuit 9 (
+B) is selected, and the selected output is stored in the count holding register 11.

With the above processing, the carry output 4000 is A-B
It outputs the positive/negative information of the operation result (if there is a carry output, it is positive, otherwise it is 0 or negative), and the output 7000 of register 7 outputs the absolute value of the subtraction result |A-B| , and the output 1100 of the register 11 outputs the number of leading zeros of the absolute value |AB| of the subtraction result. In this way, all the results necessary for the subsequent processing are obtained in the AB subtraction.

The reason why the above-described processing can correctly obtain the necessary results is as follows.

First, assume that A>B.

In the case of B0, the complement of B is equal to the number obtained by subtracting B from the number in which all digits of the arithmetic unit are "1" (hereinafter expressed as F).

That is, in the case of B0, =F-B... (1). Therefore, A+=A+F-B=F+(A-B), but since A-B>0, a positive number is added to F, and A+ will always overflow and produce a carry, so the output 4000 if the result is positive (0
or non-negative).

Next, A+=F+A-B =F+1-1+A-B From this, A++1=F+1+A-B, but since F+1 represents the carry coming from the higher rank, A++1=A-B+the carry coming from the higher rank.
...(2) becomes.

In other words, when A>B, A+, that is, the output 4000 of the arithmetic unit 4 will always be a carry, and as a result, the selector 6 will change the output 3000 of the arithmetic unit 3 to A++.
1 is selected, which means A-B=|A-B|
This means that the absolute value of B is correctly output (the carry from the upper part of the arithmetic unit 3 is ignored).

Also, at this time, the selector 10 selects A++.
Since the output 8000 on the side of the count circuit 8 which counts the leading 0 of 1 is selected, this also correctly outputs the leading 0 of the absolute value of A-B.

From the above, it can be seen that all outputs are correct when A>B.

Next, assuming AB, the following will be obtained.

As before, using equation (1), A+=A+F-B A+=F-(B-A)...(3). However, (B-A) is 0 according to the above assumption.
Or, since it is a positive number, subtracting (B-A) from F will not result in a carry.

Therefore, in this case, the result of the operation of A+ in the arithmetic unit 4 does not produce a carry from the upper digits, and the output 4000 correctly outputs information indicating that the result is 0 or negative.

Next, if we use (B-A) instead of B in equation (1), (-)=F-(B-A)...(4) If we use the relationship in equation (3), we get A+= (B-A) ∴(-)=B-A=|A-B|. As mentioned above, the output 4000 does not output carry, and therefore the selector 6 selects the output 5000 (+
B) is selected, which correctly represents the absolute value of AB, as is clear from the above equation.

Also, at this time, the selector 10 selects (+)
Count circuit 9 that counts the leading 0 of
Since the side output is selected, this is also correct A-B.
The absolute value of leading 0 will be output.

Thus, it can be seen that the above process gives correct results both in the case of A>B and in the case of AB.

Now, in this embodiment, a count circuit 8 that counts leading 0 of A++1,
As a result of providing a separate count circuit 9 for counting the leading 0 of (A+B), it is not only possible to perform the operation of A++1 and the operation of (+) in parallel, but also to count the operation of A++1 and the leading 0 of A++1. The operations for (+) and (+) are performed in an overlapping manner.
The operation of counting the leading 0 in B) is performed in an overlapping manner, and at the time when the carry 4000 is output from the arithmetic unit 4, the calculation of the leading 0 by the circuit 8 and the calculation of the leading 0 by the circuit 9 have sufficiently progressed. Hey, this Cary
When 4000 comes out, not only will you get |A-B| in register 7, but you will also get |A-B| in register 11.
It is also possible to obtain the results of counting the leading zeros almost simultaneously.

This advantage of this embodiment becomes especially clear when compared with the conventional example.

FIG. 2 shows a conventional arithmetic unit that performs the same processing as in the above-described embodiment.

The first operand storage register 1' with reference numeral 1' to 7' in FIG. 2 perform the same operations as the elements with the corresponding reference numerals in the previous embodiment.

Therefore, as is clear from the above explanation, the correct operation result of |AB| is output to the operation result storage register 7' at the time when the carry 4000' is output from the arithmetic unit 4'.

In this way, after the value of |A−B| is uniquely determined, the leading 0 count circuit 12
Start counting the leading 0 of A-B｜,
The count result is stored in count storage register 1.
Output to 1'.

As a result, in the conventional example, the counting of the leading 0 is started only after the operation of |A-B| is completed and the correct result is uniquely given, and the operation of |A-B| It cannot overlap with the operation of , and it is necessarily a vertically controlled operation.

Therefore, it is clear that the calculation time of the embodiment of the present invention is shorter.

In fact, in the conventional device, the leading 0 is counted after the calculation result of |A-B| is determined, so the calculation cycle and the leading 0 are counted.
Two counting cycles are required, but
According to the embodiment of the present invention, it is possible to count up to leading 0 in one cycle.

Next, we will explain an example of overlapping operations between the arithmetic unit and the leading 0 count circuit. The following is an example of the including side).

In this example, the bit width of the data to be calculated is divided into two (for example, in a 16-bit width calculation, the upper 8 bits and the lower 8 bits are divided into 2 parts).
(divided into equal parts), and the operation on the lower digit side and the operation on the upper digit side are performed simultaneously and in parallel. However, the calculation on the high-order digit side has both the calculation when there is a carry from the low-order digit side and the calculation when there is no carry from the low-order digit side, regardless of the carry from the low-order digit side. When a carry actually appears from the lower digit, the correct one is selected depending on the presence or absence of an actual carry and is used as the final output. Such an orientation can greatly reduce calculation time.

FIG. 3 shows the configuration of the arithmetic unit 4, inverter 5, and leading 0 count circuit 9 that operate as described above. The arithmetic unit on the upper digit side when there is no carry from the side, and the arithmetic unit 43
are the arithmetic units, inverters 51, 52, and 53 on the upper digit side when there is a carry from the lower digit side.
are an inverter and a leading 0 count circuit 91 that take the complements of the outputs of the arithmetic units 41, 42, and 43, respectively.
and 92 are circuits for calculating the leading 0 of the calculation result when the calculation is performed assuming that there is no carry from the lower digits in the front, and when the calculation is performed assuming that there is a carry in the front, respectively;
4, 45, and 93 respectively select and output the calculation results on the side calculated assuming that there is a carry before when there is a carry 4100 from the lower digit, and when there is no carry 4100, This is a selector that selects and outputs each calculation result on the side calculated assuming that there is no carry.

The operation of the portion shown in FIG. 3 will be easily understood by referring to the above explanation and FIG. 1.

Note that in the above example, the total bit width of the data to be computed is divided into two equal parts, and the upper digits are computed in parallel with and without carry from the lower digits. , instead of this, the number of divisions is further increased, and for digits other than the least significant digit, calculations are performed in parallel with and without carry from the least significant digit, and It is also possible to select the correct combination from among these results by using the carry output.

As described above, the present invention has the effect of shortening the calculation time for absolute value subtraction in an arithmetic device having the function of performing absolute value calculation and normalizing the result of the calculation.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a block diagram showing a conventional example, and FIG. 3 is a block diagram for explaining a part of the embodiment in detail. In the figure, 1...first operand storage register, 2...second operand storage register, 3...
Arithmetic unit with carry input "1", 4...Arithmetic unit with carry input "0", 6, 10...Selector, 7...
Operation result storage register, 8, 9... Leading 0 count circuit, 11... Count number holding register, 41, 42, 43... Arithmetic unit, 51, 52,
53...Inverter, 91,92...Leading 0
Count circuit, 44, 45, 93...selector.

Claims (1)

[Scope of Claims] 1. In an arithmetic device having a function of performing absolute value calculation and normalizing the result of the calculation, a calculation is performed on a carry input “1” from a lower order, and a value corresponding to the result of this calculation is read “0”.
, a circuit that calculates the carry input “0” from the lower order and counts the leading “0” of the complement of each digit of the value corresponding to the result of this calculation, and one of these two circuits. An arithmetic device comprising: a selection circuit configured to select an output in response to a carry generated by the arithmetic result.