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JPH0352256B2 - - Google Patents
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JPH0352256B2 - - Google Patents

Info

Publication number
JPH0352256B2
JPH0352256B2 JP57023553A JP2355382A JPH0352256B2 JP H0352256 B2 JPH0352256 B2 JP H0352256B2 JP 57023553 A JP57023553 A JP 57023553A JP 2355382 A JP2355382 A JP 2355382A JP H0352256 B2 JPH0352256 B2 JP H0352256B2
Authority
JP
Japan
Prior art keywords
gate
self
extinguishing semiconductor
arc
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57023553A
Other languages
Japanese (ja)
Other versions
JPS58142627A (en
Inventor
Yukinori Tsuruta
Kosaku Ichikawa
Nagataka Seki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP57023553A priority Critical patent/JPS58142627A/en
Publication of JPS58142627A publication Critical patent/JPS58142627A/en
Publication of JPH0352256B2 publication Critical patent/JPH0352256B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/72Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region
    • H03K17/722Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region with galvanic isolation between the control circuit and the output circuit
    • H03K17/723Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region with galvanic isolation between the control circuit and the output circuit using transformer coupling

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Power Conversion In General (AREA)
  • Thyristor Switches And Gates (AREA)
  • Electronic Switches (AREA)

Description

【発明の詳細な説明】 (a) 技術分野の説明 本発明は、低耐圧の光結合素子を使用してオン
ゲート電流供給用トランジスタのスイツチングを
可能とした自己消弧形半導体素子のゲート回路に
関するものである。
[Detailed Description of the Invention] (a) Description of the Technical Field The present invention relates to a gate circuit for a self-extinguishing semiconductor device that enables switching of an on-gate current supply transistor using a low breakdown voltage photocoupler. It is.

(b) 従来技術の説明 従来のターンオフサイリスタ(以下、GTOと
略称)のゲート回路を第1図につき説明すれば、
スイツチング電源2は、パルストランス1を介し
てGTO16にターンオン用のゲート電流を供給
するオンゲート回路17、および該GTO16の
ターンオフ期間中、ゲート電極を負にバイアスす
るための負バイアス回路21、にゲート電力を供
給する。オーンゲート回路17は、ダイオード
3,4、平滑コンデンサ7、により整流平滑化さ
れ、NPNトランジスタ12のオン、オフにより、
抵抗体13を介してオンゲート電流を供給する。
NPNトランジスタ12は、フオトカプラ11に
より与えられるベース信号により、オン、オフが
制御される。負バイアス回路21は、ダイオード
5,6平滑コンデンサ8により整流平滑化され抵
抗体15を介してGTO16のゲート電極を負に
バイアスする。GTO16は、第2図に示すゲー
ト信号により制御される。オン指令が入ると、フ
オトカプラ11を介してNPNトランジスタ12
にベース信号が与えられ、オンゲート電流が供給
される。ある一定時間オン指令出力後、フオトカ
プラ11、トランジスタ12のスイツチング時間
を考慮して決定される時間Td経過後、オフ指令
が与えられ、オフゲート電流が供給される。
(b) Description of prior art The gate circuit of a conventional turn-off thyristor (hereinafter abbreviated as GTO) will be explained with reference to Figure 1.
The switching power supply 2 supplies gate power to an on-gate circuit 17 that supplies gate current for turn-on to the GTO 16 via the pulse transformer 1, and a negative bias circuit 21 that biases the gate electrode negatively during the turn-off period of the GTO 16. supply. The on-gate circuit 17 is rectified and smoothed by the diodes 3 and 4 and the smoothing capacitor 7, and is turned on and off by the NPN transistor 12.
An on-gate current is supplied through the resistor 13.
The NPN transistor 12 is controlled to be turned on or off by a base signal given by the photocoupler 11. The negative bias circuit 21 is rectified and smoothed by diodes 5 and 6 and a smoothing capacitor 8, and negatively biases the gate electrode of the GTO 16 via a resistor 15. GTO 16 is controlled by a gate signal shown in FIG. When the ON command is input, the NPN transistor 12 is connected via the photocoupler 11.
A base signal is applied to the on-gate current. After an on command is output for a certain period of time, an off command is given and an off gate current is supplied after a time Td determined by taking into account the switching time of the photocoupler 11 and transistor 12 has elapsed.

GTO16は、オフ指令に応じて、オフゲート
回路18により、パルストランス19を介して与
えられるオフゲート電流によりターンオフする。
GTO16のゲート電極・カソード電極間インピ
ーダンスは、オフゲート電流供給開始後も、
GTO16がまだ導通している蓄積時間内におい
ては、ほぼインピーダンス零であるが、GTO1
6がターンオフすると、ゲート電極・カソード電
極間には、20〜30V程度の誘起逆スパイク電圧が
発生する。第3図は、この時の等価回路である。
第1図と同一部分には、同一の符号を付して、そ
の説明を省略する。オフゲート電流供給用のパル
ストランス19は、図示の極性で出力電圧Vp
発生している。GTO16のゲート電極・陰極間
には、配線のインダクタンス分20との分圧により
VGKなる誘起逆スパイク電圧が発生する。この
時、トランジスタ12はオフしているので、VTr
なる電圧が印加される。又、同時に、フオトカプ
ラ11にはVTrとほぼ同じVPCなる電圧が印加さ
れる。ここで、VTr,VPCは、コンデンサ7に充
電されたオンゲート電源電圧EONにVGKが重畳し
て加わる。すなわち、VPCVTr=EON+VGKとな
る。上述のように、オフゲート回路が作動する
際、既にターンオフしているNPNトランジスタ
12には、オンゲート電源電圧EONとGTO16の
オフ時に生じる誘起逆スパイク電圧が重畳する
が、同時にフオトカプラ11にもほぼ同じ電圧が
印加される。通常EONは、10〜10数V、VGKは20
〜30Vであり、VTrVPC=35〜45Vの電圧とな
る。トランジスタ12、フオトカプラ11の電圧
定格は、印加される電圧の数倍の耐量を持つもの
を選定するのが一般である。
The GTO 16 is turned off by an off-gate current applied by an off-gate circuit 18 via a pulse transformer 19 in response to an off-command.
The impedance between the gate electrode and cathode electrode of GTO16 remains constant even after off-gate current supply starts.
During the accumulation time when GTO16 is still conducting, the impedance is almost zero, but GTO1
6 is turned off, an induced reverse spike voltage of about 20 to 30 V is generated between the gate electrode and the cathode electrode. FIG. 3 shows an equivalent circuit at this time.
Components that are the same as those in FIG. 1 are given the same reference numerals, and their explanations will be omitted. The pulse transformer 19 for supplying off-gate current generates an output voltage V p with the polarity shown. Due to the partial voltage between the gate electrode and cathode of GTO16, due to the wiring inductance 20
An induced reverse spike voltage V GK is generated. At this time, transistor 12 is off, so V Tr
A voltage is applied. At the same time, a voltage V PC that is approximately the same as V Tr is applied to the photocoupler 11 . Here, V Tr and V PC are added to the on-gate power supply voltage E ON charged in the capacitor 7 with V GK superimposed. That is, V PC V Tr =E ON +V GK . As mentioned above, when the off-gate circuit operates, the on-gate power supply voltage E ON and the induced reverse spike voltage generated when the GTO 16 is turned off are superimposed on the NPN transistor 12, which has already been turned off, but at the same time, almost the same voltage is applied to the photocoupler 11. A voltage is applied. Normally E ON is 10 to 10-odd V, V GK is 20
~30V, resulting in a voltage of V Tr V PC =35 to 45V. The voltage rating of the transistor 12 and photocoupler 11 is generally selected to have a withstand capacity several times higher than the applied voltage.

しかし、市販のフオトカプラのコレクタ・エミ
ツタ間電圧定格は30〜50V以下のものが大半であ
る。フオトカプラに最大定格を越えた電圧が印加
されるとフオトカプラ11がブレークダウンして
フオトカプラの破損を招いたり、トランジスタ1
2がオンして、GTO16を誤点弧させるという
欠点があつた。
However, most commercially available photocouplers have collector-emitter voltage ratings of 30 to 50 V or less. If a voltage exceeding the maximum rating is applied to the photocoupler, the photocoupler 11 may break down, causing damage to the photocoupler, or causing damage to the transistor 1.
2 turned on, causing the GTO16 to fire incorrectly.

(c) 発明の目的 本発明は、上記欠点を除去するためになされた
ものであり、ゲート電極・陰極間に誘起される逆
電圧が、オンゲート電源に重畳する電路を形成し
ない位置に、フオトカプラ素子を配置することに
よりフオトカプラのブレークダウンになる該トラ
ンジスタの誤動作を防止することを目的とする。
(c) Purpose of the Invention The present invention has been made in order to eliminate the above-mentioned drawbacks, and includes a photocoupler element in a position where the reverse voltage induced between the gate electrode and the cathode does not form an electric path superimposed on the on-gate power supply. The purpose of this arrangement is to prevent malfunctions of the transistors that would result in breakdown of the photocoupler.

(d) 発明の構成と作用 第4図に本発明の実施例を示している。第1図
と同一部分には、同一符号を付してその説明は省
略する。12はPNPトランジスタで、抵抗体9
を介して電気/変換素子及び光/電気変換素子と
の組合せから成るフオトカプラ11によりその制
御極が駆動される。第5図は、第3図に対応した
等価回路である。GTO16のゲート電極・陰極
間に発生する誘起逆スパイク電圧は、トランジス
タ12のエミツタEコレクタC間のみに重畳さ
れ、第4図の如く該誘起電圧の重畳されない電路
にあるフオトカプラ11のエミツタ・コレクタ間
には印加されないため、フオトカプラの電圧定格
は、オンゲート電源電圧EON約十数Vに対して選
定すればよく、電圧定格が大幅に軽減される。
(d) Structure and operation of the invention FIG. 4 shows an embodiment of the invention. Components that are the same as those in FIG. 1 are designated by the same reference numerals, and their description will be omitted. 12 is a PNP transistor, resistor 9
Its control pole is driven by a photocoupler 11 consisting of a combination of an electric/electrical conversion element and an optical/electrical conversion element. FIG. 5 is an equivalent circuit corresponding to FIG. 3. The induced reverse spike voltage generated between the gate electrode and the cathode of the GTO 16 is superimposed only between the emitter E and the collector C of the transistor 12, and as shown in FIG. Since no voltage is applied to the photocoupler, the voltage rating of the photocoupler can be selected with respect to the on-gate power supply voltage EON , which is approximately ten or more V, and the voltage rating can be significantly reduced.

(e) 他の実施例 又、第6図は本発明の他の実施例を示す回路図
である。第4図と同一及び同相当部分には同一の
符号を付している。抵抗体9を介してフオトカプ
ラ11により、PNPトランジスタ121を駆動
し、NPNトランジスタ12を駆動するように構
成することにより、前記実施例第4図と同様の効
果すなわち前記誘起逆スパイク電圧の重畳の影響
を受けないフオトカプラの作動が可能である。
(e) Other Embodiments FIG. 6 is a circuit diagram showing another embodiment of the present invention. The same or equivalent parts as in FIG. 4 are given the same reference numerals. By configuring the photocoupler 11 to drive the PNP transistor 121 and the NPN transistor 12 via the resistor 9, the same effect as in the embodiment shown in FIG. It is possible to operate the photocoupler without any interference.

(f) 総合的な効果 以上、説明したように、本発明によれば、フオ
トカプラに印加される電圧は大幅に低減される
故、低耐圧のフオトカプラの使用が可能となり、
フオトカプラのブレークダウンによるトランジス
タの誤動作を防止できるなどの実用的効果は大な
るものである。
(f) Overall effect As explained above, according to the present invention, the voltage applied to the photocoupler is significantly reduced, so it is possible to use a photocoupler with a low withstand voltage.
This has great practical effects, such as preventing transistor malfunctions due to photocoupler breakdown.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来回路のゲート回路図、第2図、第
3図は従来回路の動作を説明する図、第4図は本
発明の一実施例を示す回路図、第5図は本発明を
説明するための回路図、第6図は本発明の他の実
施例を示す回路図である。 1…パルストランス、2…スイツチング電源、
3〜6…ダイオード、7,8…平滑コンデンサ、
9,13,15…抵抗体、11…フオトカプラ、
12,121…トランジスタ、16…GTO。
Fig. 1 is a gate circuit diagram of a conventional circuit, Figs. 2 and 3 are diagrams explaining the operation of the conventional circuit, Fig. 4 is a circuit diagram showing an embodiment of the present invention, and Fig. 5 is a gate circuit diagram of a conventional circuit. FIG. 6 is a circuit diagram for explaining another embodiment of the present invention. 1...Pulse transformer, 2...Switching power supply,
3 to 6...diode, 7,8...smoothing capacitor,
9, 13, 15...Resistor, 11...Photocoupler,
12,121...transistor, 16...GTO.

Claims (1)

【特許請求の範囲】[Claims] 1 直流電源の負極側に自己消弧形半導体素子の
カソードを接続し、前記直流電源の正極側と前記
自己消弧形半導体素子のゲート電極との間に設け
た制御極を有するスイツチング素子を、電気/光
変換素子及び光/電気変換素子との組合せから成
る光結合素子を介して駆動し前記自己消弧形半導
体素子にオンゲート電流を供給するオンゲート回
路と、一端が前記自己消弧形半導体素子のゲート
電極に、他端が前記自己消弧形半導体素子のカソ
ードに接続され前記自己消弧形半導体素子にオフ
ゲート電流を供給するオフゲート回路を備えた自
己消弧形半導体素子のゲート回路において、前記
光/電気変換素子の一方の端子を前記直流電源の
負極側に接続し、他方の端子を前記スイツチング
素子の制御極に接続したことを特徴とする自己消
弧形半導体素子のゲート回路。
1. A switching element having a cathode of a self-arc-extinguishing semiconductor element connected to the negative electrode side of a DC power source, and a control pole provided between the positive electrode side of the DC power source and a gate electrode of the self-arc-extinguishing semiconductor element, an on-gate circuit that supplies an on-gate current to the self-extinguishing semiconductor device by driving it through an optical coupling device consisting of a combination of an electric/optical conversion element and an optical/electrical converting element; In the gate circuit of a self-arc-extinguishing semiconductor device, the gate electrode of the self-arc-extinguishing semiconductor device is provided with an off-gate circuit whose other end is connected to the cathode of the self-arc-extinguishing semiconductor device and supplies an off-gate current to the self-arc-extinguishing semiconductor device. 1. A gate circuit for a self-extinguishing semiconductor device, characterized in that one terminal of the optical/electric conversion device is connected to the negative electrode side of the DC power supply, and the other terminal is connected to the control pole of the switching device.
JP57023553A 1982-02-18 1982-02-18 Gate circuit of self arc extinction type semiconductor element Granted JPS58142627A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57023553A JPS58142627A (en) 1982-02-18 1982-02-18 Gate circuit of self arc extinction type semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57023553A JPS58142627A (en) 1982-02-18 1982-02-18 Gate circuit of self arc extinction type semiconductor element

Publications (2)

Publication Number Publication Date
JPS58142627A JPS58142627A (en) 1983-08-24
JPH0352256B2 true JPH0352256B2 (en) 1991-08-09

Family

ID=12113679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57023553A Granted JPS58142627A (en) 1982-02-18 1982-02-18 Gate circuit of self arc extinction type semiconductor element

Country Status (1)

Country Link
JP (1) JPS58142627A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63102334U (en) * 1986-12-23 1988-07-04

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5465466A (en) * 1977-11-04 1979-05-26 Hitachi Ltd Control circuit for thyristor

Also Published As

Publication number Publication date
JPS58142627A (en) 1983-08-24

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