JPH0353659B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a virtual storage scheme in a data processing system.

[Background of the invention]

As is well known, virtual memory systems have the advantage of being able to improve the utilization rate of real memory while removing the limitation on real memory capacity, which is one of the factors that makes it difficult to operate computer systems flexibly. are doing. In a virtual memory system, a processing program is loaded into virtual memory and executed. Virtual memory is divided into pages of a fixed size, and when a program is executed, pages necessary for execution are brought into real memory (page-in), and pages that are not needed are written out to auxiliary storage (page-out). . The management of real memory and virtual memory, including page-in/page-out processing, is normally performed by the OS (operating system), but as the processing programs become larger and the degree of multiplicity increases, the overhead for page management increases. This increases the throughput of the system.

By the way, processing programs usually consist of several areas with different characteristics in terms of access range and frequency (for example, an area occupied by a group of instructions, a data area, and a work area), but in recent years, processing programs As the amount of data handled increases, the area used for data tends to become larger than the area occupied by a group of instructions. Therefore, in order to reduce the overhead for page management, it is possible to reduce the number of pages by dividing the virtual memory coarsely, but in the conventional method, the page size is fixed to a large value, so the real memory There was a problem that usage efficiency decreased and page usage became less flexible.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a virtual storage system that is effective in reducing overhead for page management and improving the efficiency of using real storage.

[Summary of the invention]

The present invention divides virtual memory and real memory into a plurality of areas consisting of pages of different sizes, and provides an address translation table for each area that associates virtual addresses and real addresses in pages of different sizes. Features.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

FIG. 1 is a conceptual diagram of a virtual storage system according to the present invention, showing an example in which virtual storage is divided into pages of three different sizes. In Figure 1,
Virtual memory (VS) 1 has three areas VS0, VS1,
It is divided into VS2, and the page sizes of each area are PS0, PS1, and PS2, respectively. Similarly, the real memory (RS) 2 is divided into three areas RS0, RS1, and RS2, and the page size of each area is PS0, respectively.
PS1 and PS2. RS0 and VS0, RS1 and VS
1. RS2 and VS2 are address translation tables 3- that store the correspondence between real areas and virtual areas, respectively.
0, 3-1, 3-2. Registers 4-0, 4-1, and 4-2 correspond to address conversion tables 3-0, 3-1, and 3-2, respectively, and the start addresses AD0, AD0, and AD0 of the corresponding tables, respectively.
The lengths are maintained as AD1 and AD2. On the other hand, the processing unit (BPU) 5 stores the address on VS0.
RS the address on VS1 to the address on RS0
Address translation control unit (TU) 7-0, 7-1, 7-2 for converting the address on VS2 to the address on RS2.
It has an address translation mechanism 6 including the following.

FIG. 2 is an example of the address translation operation in FIG. 1, in which address translation from virtual address A to real address B is performed by address translation control unit 7-2.
This shows that success is achieved by referring to the address translation table 3-2.

FIG. 3 is a block diagram of an embodiment of the present invention, showing a hardware configuration corresponding to the conceptual diagram of FIG. 1. The virtual address for memory reference is set in the address register 8 and sent to address translation control units 7-0, 7-1, and 7-2, respectively.
Address conversion control unit 7-0, 7-1, 7-
2, address translation tables 3-0,
Perform address conversion with reference to 3-1 and 3-2,
If successful, the real address corresponding to the virtual address is set in register 10-0, 10-1 or 10-2, and if unsuccessful, signal line 9 is set high. Selector 11 is register 10-0, 10-
1 and 10-2, the register whose signal line 9 is not high is selected, and its contents (actual address) are set in the address register 12. Also, all signal lines 9
When is high, the signal line 13 is set high to generate an address conversion exception. Note that the configuration itself of each address translation control unit 7-0, 7-1, 7-2 is the same as the conventional one.

The embodiment is an example in which the virtual memory (VS) is divided into pages of three different sizes.
By adding an address translation table and an address translation control unit, the variety of page sizes can be easily increased. Further, by changing the contents of the register indicating the address translation table when switching virtual address spaces, it is possible to easily implement a multiple virtual memory system using the virtual memory system according to the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to select multiple page sizes and numbers of pages into which virtual memory is divided depending on the characteristics of the processing program, thereby effectively utilizing real memory and reducing overhead for page management. Wide reductions can be achieved.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram of a virtual storage system according to the present invention, FIG. 2 is a diagram showing an example of address translation operation in FIG. 1, and FIG. 3 is a block diagram of an embodiment of the present invention. 1...Virtual memory, 2...Real memory, 3-0 to 3-2...
Address conversion table, 4-0 to 4-2... register, 5... arithmetic processing unit, 7-0 to 7-2... address conversion control unit.

Claims (1)

[Claims] 1. In a data processing system that uses a virtual memory method, the virtual memory and real memory are each divided into a plurality of areas with pages of different sizes as units, and each area is provided with a virtual address and a real address. A virtual storage method characterized in that address translation from a virtual address to a real address is performed using an address translation table that stores correspondence relationships with addresses.