JPH0353784B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a semiconductor memory device suitable for extremely highly integrated semiconductor memory devices and a method of manufacturing the same.

[Conventional technology]

Conventional semiconductor memory devices are, for example,
There was a semiconductor memory device as shown in Japanese Patent No. 13252, which consisted of one switching transistor and one capacitance cell.

[Problem that the invention seeks to solve]

The above-described cell configuration has fewer elements than a conventional three-transistor cell, etc., and can be highly integrated. However, as the level of integration increases, it becomes impossible to reduce the capacity below a certain value in order to withstand disturbances to stored information, which prevents the level of integration.

With the remarkable increase in the integration density of semiconductor devices in recent years, there is a strong demand for a reduction in the area required for semiconductor memory devices.

An object of the present invention is to solve the above-mentioned conventional problems, provide a capacitor with an extremely small desired area, and provide a semiconductor memory device using the capacitor that can be highly integrated, and a method for manufacturing the same.

[Means for solving problems]

In order to achieve the above object, in the first invention of the present application, the information storage capacitor includes a first electrode, a second electrode, and a capacitive insulating film provided between the first and second electrodes. and at least a part of the portion where the first and second electrodes form a capacitor by facing each other with the capacitor insulating film in between is substantially perpendicular to the semiconductor substrate. A semiconductor memory device is provided.

Further, in the second invention of the present application, a step of providing a gate electrode of a transistor for connection, a step of providing a pore for forming a capacitor for information storage, and a step of providing a pore for forming a capacitor for information storage are provided. and a step of providing a source or drain region in self-alignment with the gate electrode, and the pore is provided in self-alignment with the gate electrode. .

[Effect]

At least a portion of the portion forming the capacitor is provided substantially perpendicular to the semiconductor substrate, so a large capacitance can be obtained with a small occupied area. Further, by manufacturing the insulated gate field effect transistor in a self-aligned manner with the capacitance of the pores, there is no need for areas such as alignment margins, and high integration becomes possible.

〔Example〕

A conceptual diagram of the present invention is shown in sections 1a and 1b. a
The case of the drain capacitance is shown in 1, and the case of the inversion capacitance is shown in b. The gist of the present invention is that a pore 1 is formed in a semiconductor substrate 4.
6 and use the surface of the inner wall of the pore as a capacitor, and is characterized in that the inner wall surface of the pore can be significantly enlarged relative to the area of the opening on the substrate surface. In this way, the storage capacity can be expanded without increasing the planar area, and the disadvantage of multi-stage connection, which was a drawback of the conventional method, can be dramatically reduced.

According to the conventional example, a capacitance of 100 μm results in a power of 1 pF, but the pore shown in Figure 1 can easily form a depth of 50 μm with an opening of 2 μm x 100 μm, so the area of the capacitor is the same and the area of the substrate surface is 1/50th. It can be reduced to In this example, at least 50 times the integration density is achieved on the same substrate surface as before. Moreover, if the scale is the same, the area can be reduced to 1/50, and the effect of implementing the present invention is immeasurable.

Next, the method for forming pores will be described. An etching method using an aqueous solution of KOH has been known for a long time, and the etching speed of the {111} plane of silicon is particularly slow, and if appropriate conditions are chosen, the etching speed can be 1/400 of that of planes other than the {111} plane. It is also possible to do so. In other words, orientation-dependent etching (orientaion
Even if the etching method (dependent etching) is used, the {111} plane, which has the slowest etching rate, can be formed with high precision. This explanation is shown in FIG. Since the pores are formed deeply in the vertical direction according to the purpose of the present invention, the substrate surface is the {111} plane or its vicinity (hereinafter, when the {110} plane is referred to as the {110} plane, unless otherwise specified, the vicinity thereof is also included. must be within 20° from the {110} plane (in the case of the {110} plane, there must be no other low index plane within 20°).

As shown in FIG. 2, etching mask hole side lines 17 are formed on the {110} plane. As an etching mask, any material can be used as long as it has a sufficiently slower etching rate than silicon, but usually
_SiO2 is used. An etching mask hole with a width LB ₀ is formed in this SiO ₂ film, and then etched with an aqueous KOH solution. Figure 3 shows the measured values of the etching rate and KOH concentration of the {110} plane. Although the dependence of the etching rate on the KOH concentration is small, a concentration of 20% or more is appropriate in consideration of the smoothness of the etched surface. For example, if a solution with a temperature of 80°C and a KOH concentration of 40% is used, the etching rate will be 1.25 μm/min.

When etching is performed for 60 minutes using this solution, the depth D of the etching hole becomes 75 μm. Second
As shown in the figure, the etching hole inner wall surface 18 is composed of {110} plane, and the etching mask hole side line 1
7 is the intersection line of {111} plane and {111} plane [112]
Assuming that it is tilted by θ from the direction, the larger θ becomes, the more minute {111} planes will be present on the inner wall surface. The figure depicts an uneven surface with many steps, but this is an atomically enlarged view; the actual inner wall surface is a mirror surface, and the schematic uneven surface shown in the figure cannot be seen.

Furthermore, the final width L _F of the etching hole is generally expanded compared to the width L ₀ of the etching mask hole, and the amount of expansion strongly depends on θ. Now let the amount of expansion be m,
It is defined by the following formula.

m=L _F −L ₀ /2 (1) This m is the distance from the side line of the etching mask to the inner wall surface of the etching hole. The relationship between this m and the value θ normalized by the etching hole depth D is shown in FIG. θ and m/D show a nearly linear relationship, and m is expected to be extremely small when θ=0. In other words, it is shown that if the side line of the etching mask hole is exactly in the [112] direction, an etching hole with almost the same width as the etching mask hole width can be formed. In reality, the condition θ=0 cannot be used. For example, when θ=1°, if an etching hole with a depth of 75 μm is formed as described above, m=2.6 μm. That is, even if the width L ₀ of the etching mask hole is 1 μm, it expands by 2.6 μm at both ends, and the final etching hole width becomes 6.6 μm.

Although the pore-forming etching method used to carry out the present invention has been described above, the present invention does not limit the etching method, and does not limit the type of etching method.

The present invention will be described using detailed examples above.
Furthermore, in the description of the present invention, the above-described pore-forming etching will be abbreviated as ODE (Orientation Dependent Etching), and the detailed etching conditions will not be specified each time. Furthermore, since the structure of the present invention can use a drain capacitor (FIG. 1a) or an inversion capacitor (FIG. 1b), an example of the drain capacitor will be described first.

FIG. 5 shows an embodiment of the present invention. First, as shown in a, an etching hole 19 is formed in an insulating film (SiO ₂ is often used) to serve as an etching mask on the substrate 4 by photo-etching. Thereafter, pores 16 are formed by ODE, and as shown in b, the source region and the insulating film in the pores are removed, and a substrate of the first conductivity type is formed by known thermal diffusion or ion implantation methods. A region 5 of the opposite second conductivity type is formed. As shown in c, an insulating film 6 is then deposited by thermal oxidation or the like, electrode connection holes 20 are formed by photoetching or the like, and then d
A gate electrode 8 and a source electrode 7 are formed as shown in FIG. By doing this, the structure of the present invention shown in FIG. 1a can be realized.

Another embodiment of the invention is shown in FIG. The process up to step a is the same as the method shown in FIG. After that, as shown in b, a self-aligned electrode 21 is formed on a predetermined insulating film 6.
Using this as a mask, a second conductivity type region 5 is formed by known ion implantation or thermal diffusion method as shown in c. The self-aligned electrode 21 may be made of any material that can withstand ion implantation or thermal diffusion, and in the thermal diffusion method, polycrystalline silicon, high melting point metals such as M _{2 O} 2 and W, etc. are often used. further on top of that
By CVD (Chemical Vapor Deposition) method
SiO ₂ film and PSG with phosphorus and boron added to it
(Phospho-silicate Glass) and BSG (Boro-Silicate Glass)
2nd layer insulating film 22 typified by silicate glass)
is deposited to connect the source region, the source electrode 7 connected to the self-aligned electrode 21, and the gate electrode 8.
In this embodiment, the source region, the drain region, and the gate are formed in self-alignment, so that miniaturization of the device can be achieved.

FIG. 7 shows another embodiment of the invention. As shown in a, an insulating film 6 is formed, and self-aligned electrodes 21 are formed in predetermined portions. Since this electrode is used as a mask for ODE etching, it needs to be hardly soluble in KOH aqueous solution, but the above-mentioned polycrystalline silicon, M _{2 O 2} , W, etc. are easily soluble. Therefore, it is also necessary to deposit the insulating film 6 on the electrode 21 as well. Next, as shown in b, pores 16 are formed by ODE,
Next, the electrode 21 is masked and the insulating film 6 in the source portion is removed. Thereafter, as shown in c, a region 5 of the second conductivity type is formed by known ion implantation or thermal diffusion method.
is formed, and a second layer insulating film 22 is deposited. Further, as shown in d, an electrode connection hole 20 is formed by photoetching, and a source electrode 7 and a gate electrode 8 are formed. In this embodiment, since the pore, drain, source, and gate are self-aligned, the device can be made even smaller than the embodiments shown in FIGS. 5 and 6. At this time, the self-type electrode 21 is formed so as to surround the pore 16, as shown in the plan view e.

The three embodiments of the present invention have been described above, and in the cases of FIGS. 5 and 6, the drain and gate are arranged in one direction. As shown in FIG. 8, a second conductivity type region 5 that becomes a gate electrode and a source can be formed to surround the pore 16.

Further, all of the above three embodiments of the present invention have been explained using one element, but when this element is arranged in a matrix, the data line 13, which is the connection of the source region, and the word line 13, which is the connection of the gate, cross each other. . At this time, in the above three embodiments, the gate electrode 8 and the source electrode 7 cannot be separated within the same plane. To solve this problem, it is sufficient to align the surface of the substrate 4 without connecting the source electrode 7 from the second conductivity type region 5 of the source. However, in this case, the region 5 cannot be formed directly under the self-aligned electrode 21 which becomes the gate, so as shown in FIG.
In the case of FIG. 7, it is necessary to form the region 5 for source connection in advance in addition to forming the region 5.

For this, as shown in FIG. 9a, a part of the insulating film mask 6 is removed and a region 5 of the second conductivity type is formed by known ion implantation or thermal diffusion method, or b
As shown in FIG. 2, a method can be used in which a region 5 is formed over the entire surface of the substrate and then the region 5, which will become a source region, is left and the rest are removed.

FIG. 10 shows an embodiment of the present invention arranged in a matrix. In case a, the source and gate are arranged in one direction, but in case b, the source is formed to surround the gate. Using the method described above, the second conductivity type region 5 serving as the source is used as a data line, and the self-aligned electrode 21 serving as the gate is used as a word line. At this time, it is necessary to electrically isolate the sources arranged in parallel, and a separation band 23 is formed between them. This separation band can be formed by increasing the thickness of the insulating film above it to 5000 mm or more, by adding impurities to this part to have the same conductivity type as the substrate, or by connecting the third electrode to the electrode 21 through the insulating film 6. Several methods are known, such as forming the substrate under the substrate and applying a voltage to prevent the channel from forming on the substrate and becoming conductive, but the present invention is not limited to these methods.

FIG. 11 shows another embodiment of the present invention. This uses the inversion capacitance b in Figures 1, 2, and 5, and forms a region 5 of the second conductivity type that becomes a source as shown in a in Figure 11, and then as shown in b in Figure 11. Then, pores 16 are formed in predetermined portions by ODE. Furthermore, after forming the insulating film 6 as shown in c, an electrode connection hole 20 is formed on the source, and d
As shown in the figure, a source electrode 7, a gate electrode 8, and a capacitor electrode 9 are formed, and the inner wall of the pore is used as a capacitor.

In this way, using the inner wall of the pore as a capacitor means that the inversion layer formed on the semiconductor substrate side becomes the first electrode, the capacitor electrode 9 becomes the second electrode, and the first and second electrodes The information storage capacitor is constituted by the capacitive insulating film provided between the two. Therefore, at least a part of the portion where the first and second electrodes form a capacitor by opposing each other with the capacitor insulating film in between is provided substantially perpendicularly to the semiconductor substrate. It constitutes a storage device.

Another embodiment of the invention is shown in FIG. In this method, the gate and source are formed by self-alignment, and after forming the pores 16 by ODE as shown in a, an insulating film 6 covering the entire surface is formed, and b
After forming a self-aligned electrode 21 at a predetermined position as shown in FIG. 2, a second conductivity type region 5 is formed by a known ion implantation or thermal diffusion method using this as a mask. After that, as shown in c, the second layer insulating film 2 is formed.
A source electrode 7, a gate electrode 8, and a capacitor electrode 9 are connected through electrode connection holes as shown in d. By doing so, the source, gate, and capacitor electrode can be formed by self-alignment, which is effective for miniaturization.

Another embodiment of the invention is shown in FIG. In this method, the gate, source, capacitor electrode, and pore are formed by self-alignment, and as shown in a, after forming the self-alignment electrode 21 by the method described above, this is used as a mask during ODE etching. For use, as an example, an insulating film 6 is deposited, and using this as a mask, ODE etching is performed as shown in b to form a pore 16, and then the inner wall of the pore is covered with the insulating film 6.
Thereafter, as shown in c, the second self-aligned electrode 24
and leave a designated part. Thereafter, a second conductivity type region 5 that will become a source is formed by known ion implantation or diffusion. Further, this region 5 may be formed before the second self-aligned electrode 24 is formed. After that, as shown in d, a second layer insulating film 22 is formed and the electrode connection hole 2 is
0, the source electrode 7, gate electrode 8, and capacitor electrode 9 are connected. This allows the electrodes to be formed in self-alignment with each other, which is further advantageous for miniaturization.

FIG. 14 shows another embodiment of the present invention in which source and gate capacitor electrodes are formed by self-alignment in an arrangement different from that in FIG. 13.

These figures 11, 12, 13 and 1
In addition to arranging the capacitor electrodes, sources, and gates in one direction as shown in FIG. 4, they can also be arranged so as to surround each other as shown in FIG. 12. Further, when a large number of elements are arranged in a matrix and a common source is to be used, the common source shown in FIG. 13 may be formed in advance as described above.

The elements having this capacitive electrode can be arranged in a matrix as shown in FIG. This is a configuration in which a capacitor electrode is added when using the drain junction capacitor shown in FIG. 10, and the gate electrode and capacitor electrode may be arranged alternately as shown in the figure. In this way, the matrix can be constructed without forming electrode connection holes, so that it can be miniaturized.

In the description of the present invention, for convenience, the insulating film 6 was formed on the substrate surface and on the self-aligned electrode in the same way, but a different insulating film may be used on each substrate.

In addition, although a {110} plane silicon substrate is used in the present invention, other low index planes, such as {111}, {100}
Since pores almost perpendicular to the surface cannot be formed in this case, there is almost no effect of implementing the present invention, and the present invention is based on {110}
Preferably within about 20 degrees of the surface and its vicinity.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the area required for a capacitor can be significantly reduced, and it is extremely useful for improving the integration density of semiconductor devices.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the concept of the present invention, FIG.
FIGS. 3 and 4 are diagrams for explaining the method of forming pores, and FIGS. 5 to 15 are diagrams showing examples of the present invention.

Claims (1)

[Claims] 1. A semiconductor substrate, a plurality of word lines provided on the semiconductor substrate, a plurality of data lines provided on the semiconductor substrate, and connection insulation provided on the semiconductor substrate. a gate field effect transistor;
a semiconductor memory device having a capacitor for information storage provided on the semiconductor substrate, and in which a memory cell is constituted by the insulated gate field effect transistor for connection and the capacitor for information storage; The insulated gate field effect transistor has a gate electrode, the gate electrode is connected to the word line, and the information storage capacitor is connected to a first electrode, a second electrode, and a first and second electrode. and a capacitive insulating film provided between the electrodes, and at least a part of the portion where the first and second electrodes form a capacitance by facing each other with the capacitive insulating film in between. A semiconductor memory device, characterized in that it is provided substantially perpendicularly to the semiconductor substrate. 2. The semiconductor memory device according to claim 1, wherein one of the first and second electrodes is provided on the gate electrode with an insulating film interposed therebetween. 3. In a method for manufacturing a semiconductor memory device having a connection transistor and an information storage capacitor, the steps include: providing a gate electrode of the connection transistor; and providing a pore for forming the information storage capacitor. a step of providing a first electrode for forming the information storage capacitor; and a step of providing a source or drain region in self-alignment with the gate electrode, and the pore is connected to the gate electrode. 1. A method of manufacturing a semiconductor memory device, characterized in that the device is provided in a self-aligned manner. 4. The method for manufacturing a semiconductor memory device according to claim 3, wherein the gate electrode is a first layer electrode, and the first electrode is a second layer electrode. A method for manufacturing a semiconductor memory device. 5. In the method of manufacturing a semiconductor memory device according to claim 3 or 4, the first electrode is provided on the gate electrode with an insulating film interposed therebetween. A method for manufacturing a semiconductor memory device characterized by: 6. In the method for manufacturing a semiconductor memory device according to any one of claims 3 to 5, the first electrode is provided so as to extend over an insulating film for element isolation. A method of manufacturing a semiconductor memory device, characterized in that: 7. In the method for manufacturing a semiconductor memory device according to any one of claims 3 to 6, the step of providing the pore and the gate electrode in a self-aligned manner includes oxidizing the sidewall of the gate electrode. A method for manufacturing a semiconductor memory device, comprising the steps of providing a film and forming the pores using the oxide film as a mask. 8. The method of manufacturing a semiconductor memory device according to any one of claims 3 to 7, wherein the gate electrode contains polycrystalline silicon. 9. The method of manufacturing a semiconductor memory device according to any one of claims 3 to 8, wherein the gate electrode contains a high melting point metal. 10. The method of manufacturing a semiconductor memory device according to claim 9, wherein the high melting point metal contains Mo or W.