JPH0354899B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a delay circuit applied to, for example, a gate array LSI.

2. Description of the Related Art In gate array LSIs, delay circuits are used to keep the propagation delay time between signals constant.
For example, in Figure 2, clock CK ₀ is set to
Assume that flip-flops _FF1 and FF2 are latched by clocks _CK1 and _{CK2 obtained by delaying them by t1 and t2 .} In this case, as shown in FIG. 3, if the delay of clock CK ₂ after flip-flop FF1 is latched by clock CK ₁ is large,
Latching by clock _CK2 of flip-flop FF2 may be performed for later data. In other words, flip-flop FF by clock CK ₂
The hold time of the input data in step 2 may become shorter. Therefore, as shown in FIG. 4, a delay circuit DL is installed between flip-flops FF1 and FF2.
, the data output Q of the flip-flop FF1 is delayed by the delay circuit DL by the time _td , as shown in FIG.
The data input D of FF2 is delayed by _td from the data output Q of flip-flop FF1. As a result,
The hold time of the input data of the flip-flop FF2 by the clock _CK2 becomes sufficiently long.

As a condition for the above delay circuit, (A) Optimum delay time can be obtained; (B) does not require a large area; (C) Small variation in delay time; etc. are required.

Generally, the delay time t _pd per gate of a MOS transistor is t _pd ∝C/g _n However, C can be expressed as load capacitance and g _n can be expressed as conductivity. Therefore, if the load capacitance C is constant, , g _n ∝W/L, so the gate width W
The delay time can be increased by using an inverter using MOS transistors with a small gate length L and a large gate length L, but gate array LSIs use only transistors with fixed dimensions, so the transistor dimensions cannot be changed arbitrarily. . Therefore, in gate array LSIs, conventionally, as shown in FIG. 6, inverters are connected in multiple stages to increase the delay time. Note that it is also possible to configure a delay circuit using a CR circuit, but in this case, the delay time must be adjusted using polysilicon resistance or diffused resistance, and therefore parameters that are not used in gate array LSIs must be adjusted. However, considering the variations, CR circuits are integrated into gate array LSIs.
It is impossible to use this as a delay circuit.

In Figure 6, if 4 gates in terms of 2-input gates are used as one basic cell, and each inverter INV is configured with one basic cell, when the potential of the input terminal IN changes from high to low, the delay time of the first stage is 0.77 ns 2nd stage delay time 0.43ns 3rd stage delay time 0.77ns 4th stage delay time 0.71ns, therefore, the total delay time is
It is 2.68ns. Also, when the input potential IN changes from low to high, the delay time of the first stage is 0.43ns, the delay time of the second stage is 0.77ns, the delay time of the third stage is 0.43ns, and the delay time of the fourth stage is approximately 1.32ns. Therefore, the total delay time is
It is 2.95ns.

Problems to be Solved by the Invention However, as mentioned above, if inverters are simply connected in multiple stages, the number of gates will be large in order to obtain a large delay time, and therefore a large area will be required. Ta.

Means for Solving the Problems In view of the above-mentioned problems, an object of the present invention is to provide a delay circuit that is suitable for gate array LSI and has a small area. This is achieved by providing two inverters each having transistors connected in series.

Operation According to the above-described configuration, the voltage is charged by the cascade-connected P-channel transistors of each inverter to increase the output of each inverter, and is discharged by the cascade-connected N-channel transistors of each inverter. Since the output of each inverter is lowered by the delay time, the delay time increases depending on the number of P-channel transistors and N-channel transistors.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 7 is a circuit diagram showing inverter means for explaining the delay circuit according to the present invention. In Figure 7, P-channel transistors Q _1p , Q _2p , Q _3p , and Q _4p are connected in series between the power supply V _cc and the output terminal OUT, and an N-channel transistor Q is connected between the output terminal OUT and the ground. _1o , Q _2o , Q _3o , and Q _4o are connected in cascade. Furthermore, a load capacitor C _L is connected to the output terminal OUT. These P channel transistors Q _1p , Q _2p , Q _3p , Q _4p and N channel transistors Q _1o , Q _2o , Q _3o , Q _4o are all driven by the potential of the input terminal IN. for example,
When the potential of the input terminal IN is low level, transistors Q _1p , Q _2p , Q _3p , and Q _4p are in the on state,
Transistors Q _1o , Q _2o , Q _3o , and Q _4o are in the off state, so the load capacitance _CL is equal to the transistors Q _1p ,
It is charged to V _cc via Q _2p , Q _3p , and Q _4p , and the potential of the output terminal OUT is at a high level. On the other hand, if the potential of the input terminal IN is at a high level, transistors Q _1o , Q _2o , Q _3o , and Q _4o are in an on state, and transistors Q _1P , Q _2P , Q _3P , and Q _4P are in an off state, Therefore, the load capacitance C _L is the transistor Q _1o ,
Discharged through Q _2o , Q _3o , Q _4o , output terminal OUT
The potential of is at low level. Therefore, the input terminal
When the potential of IN changes from high level to low level, P channel transistors Q _1p , Q _2p , Q _3p ,
Q _4p , as shown in Figure 8A.
The output terminal has the same characteristics as the rising operation of the input NOR circuit.
The potential of OUT increases. On the other hand, when the potential of the input terminal IN changes from low level to high level, N
It is discharged through the channel transistors Q _1o , Q _2o , Q _3o , and Q _4o , and the output terminal OUT has the same characteristics as the falling operation of a 4-input NAND circuit as shown in Figure 8B.
The potential of decreases.

Incidentally, the variations in circuit operation shown in FIG. 7 are also equivalent to the variations in circuit operation of a normal logic circuit.

FIG. 1 is a circuit diagram showing an embodiment of the delay circuit according to the present invention, in which the inverter shown in FIG.
There are several. That is, the inverter INVA is
P-channel transistors Q _1p , Q _2p , Q _3p , Q _4p ,
and N-channel transistors Q _1o , Q _2o , Q _3o ,
Consists of Q _4o connected in series, inverter INVB
are P-channel transistors Q′ _1p , Q′ _2p , Q′ _3p ,
Q′ _4p , and N-channel transistors Q′ _1o , Q′ _2o ,
It is constructed by connecting Q′ _3o and Q′ _4o in cascade.

In Fig. 1, the potential of the input terminal IN is different from each transistor Q _1p , Q 2p , Q 3p , Q _3p , Q _{2p ,} Q 3p ,
are supplied to the gates of Q _4p , Q _1o , Q _2o , Q _3o , and Q _4o , and therefore these transistors
Driven by IN potential. Also, inverter
The common output C of the central P-channel/N-channel transistor pair Q _4p and Q _4o of INVA is the inverter INVB.
Each transistor Q′ _1p , Q′ _2p , Q′ _3p , Q′ _4p , Q′ _1o
，
is supplied to each gate of Q′ _2o , Q′ _3o , Q′ _4o , and therefore,
These transistors are driven by the potential of output C. Then, P in the center of the inverter INV
Channel/N-channel transistor pair Q′ _4p , Q′ _4o
The common output of is connected to the output terminal OUT of this delay circuit.

Note that if the circuit shown in Figure 1 is configured with a basic cell of 4 gates converted into 2-input gates, the transistor
Q _1p , Q _2p , Q _1o , Q _2o ; Transistor Q _3p , Q _4p ,
Q _3o , Q _4o ; Transistor Q′ _1p , Q′ _2p , Q′ _1o ,
Q′ _2o ; transistors Q′ _3p , Q′ _4p , Q′ _3o , Q′ _4o ,
Each of them can be configured with one basic cell, so the circuit of FIG. 1 can be configured with four basic cells like the circuit of FIG. 6.

The circuit operation of FIG. 1 is illustrated in FIGS. 9-12. Figure 9 shows the case where the fanout (F/O) = 0 and the potential of the input terminal IN changes from low to high, and Figure 10 shows the case where the fanout (F/O) = 0. Figure 11 shows the case where the potential of the input terminal IN changes from high to low, and Figure 11 shows the case where the fan-out (F/O) = 5 and the potential of the input terminal IN changes from low to high. Figure 12 shows fan out (F/O) = 5.
This shows the case where the potential of the input terminal IN changes from high to low.

Referring to Figure 9, if the potential of the input terminal IN is at low level at the beginning, the inverter
In INVA, P channel transistor Q _1p ,
Since Q _2p , Q _3p , and Q _4p are in an on state, and N-channel transistors Q _1o , Q _2o , Q _3o , and Q _4o are in an off state, the potential of node C is at a high level.
Therefore, in the inverter INVB, the P-channel transistors Q' _1p , Q' _2p , Q' _3p , Q' _4p are in the off state, and the N-channel transistors Q' _1o , Q' _2o ,
Since Q′ _3o and Q′ _4o are in the on state, the output terminal OUT
The potential of is at low level. In this state, the input terminal
When the potential of IN changes from low level to high level, N-channel transistors Q _1o , Q _2o , Q _3o ,
Q _4o tends to turn on and P channel transistor
Q _1p , Q _2p , Q _3p , and Q _4p tend to be off. At this time, if the potential of the input terminal IN changes suddenly, the potentials of the nodes A ₁ , A ₂ , A ₃ , and C temporarily rise due to capacitive coupling between the gate and drain, as shown in the figure. . In other words, it becomes higher than the power supply potential _Vcc .
Then, as the transistors Q _1o , Q _2o , Q _3o , and Q _4o turn on, the node C is discharged through these transistors, and as a result, the potential of the node C decreases and the potential of the nodes B _{1 , B 2 ,} and B ₃ decreases. Each potential is DC depending on the impedance ratio of these transistors.
Change towards a stable point. At the same time, as the potential of node C decreases, transistors Q′ _1p ,
Q′ _2p , Q′ _3p , and Q′ _4p also tend to turn on, and therefore, the respective potentials of nodes D ₁ , D ₂ , and D ₃ also change to those of transistors Q′ _1p ,
DC according to the impedance ratio of Q′ _2p , Q′ _3p , Q′ _4p
Change towards a stable point. At this time, due to the sudden drop in the potential of node C, nodes E ₁ , E ₂ , and E ₃ become below the ground level.

Next, when the potential of the input terminal IN reaches a sufficiently high level, the transistors Q _1o , Q _2o , Q _3o , Q _4o
is almost completely turned on, and therefore the potentials of nodes C, B ₁ , B ₂ and B ₃ decrease due to discharge. Note that at this time, the transistors Q _1p , Q _2p ,
Since Q _3p and Q _4p are almost completely off, the potentials of nodes A ₁ , A ₂ , and A ₃ will change to the leakage current of transistors Q _1p , Q _2p , Q _3p , and Q _4p after enough time. Therefore, the potential will be in accordance with the impedance determined. Furthermore, when the potential of node C becomes a sufficiently low level, transistors Q' _1p , Q' _2p , Q' _3p , and Q' _4p are almost completely turned on, so that nodes D ₁ ,
The potentials of D ₂ and D ₃ and the potential of the output terminal OUT begin to rise due to charging. Note that at this time, the transistors Q′ _1o , Q′ _2o , Q′ _3o , and Q′ _4o are almost completely off, so the potentials of the nodes CE ₁ , E ₂ , and E ₂ will change after a sufficient period of time. , transistor Q′ _1o ,
The potential follows the impedance determined by the leakage currents of Q′ _2o , Q′ _3o , and Q′ _4o .

In this way, the transistors Q′ _1p , Q′ _2p , Q′ _3p ,
The potential of the output terminal OUT changes due to the discharge by Q′ _4p , transistors Q _1o , Q _2o , Q _3o , and Q _4o , but
At this time, since charging or discharging is performed through a large number of transistors, the delay time becomes long.

Further, when the potential of the input terminal IN changes from high level to low level, the potential of each node changes as shown in FIG. The details _are the same as in the case of Fig _. 9 _{, so the} explanation will be omitted, _but in _this case, _the The potential of the output terminal OUT changes due to discharge.

Note that if the number of fanouts is set to 5, for example, FIG. 9 changes as shown in FIG. 11, and
FIG. 10 changes as shown in FIG. 12. Output terminal
As the OUT waveform becomes duller, the delay time becomes even larger.

In either case, a delay time of 5 ns or more can be ensured, which is longer than in the case of FIG.

In the above embodiment, the same number of P channel transistors and N channel transistors are connected in series to each inverter means INVA, INVB, but it goes without saying that the number of transistors can be changed arbitrarily. Further, an inverter as a waveform shaping means may be connected to the circuit shown in FIG.

Effects of the Invention As explained above, according to the present invention, when the same number of basic cells are used, the delay time can be increased compared to the conventional case where inverters are simply connected in multiple stages. In other words, when obtaining the same delay time, the area of the delay circuit can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of a delay circuit according to the present invention, FIG. 2 is a partial circuit diagram of a gate array LSI without inserting a delay circuit, and FIG. 3 is for explaining the circuit operation of FIG. 2. Fig. 4 is a partial circuit diagram of a gate array LSI with a delay circuit inserted, Fig. 5 is a timing diagram for explaining the circuit operation of Fig. 4, and Fig. 6 is a circuit showing a conventional delay circuit. 7 is a circuit diagram showing an inverter means for explaining the delay circuit according to the present invention, and FIG. 8A,
B is a circuit diagram for explaining the circuit operation of FIG. 7;
9-12 are timing diagrams of signals appearing within the circuit of FIG. 1. IN: Input terminal, OUT: Output terminal, V _cc : Power supply,
INVA, INVB: Inverter means, Q _1p , Q _2p ...:
P channel transistor, Q _1o , Q _2o ...: N channel transistor.

Claims (1)

[Claims] 1. An input terminal IN, an output terminal OUT, first and second power supply means V _cc and GND, and a first inverter connected to the input terminal.
INVA; and a second inverter INVB connected between the output C of the first inverter and the output terminal, wherein each of the first and second inverters has a a plurality of P-channel transistors Q _1p , ..., Q' _1p , ... connected in series between the first power supply means and the output of the inverter; and between the second power supply means and the output of the inverter. The same number of N-channel transistors Q _1o as the P-channel transistors connected in series with Q 1o ,...,
Q′ _1o , . In response to the rising or falling edge of the applied input signal, the plurality of P
A delay circuit in which transistors in one group of channel and N-channel transistors are sequentially turned on from the power supply means side, and transistors in the other group are sequentially turned off from the output side of the inverter.