JPH0834418B2 - Delay circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit applied to, for example, a gate array LSI.

2. Description of the Related Art In a gate array LSI, a delay circuit is used to make the propagation delay time between signals constant. For example, in FIG. 2, it is assumed that latches the flip-flop FF1, FF2 by the clock CK _1, CK ₂ of the clock CK ₀ obtained by delaying the time t _1, t _2. In this case, as shown in Figure 3, after the latch by the clock CK ₁ of the flip-flop FF1, if the delay of the clock CK ₂ is large, that the latch by the clock CK ₂ of the flip-flop FF2 is performed on data after is there. In other words, it may hold time of the input data of the flip-flop FF2 is reduced by the clock CK _2. Therefore, as shown in FIG.
When the delay circuit DL is inserted between the flip-flops FF1 and FF2, the data output Q of the flip-flop FF1 is delayed by the delay circuit DL by the time t _d , as shown in FIG.
Therefore, the data input D of the flip-flop FF2 is delayed from the data output Q of the flip-flop FF1 by t _d .
As a result, the hold time of the input data of the flip-flop by the clock CK ₂ is sufficiently large.

 The conditions of the above-mentioned delay circuit are: A) obtaining an optimum delay time, B) not requiring a large area, C) having a small variation in delay time, and the like.

Generally, the delay time t per gate of a MOS transistor
_pd can be expressed as t _pd αC / g _m where C is the load capacitance and g _m is the conductivity. Therefore, if the load capacitance C is constant, then g _m αW / L. The delay time can be increased by using an inverter with a MOS transistor that is small and has a large gate length L.
In I, only transistors of a certain size are used, so that the size of the transistor cannot be arbitrarily changed. Therefore, in the gate array LSI, conventionally, as shown in FIG. 6, inverters are connected in multiple stages to increase the delay time. Note that a delay circuit can be configured by a CR circuit, but in this case, the delay time must be adjusted by the resistance or diffusion resistance of polysilicon, and therefore, parameters that are not used in the gate array LSI must be adjusted. Considering the variation, CR circuit is gate array
It is impossible to adopt it as a delay circuit of LSI.

In Fig. 6, if 4 gates converted into 2 input gates are set as one basic cell and each inverter INV is made up of one basic cell, when the potential at the input terminal IN changes from high to low, the delay time of the first stage 0.77ns Second stage delay time 0.43ns Third stage delay time 0.77ns Fourth stage delay time is about 0.71ns, so the total delay time is 2.68ns. When the input potential IN changes from low to high, the delay time of the first stage is 0.43ns, the delay time of the second stage is 0.77ns, the delay time of the third stage is 0.43ns, and the delay time of the fourth stage is about 1.32ns. Therefore, the total delay time is 2.95 ns.

Problems to be Solved by the Invention However, as described above, if the inverters are simply connected in multiple stages, the number of gates becomes large in order to obtain a large delay time, and thus a large area is required. .

Means for Solving the Problems In view of the above problems, an object of the present invention is to provide a gate array.
The purpose of the present invention is to provide a delay circuit suitable for LSI and having a small area. The means is to provide two inverter means in which P-channel / N-channel transistors are connected in cascade, and to output each output of the inverter means of the latter stage to the inverter means of the former stage. This is achieved by feeding back each input.

Action According to the above configuration, since the output of the inverter means at the latter stage is fed back to the input of the inverter means at the former stage, the driving ability becomes smaller, therefore the delay time becomes longer and the fanout (F / O) A large delay circuit can be obtained.

Embodiment FIG. 1 is a circuit diagram showing one embodiment of a delay circuit according to the present invention. In FIG. 1, two inverter means INV
A and INVB are provided. The inverter means INVA is constituted by connecting P-channel transistors Q _1p , Q _2p , Q _3p , Q _4p and N-channel transistors Q _1n , Q _2n , Q _3n , Q _4n in cascade connection,
Each P-channel / N-channel transistor pair Q _1p , Q _1n ; Q _2p , Q
_2n ; Q _3p , Q _3n ; Q _4p , Q _4n constitute one inverter. Similarly, the inverter means INVB has P-channel transistors _Q1'p , _Q2'p , _Q3'p , _Q4'p , and N-channel transistors _Q1'n , _Q2'n , _Q3'n ,. Q _4'n
In cascade connection, and each P-channel / N-channel transistor pair Q _1'p , Q _1'n ; Q _2'p , Q _2'n ;
Q _3'p , Q _3'n ; Q _4'p , Q _4'n constitute one inverter.

Here, each transistor pair Q _1p , Q _1n ; Q _1'p ,
Q _1'n ; Q _2p , Q _2n ; Q _2'p , Q _2'n ; Q _3p , Q _3n ; Q _3'p ,
Q _3'n ; Q _4p , Q _4n ; Q _4'p , Q _4'n are _connected to inverters INV ₁ , I
NV ₂ , INV ₃ , INV ₄ , INV ₅ , INV ₆ , INV ₇ , INV ₈
The circuit in the figure can be rewritten schematically as shown in FIG. Although the P-channel transistor Q _p and the N-channel transistor Q _n are not present in FIG. 1, they are provided for easy understanding of the operation. If INV _{3 to} INV ₈ are regarded as transfer gates, the circuit of FIG. 1 can be rewritten schematically as shown in FIG.

That is, in FIG. ₁ , the inverter INV ₁ (Q _1p ,
Q _1n ) is driven by the potential of the input terminal IN,
INV ₂ (Q _1'P , Q _1'n ) is driven by the output A of the inverter INV ₁ , and inverter INV ₃ (Q _2p , Q _2n ) is the inverter I.
Driven by output B of NV ₂ , inverter INV ₄ (Q
_2'P , Q _2'n ) is driven by the output C of the inverter INV ₃ , the inverter INV ₅ (Q _3p , Q _3n ) is driven by the output D of the inverter INV ₄ , and the inverter INV ₆ (Q _3'P , Q
_3'n ) is driven by the output E of the inverter INV ₅ ,
The inverter INV ₇ (Q _4p , Q _4n ) is driven by the output F of the inverter INV ₆ , and the inverter INV ₈ (Q _4′P , Q _4′n )
Is driven by the output G of the inverter INV _{7, and} the output of the inverter INV ₈ becomes the potential of the output terminal OUT.

In this way, the output of each inverter in the subsequent stage is fed back to the input of each inverter in the previous stage, so the driving capability of each inverter is reduced and the delay time is increased.

If the circuit shown in FIG. 1 is composed of a basic cell having 4 gates converted into 2 inputs, the transistors Q _1p , Q _2p , Q _1n ,
Q _2n ； Transistor Q _3p , Q _4p , Q _3n , Q _4n ； Transistor Q
_1'p , Q _2'p , Q _1'n , Q _2'n ; transistor Q
_{Each of 3'p} , Q _4'p , Q _3'n , and Q _4'n can be constructed by one basic cell. Therefore, the circuit of FIG. 1 has four basic cells like the circuit of FIG. Can be configured.

The circuit operation of FIG. 1 is shown in FIGS. Ninth
The figure shows the case of fanout (F / O) = 0 and the input terminal I
Fig. 10 shows the case where the potential of N changes from low to high. Fig. 10 shows the case of fanout (F / O) = 0 and the input terminal IN
11 shows the case where the potential of the input changes from high to low, and FIG. 11 shows the case where the potential of the input terminal IN changes from low to high when fanout (F / O) = 5. Shows the case where fan-out (F / O) = 5 and the potential of the input terminal IN changes from high to low.

Referring to FIG. 9, when the potentials of the input terminal IN, the outputs B, D, F, and the output terminal OUT are all at the low level,
It is assumed that the potentials of outputs A, C, E, and G are all at high level. At this time, when the potential of the input terminal IN changes from low level to high level, the transistor Q _1p turns off and the transistor Q _1n turns on. As a result, the potential of the output A of the inverter INV ₁ (Q _1p , Q _1n ) drops. At this time, since the transistors Q _2p , Q _3p , and Q _4p are still in the ON state, the potentials of the outputs C, E, and G also decrease. Output like this
The decrease of each potential of C, E, G is caused by the inverter INV ₂ (Q _1'P , Q
_1'n ) output B continues until the threshold value of the P-channel transistor is reached. On the other hand, as the potential of the output A decreases, the inverter INV ₂ (Q _1'P , Q _1'n )
Output B rises, but at this time, transistor Q
_{Since 2'n} , Q _3'n and Q _4'n are still in the ON state, the potentials of the outputs D, F and the output terminal OUT also rise with the output B. Then, when the potential of the output B reaches the threshold value, the transistor Q _2p is cut off, so that the outputs C, E and G are temporarily not discharged. further,
When the potential of the output B rises, the potential of the output C is temporarily held, so the transistor Q 2 ′ _n is cut off, and as a result, only the potential of the output B rises. Therefore, the output C of the inverter INV ₃ (Q _2p , Q _2n ) decreases again. At this time, since the transistors Q _3p and Q _4p are still in the ON state, the potentials of the outputs E and G also decrease. Such a decrease in each potential of the outputs E and G _{causes the} inverter INV ₄ (Q _2'P , Q
The output D of _2'n ) continues until the threshold value of the P-channel transistor is reached. When the potential of output D reaches this threshold value, transistor Q _3p
Cut off, so that the outputs E, G are temporarily not discharged. Further, when the potential of the output D rises, the potential of the output E is temporarily held, so that the transistor Q
_3'n is cut off, so that only the potential of the output D rises. Therefore, the output E of the inverter INV ₅ (Q _3p , Q _3n ) decreases again. At this time, since the transistor Q _4p is still in the ON state, each potential of the output G also drops. Such a decrease in each potential of the output G causes the inverter INV ₆ (Q
The output F of _3'p , Q _3'n ) continues until the threshold value of the P-channel transistor is reached. When the potential of the output F reaches this threshold value, the transistor Q _4p is cut off, so that the output G is temporarily not discharged. Further, when the potential of the output F rises, the potential of the output G is temporarily held, so the transistor Q 4 ′ _n is cut off, and as a result, only the potential of the output F rises. Therefore, the output G of the inverter INV ₇ (Q _4p , Q _4n ) decreases again, and as a result, the potential of the output terminal OUT increases.

Conversely, when the potentials at the input terminal IN, outputs B, D, F, and output terminal OUT are all at high level, and the potentials at outputs A, C, E, G are all at low level, When the potential of the terminal IN changes from high level to low level, each potential changes as shown in FIG. The details are the same as in the case of FIG.

In this way, saddle points occur in the changes in the potentials of the outputs C, E, G and the outputs B, D, F, and therefore the delay time increases.

If the fanout number is set to 5, for example,
FIG. 9 changes as shown in FIG. 11, and FIG. 10 changes as shown in FIG. The waveform of the output terminal OUT becomes dull and the delay time becomes even longer.

However, in any case, a delay time of 7 ns or more can be secured, which is longer than in the case of FIG.

FIG. 13 is a circuit diagram showing another embodiment of the delay circuit according to the present invention. In FIG. 13, the output B of the inverter INV ₂ (Q _1'p , Q _1'n ) of the inverter means INVB is used to output the inverter INV ₃ (Q _2p , Q _2n ), INV ₅ (Q
_3p , Q _3n ), INV ₇ (Q _4p , Q _4n ) are driven at the same time, and the output of the inverter INV ₇ (Q _4p , Q _4n ) of the inverter means INVA causes the inverter INV ₄ (Q _2'p , Q of the inverter means INVB).
Q _2'n ), INV ₆ (Q _3'p , Q _3'n ), INV ₈ (Q
_4'p , Q _4'n ) are driven simultaneously. In such a circuit of FIG. 13, for example, when the potentials of the input terminal IN and the output B are at the high level and the potentials of the outputs A and C are at the low level, the potential of the input terminal IN is from the high level to the low level. When it changes to, the output A changes from low level to high level. At this time, since the potential of the output C is low level, the P-channel transistors Q 2 ′ _p , Q 3 ′ _p and Q 4 ′ _p are in the ON state, and the potential of the output A is high level. The N-channel transistor _Q1'n is on. Therefore, the potential of the output B is the transistor _{Q 2'p, Q 3'p,} changes in DC stable point of the impedance ratio of _{Q 4'P} the transistor _{Q 1'n.} As a result, both the P-channel transistors Q _2p , Q _3p , Q _4p and the N-channel transistors Q _2n , Q _3n , Q _4n tend to turn on, so that the high level potential of the output A is transmitted to the output C and the output C is High level, therefore output terminal OUT
Potential becomes low level. With this configuration,
An unsteady waveform is less likely to occur at the output terminal OUT as compared with the embodiment shown in FIG.

In the above embodiment, each inverter means IN
The same number of P-channel transistors and N-channel transistors are cascade-connected to VA and INVB, but it goes without saying that the number of the transistors can be changed arbitrarily.
Further, an inverter as a waveform shaping means may be connected to the circuits shown in FIGS. 1 and 13.

As described above, according to the present invention, when the same number of basic cells are used, the drive capacity of each inverter is reduced by feedback control as compared with the conventional case where the inverters are simply connected in multiple stages. Therefore, the delay time can be increased. In other words, when obtaining the same delay time, the area of the delay circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a delay circuit according to the present invention, FIG. 2 is a partial circuit diagram of a gate array LSI in which no delay circuit is inserted, and FIG. 3 is for explaining the circuit operation of FIG. 4 is a partial circuit diagram of a gate array LSI in which a delay circuit is inserted, FIG. 5 is a timing diagram for explaining the circuit operation of FIG. 4, and FIG. 6 is a circuit showing a conventional delay circuit. FIGS. 7, 7 and 8 are conceptual circuit diagrams for making the circuit of FIG. 1 easier to understand, FIGS. 9 to 12 are timing diagrams of signals appearing in the circuit of FIG. 1, and FIG. It is a circuit diagram which shows the other Example of the delay circuit of invention. IN: Input terminal, OUT: Output terminal, V _CC : Power supply, INVA, INVB: Inverter means, Q _1p , Q _2p ,…: P-channel transistor, Q
_1n , Q _2n , ...: N-channel transistor.

Claims (2)

[Claims] 1. An input terminal, an output terminal, first and second power supply means, and a plurality of P-channel transistors and N-channel transistors of the same number which are connected in series between the first and second power supply means. The first and second inverter means are connected, and the outermost P-channel / N-channel transistor pair of the first inverter means is driven by the potential of the input terminal to drive the first inverter means. The common output of the P-channel / N-channel transistor pair sequentially drives the P-channel / N-channel transistor pair of the second inverter means from outside to inside, while the driven P-channel / of the second inverter means is driven. Driving the P-channel / N-channel transistor pair of the first inverter means sequentially from the outside to the inside by each common output of the N-channel transistor pair, A delay circuit in which the output of the central P-channel / N-channel transistor pair of the second inverter means is connected to the output terminal. 2. An input terminal, an output terminal, first and second power supply means, and a plurality of P-channel transistors and N-channel transistors of the same number connected in series between the first and second power supply means. The first and second inverter means, the outermost P-channel / N-channel transistor pair of the first inverter means is driven by the potential of the input terminal, and the outermost P-channel of the first inverter means is provided. The common output of the / N-channel transistor pair drives the outermost P-channel / N-channel transistor pair of the second inverter means, and the common output of the outer-most P-channel / N-channel transistor pair of the second inverter means P-channels inside the first inverter means
/ N channel transistor pair is driven, and the plurality of P channel / N channel transistor pairs inside the second inverter means are driven by the common output of the plurality of P channel / N channel transistor pairs inside the first inverter means. A delay circuit for driving and connecting the outputs of a plurality of P-channel / N-channel transistor pairs inside the second inverter means to the output terminal.