JPH0357480B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention samples an input waveform, performs linear interpolation, and then performs multi-step luminance interpolation.
The present invention relates to a dot display signal generation circuit attached to a dot type waveform display device such as a cathode ray tube display device or a recorder for converting dot display data stored in a waveform processing device into an analog dot display signal.

[Problems to be solved by conventional technology and invention]

In a dot-type waveform display device, the waveform processing device stores dot display data in a dot pattern in RAM with a capacity corresponding to the time axis address x amplitude address on the display screen, and displays the total amplitude for each time axis address. The address is read and scanned to generate a dot display signal. Therefore,
This naturally increases the capacity of the RAM, and when performing luminance interpolation, there is a problem in that the capacity doubles by the number of bits required to provide luminance information for each dot data.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a dot display signal generation circuit of the type mentioned at the beginning, which can reduce the storage capacity of a RAM for storing dot display signals in a waveform processing device.

[Means and actions for solving problems]

In order to achieve this object, the present invention provides a dot display signal generation circuit for a dot type waveform display device.
It was configured as shown in the figure. From the waveform processing device, only a top address and a bottom address for each time-axis address on the display surface, as well as multi-bit luminance interpolation data for performing luminance interpolation in the amplitude address direction based on both of these addresses, are received. Circuit portions 1 to 4 for each bit generate serial logic signals in which the brightness information is the bottom side brightness interpolation data in the amplitude address direction, while circuit portions 1a to 4a generate serial logic signals that use the top side brightness interpolation data as the brightness information. Therefore, the gate circuit 5 generates a dot display signal interpolated with linear and luminance interpolation between the bottom and top addresses. When such a gate output is analogized as a parallel digital input of the D/A converter 6 along with other bits, a luminance signal of three stages, that is, two or more bits can be obtained.

For example, as shown in FIG. 3a, dots whose luminances are interpolated in four stages (●, square, circle, the luminance decreases in this order) are displayed on the display surface. In the RAM of the waveform processing device, for example, a bottom address n and a peak address n+4, which are the standards for luminance interpolation, are stored for the time axis address N, and further, luminance interpolation data on the bottom address side in the increasing direction of the amplitude address (○, 〓 , ●) are set to 2 bits (01, 10, 11) according to FIG. 3b, and the brightness interpolation data on the top address side is similarly stored as (11, 10, 01).

When displaying address N, please refer to Figure 1.
The latch circuit 4 of the b ₀ digit circuit section receives b ₀ digit data (101) of the bottom address side luminance interpolation data, and the latch circuit 4a receives the b ₀ digit data (101) of the top address side luminance interpolation internal data. Keep it locked. When the clock count reaches the bottom address n, the bottom address comparator 2 outputs an output, and the bottom address shift register 3 starts to advance, and as shown in FIG. Outputs the value and then outputs “1”. On the other hand, the top address shift register 3a outputs "1" until the count reaches the peak address n+4, at which point it outputs the preset value, and thereafter outputs "0", as shown in FIG. 3d. . Therefore, the gate circuit 5 outputs _b0 -digit linear/luminance interpolated data (Fig. 3e).

In the same way, latch circuits 4 and 4 of the circuit section for b ₁ digit
B ₁ -digit bottom address and bottom address side luminance interpolation data (011) and (110) are latched in a, and the gate circuit 5 outputs B _1- digit linear/luminance interpolation data (FIG. 3 f). D/A converter 6
A dot display signal whose level changes in four stages corresponding to FIG. 3a is output from the dot display signal (FIG. 3g).

[Embodiments of the invention]

In FIG. 2, reference numeral 10 denotes a waveform processing device that creates dot display data that has been subjected to linear interpolation as shown in FIG. That is, in that RAM, as shown in FIG. 3b, for each time axis address as described above, high brightness ● is (11), medium brightness 〓 is (10), low brightness ○ is (01), For non-luminance, there are 2 parallel bits b ₀ and b ₁ of brightness interpolation data per address (00), and 4 top and bottom addresses that serve as the reference for the display position of these interpolation data and linear interpolation data.
Types of data are stored.

Reference numeral 20 denotes a dot display signal generation circuit according to the present invention attached to the cathode ray tube display device 30, which converts dot display data read out from the waveform processing device 10 to generate an analog dot display signal. This circuit includes signal processing sections 20a and 20b having the same configuration for the first bit _b0 and the second bit _b1 , a D/A converter 26 that converts these 2-bit output signals into analog signals, and a clock counting circuit. , an address counter 27 which is cleared every vertical raster scan of the cathode ray tube display 30, and a clock generator 28 which generates this clock. Each of the signal processing units 20a and 20b includes a bottom address latch circuit 2 corresponding to FIG.
1, a latch circuit 21a for top address,
A latch circuit 24 for the bottom address side luminance interpolation data, a latch circuit 24a for the top address side luminance interpolation data, a comparator 22 that generates an output signal when the clock count value reaches the latched bottom address, and a clock count value. Comparator 2 generates an output signal when reaches the latched top address.
2a, a shift register 23 which is preset with the bottom side luminance interpolation data of the latch circuit 24 and which starts a stepping operation by a clock with the output signal of the comparator 22, and a shift register 23 which is preset with the top side luminance interpolation data of the latch circuit 24a; and a shift register 23a that starts a clock increment operation with the output signal of the comparator 22a, and both shift registers 23, 23a.
AND gate 25 that performs an AND operation of the output signals of
It is composed of.

The cathode ray tube display device 30 sequentially displays the output signals of the D/A converter 26, which are output in synchronization with the counting operation of the address counter 27 and the clock of the clock generator 28, on its display surface by vertical raster scanning. Note that the output of the shift register 23a is normally at H level, and starts sending out the preset value in response to the output of the comparator 22a.

The operation will be explained with reference to FIG.

When displaying a waveform, the waveform processing device 10 sequentially sends the top address and bottom address of each time axis address .
For example, a certain time axis address N in FIG.
, the latch circuits 21 of both signal processing units 20a and 20b latch the bottom address n, and the latch circuits 21a latch the top address n+4. On the other hand, the latch circuits 24 and 24a of the signal processing section 20a contain the interpolated value (101) on the bottom address side of the _b0 digit and the interpolated value (101) on the top address side, and the latch circuits 24 and 24 of the signal processing section 20b.
a is b ₁ -digit bottom address side interpolated value (011)
and the interpolated value (110) on the top address side are respectively latched.

The address counter 27 starts clock counting, and when the counted value reaches the bottom address n, the shift register 23 starts an increment operation, and performs the operations corresponding to FIG. 26 outputs a dot pulse signal (FIG. 3g) whose level changes in four stages for brightness modulation, and the cathode ray tube display device 30 displays dots of brightness corresponding to the level.

For the next time axis address N+1, the bottom address n+4 is sent to the dot display signal generation circuit 20.
Top address n+7 is sent. In this case, the bottom address side luminance interpolated data sent out is the same as that of the time axis address N, and the top address side luminance interpolated data is (11, 00, 00). Therefore, the output of the AND gate with b ₀ digits is shown in Figure 3 h
Therefore, the output of the D/ _A converter 26 is as shown in FIG. 3, and therefore the output of the D/A converter 26 is shown in FIG.

For time axis address N+4 where the top address and bottom address match, n is sent to both the top address and bottom address, and the bottom address side luminance interpolation data (11, 00, 00) and the top address side luminance interpolation data (11, 00) are sent. , 00). Therefore, the outputs of the shift register 23 for both digits b ₀ and b ₁ are both as shown in FIG. 3k, and the output of the shift register 23a is as shown in FIG. 3l. The outputs of the AND gate 25 of b ₀ and b ₁ are both m in Fig. 3, and D/
The output of the A converter 26 is as shown in FIG. 3n. In this way, the cathode ray tube display device displays the dot display data from the waveform processing device 10 for the time axis address . The waveform shown in is displayed.

In the above embodiment, if the scanning direction of the amplitude address is reversed, the relationship between the top and bottom is reversed. Depending on the circuit configuration, shift registers 23, 23a
Various modifications can be made within the scope of the present invention, such as inverting the output level of.

〔Effect of the invention〕

As described above, according to the hard logic type dot display signal generation circuit of the present invention, the capacity of the RAM of the waveform processing device can be calculated by multiplying the amplitude address by the amplitude address for each time axis address.
The brightness interpolation data of multiple bits, which interpolates the brightness in the direction of the amplitude address based on the top address, bottom address, and both of these addresses, is simply stored as dot display data without corresponding to bits, which greatly reduces the memory capacity. make it possible to achieve significant reductions.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a dot display signal generation circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a dot display signal generation circuit according to an embodiment of the present invention, and FIG.
FIG. 2 is a diagram illustrating the operation of the circuit.

Claims (1)

[Claims] 1 The dot display data of the waveform processing device, which samples the input waveform, performs linear and luminance interpolation, and stores it in RAM, is transferred to the dot display signal of the corresponding amplitude address on the display screen of the dot-type waveform display device on the time axis. In a dot display signal generation circuit for a dot type waveform display device that successively converts each address,
Latch circuits 1 and 21 for the bottom address of the dot display data, latch circuits 1a and 21a for the top address of the dot display data, latch circuits 4 and 24 for the bottom address side luminance interpolation data of the dot display data, and the latch circuits 4 and 24 for the bottom address side luminance interpolation data of the dot display data. Data top address side luminance interpolation data latch circuit 4a,
24a, a bottom address comparator 2, 22 which outputs an output signal in which the count value of the amplitude direction address obtained by counting the clocks reaches the output value of the bottom address latch circuits 1, 21; Address latch circuit 1a, 21
The top address comparators 2a and 22a generate an output signal when the latch value of a is reached, and the increment by the clock is controlled by the output of the bottom address comparators 2 and 22, and the bottom side luminance interpolated data is The bottom address shift registers 3, 23 are preset, and the top address shift registers whose increment by the clock is controlled by the outputs of the top address comparators 2a, 22a, and the top address side luminance interpolation data are preset. A circuit section comprising registers 3a, 23a, and gate circuits 5, 25 for generating an AND signal of the input signals between the bottom address and the top address using the output signals of the shift registers as both input signals. A dot according to the number of bits of the luminance interpolation data, and further followed by D/A converters 6, 26 which receive the output signals of the gate circuits 5, 25 of each circuit section as parallel digital inputs. Display signal generation circuit.