JPH0359655B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a static overcurrent detection device for detecting a fault current in an AC circuit in order to optimally protect and monitor an AC circuit.

[Prior Art] Conventionally, this type of device includes a device that detects the maximum value of the current in each phase as shown in Fig. 1, and a device that detects the effective value or average value of the current in each phase as shown in Fig. 2. There was a device to detect the value.

In the configuration of the conventional maximum value detection type device shown in FIG.
Current transformer 2 as current sensor means for each phase of T
1, 22, and 23 are provided, respectively. When a fault current flows through the electric line 10, each current transformer 21, 2
Full-wave rectifier circuit 3 provided on the secondary side of 2 and 23
1, 32, and 33 are connected in series with the same polarity, and the maximum value of the fault current is converted into a direct current and detected by the maximum value detection circuit 30. Full wave rectifier circuit 31, 3
The output signal waveform according to No. 2, 33 is shown in FIG. A burden circuit 40 is connected to the output side of the maximum value detection circuit 30. This load circuit 40 includes a current transformer 21,
It converts the output currents 22 and 23 into voltage signals, and also serves as a level adjustment circuit (for example, a circuit in the form of a potentiometer with an appropriate voltage division ratio) for obtaining an output signal within a predetermined level range. The output voltage waveform of the burden circuit 40 is shown by a solid line in FIG. A level determination circuit 50 connected to the output side of the burden circuit 40 determines whether the output signal level of the burden circuit 40 is below a predetermined value. Next, a time limit generation circuit 60 is connected which performs a predetermined time limit operation according to the input signal level. When the level determination circuit 50 determines that the output signal level of the burden circuit 40 is equal to or higher than a predetermined value, it issues a signal to the time limit generation circuit 60. The time limit generation circuit 60 performs a predetermined time limit operation according to the input signal level (ie, the output signal level of the burden circuit 40) from the time it receives the signal issued by the level discrimination circuit 50. Generally, the relationship between the input signal level and the generation time limit has an inverse time limit characteristic as shown in FIG. 5, which takes into account the heat resistance of the power distribution line (electric circuit) to be protected. When the time limit based on the predetermined time characteristic has elapsed after the time limit generation circuit 60 starts the time limit operation as described above, the time limit generation circuit 60 provides an output signal to the output circuit 70. Output circuit 70
responds to this signal and drives the output device 80.

As described above, the device shown in FIG. 1 detects the presence of a fault current in a certain phase without determining which phase it is.
Generally, the voltage induced in the load circuit 40 connected to the output side of the maximum value detection circuit 30 as described above has a waveform as shown in FIG. Due to the configuration of the maximum value detection circuit 30, the voltage waveform induced in the burden circuit 40 necessarily differs depending on the magnitude of the current in each phase. Furthermore, with the circuit configuration described above, it is essentially impossible to convert the waveform into a signal corresponding to an effective value or an average value, and only the peak of the maximum value is detected. That is, the configuration of the apparatus shown in FIG. 1 is essentially of the peak detection type. For this reason, it is not possible to perform accurate fault current detection by performing waveform conversion to obtain the average value or effective value of the current for each phase of the electrical circuit.

Therefore, the current for each phase is converted to voltage, and when an overcurrent occurs in even one phase, a detection signal is extracted only from the output from the phase where the overcurrent occurred. Therefore, a detection circuit for each phase as shown in FIG. 2 was devised.

Next, a conventional device having an effective value or average value detection type configuration for each phase shown in FIG. 2 will be explained. In FIG. 2, parts corresponding to those in FIG. 1 are indicated using the same reference numerals. When a fault current flows through the AC line 10, the AC transformers 21, 22, and 23 of each phase detect the fault current at their own current transformation ratios and induce an output current on the secondary side. Each of these output currents is converted into a direct current by full-wave rectifier circuits 31, 32, and 33, respectively.
This DC full wave rectifier circuit 31, 32, 33
The output current of each corresponding load circuit 41, 42, 4
3, respectively. At this time, burden circuit 4
The signal voltage waveforms induced at 1, 42, and 43 are as shown in FIG. Each burden circuit 41, 42,
The output signals of 43 are converted for each phase by a waveform conversion circuit 90 into signals corresponding to their effective values or average values. The output signal of the waveform conversion circuit 90 is input to the level discrimination circuit 50 for each phase. When the level determination circuit 50 determines that the input signal level is equal to or higher than a predetermined value, it issues a signal to the time limit generation circuit 60. The time limit generating circuit 60 starts a predetermined time limit operation according to the input signal level (that is, the input signal level of the level discriminating circuit 50) from the time it receives the signal generated by the level discriminating circuit 50. The relationship between this input signal level and the generation time limit has an inverse time limit characteristic as shown in FIG. 5, which takes into consideration the heat resistance of the distribution line (electrical circuit) to be protected, as explained for the device in FIG. 1. It's set. When the time limit based on the predetermined time characteristic has elapsed after the time limit generation circuit 60 starts the time limit operation as described above, the time limit generation circuit 60 provides an output signal to the output circuit 70. Output circuit 70 responds to this signal and drives output device 80.

In the device shown in FIG. 2, the fault currents of each phase are converted into waveforms into effective values or average values, and are detected accurately. On the other hand, since the fault current is detected via the waveform conversion circuit 90, there is a delay in response. This is because the waveform conversion circuit 90 essentially has to include an integral element, so it has a response characteristic with a relatively long time constant. Therefore, the device shown in FIG. 2 is not suitable for detecting large currents that increase instantaneously, such as short-circuit currents.

[Problems to be Solved by the Invention] The first conventional example has the drawback that accurate thermal detection cannot be performed in principle when a distorted current including a current other than the commercial frequency is flowing in an AC line. It was hot.

The second conventional example has a drawback that instantaneous overcurrent cannot be detected because the time constant is long.

[Summary of the Invention] The present invention aims to provide a novel device of this type that solves the problems of the conventional devices as described above. That is, if the magnitude of the overcurrent is within a predetermined range, the overcurrent of each phase is detected relatively sensitively using the same method as in the second conventional example, while the overcurrent of any phase is detected relatively sensitively. If an overcurrent that significantly exceeds a predetermined range occurs, the device immediately responds to the maximum value and detects a short-circuit current or the like.

[Embodiments of the invention]

The present invention will be clarified by describing embodiments of the present invention in detail below using the drawings.

FIG. 6 is a block diagram showing a static overcurrent detection device as an embodiment of the present invention. In FIG. 6, current transformers 21, 22, 23 for detecting current are provided for each phase of a plurality of phases (three phases R, S, and T in this example) of the electrical circuit.
are provided for each. Each current transformer 21, 2
Full-wave rectifier circuits 31, 32, and 33 are connected to the secondary sides of 2 and 23, respectively, for obtaining the absolute value of the secondary output. Each full wave rectifier circuit 31, 32, 33
Burden circuits 41, 42, and 43 are connected to the output side of each. The load circuits 41, 42, and 43 convert the output currents of the current transformers 21, 22, and 23 into voltage signals, and also serve as level adjustment circuits for obtaining output signals within a predetermined level range. The first output terminals (output terminals of level-adjusted signals) of each of the load circuits 41, 42, and 43 are connected to a waveform conversion circuit 90, respectively. The waveform conversion circuit 90 is for obtaining the effective value or average value of the output signal induced in each burden circuit 41, 42, 43. Each second of the burden circuits 41, 42, 43
The output terminals of are diodes 131 and 13, respectively.
It is connected to each input terminal of an OR circuit 130 consisting of 2,133 circuits. In addition, each of the burden circuits 41, 4
The ends of terminals 2 and 43 on the opposite side from the second output terminal are connected to a common potential point (ground point). The above current transformers 21, 22, 23, full wave rectifier circuits 31, 3
2, 33, load circuits 41, 42, 43, waveform conversion circuit 90 and OR circuit 130 (131+132
+133) constitutes a current sensor means 200 for detecting the current of the AC line 10. That is, the current sensor means 200 receives the first signal from the waveform conversion circuit 90.
A signal corresponding to the effective value or average value of the current for each phase of the AC line 10 is output as an output signal.
Further, the OR circuit 130 outputs a signal corresponding to the maximum value of the current flowing through the AC line 10 as a second output signal. The output side of the OR circuit 130 is the second
Zener diode 1 as a means of determining the level of
It is connected via 40 to a time limit generation circuit 150 as a second time limit generation means. Time limit generation circuit 1
The output terminal of 50 is connected to the gate of thyristor 120. Further, an analog multiplexer/A/D conversion circuit 100 is provided which selects each output signal of the waveform conversion circuit 90 in a time-divisional manner and performs A/D conversion. Each output of the analog multiplexer/A/D conversion circuit 100 is connected to the microcomputer 1.
10 is input. In this embodiment, a power supply circuit 160 is provided as a power supply for operating the analog multiplexer/A/D conversion circuit 100 and the microcomputer 110.
Further, the configuration is such that the output signal of the microcomputer 110 is applied to the gate of the thyristor 120. An output device 80 having an output terminal 81 is connected in series to the thyristor 120.
Note that the first and second time limit generating means described above may be provided with separate first and second output means, but in this example, these output means are provided in a single output device 80 as described above. It is summarized.

The configuration of the microcomputer 110 is
The following is an overview based on the block diagram in Figure. In FIG. 7, the microcomputer 110 includes a CPU 111
The circuit includes a ROM 114, a RAM 115, and an I/O port 116 via a data bus 112 and an address bus 113, and a portion of the data bus 112 and address bus 113 are connected to the analog multiplexer/A/D conversion circuit 100. has been done. Generally, the ROM 114 includes a program for executing predetermined signal processing, and the CPU 111 executes the program in synchronization with a predetermined clock signal. Further, the RAM 115 functions as a register necessary for signal processing.

The signal processing process in the above-mentioned microcomputer 110 is shown in the main flowchart of FIG. This flowchart includes at least a first level determining means 10 for the input signal as a basic function.
01 and a first time limit generating means 1002 that executes a predetermined time limit operation based on the level determined value. Further, in this flowchart, when the input signal to at least one of the first time limit generating means 1002 or the second time limit generating means 150 (FIG. 6) becomes below a predetermined level, a predetermined heat dissipation characteristic ( A reset means 1003 is included which is configured to perform a reset operation over time with a reduction rate in accordance with the heat dissipation characteristics of the electrical circuit and the load.

The operation of the apparatus of the present invention configured as described above will be explained below.

When a fault current flows through the AC line 10, the current transformers 21, 22, and 23 of each phase detect the fault current at their own current transformation ratios and induce an output current on the secondary side. Each of these output currents is connected to the full-wave rectifier circuit 3.
1, 32, and 33 convert it into a direct current. The output currents of the full-wave rectifier circuits 31, 32, and 33 converted into direct current are supplied to the corresponding burden circuits 41, 42, and 43, respectively. At this time, burden circuits 41, 42, 43
The signal voltage waveform induced in this case has a shape as shown in FIG. The output signals of the burden circuits 41, 42, and 43 are converted for each phase by a waveform conversion circuit 90 into signals corresponding to their effective values or average values.
The effective value or average value output of the waveform conversion circuit 90 is input to an analog multiplexer/A/D conversion circuit 100. An analog multiplexer/A/D conversion circuit 100 is controlled by a microcomputer 110 to time-divisionally select input signals and convert them into digital signals. These digital signals are supplied to microcomputer 110. The microcomputer 110 executes level determination of these digital input signals according to a predetermined program. Further, based on the result of this level determination, a predetermined time-limited operation is performed and an output signal is generated from the output port 116. That is, microcomputer 1
Reference numeral 10 functions as a first level determining means and a first time limit generating means. In this case, the time limit operation is performed, for example, along the inverse time limit characteristic for long time limits in the characteristic curve of FIG. Microcomputer 1
The output signal issued from the ten output ports 116 is applied to the gate of the thyristor 120. Thyristor 120 is triggered by this signal and turns on to drive output device 80. Output device 80
An output signal for displaying the fault current or driving the circuit protection means is obtained from the output terminal 81.

On the other hand, the voltage signal corresponding to the fault current induced in the burden circuits 41, 42, 43 is transmitted to the OR circuit 130 consisting of diodes 131, 132, 133.
is input. The output side of the OR circuit 130 is a Zener diode 14 as a second level discrimination circuit.
Since the output level of the OR circuit 130 exceeds the Zener voltage of the Zener diode 140, a signal is input to the time generator circuit 150 via the zener diode 140. The time limit generation circuit 150 performs a predetermined time limit operation based on this signal and triggers the gate of the thyristor 120. In this case, the time limit operation is performed, for example, along the short time limit inverse time limit characteristic and the instantaneous characteristic in the characteristic curve of FIG. Thyristor 120 is triggered and turned on to drive output device 80 as described above. In this case, as described above, an output signal for displaying a fault current or protecting a circuit can be obtained from the output terminal 81 of the output device 80. It is also recommended to use an open-circuit element with low power consumption as the output device 80. In the above, we have detailed an example in which a diode is used as an OR circuit, but in order to effectively form an OR circuit using a part of a microcomputer (low power consumption such as C-MOS) Of course, it may also be constructed using shaped elements.

Next, the signal processing process in the microcomputer 110 will be explained in detail along the main flowchart of FIG.

First, when the microcomputer 110 is activated and becomes operational, the program starts, initializes the system (i.e., I/O port settings, flag settings, resets, etc.), and enters the main processing flow for overcurrent detection. . Next, a control operation (A/D conversion process) of the analog multiplexer/A/D conversion circuit 100 is executed. Through this control operation, the signal of the effective value or average value of the current corresponding to each phase of the electric circuit outputted from the waveform conversion circuit 90 is selected in a time division manner and converted into a digital signal,
It is written to the RAM 115 in the microcomputer 110. Next, as described above, the RAM115
Regarding the input signal data written in, an operation is performed to determine whether or not the value is an overcurrent value. As a result, if there is no overcurrent, the process exits from the heat storage routine shown in FIG. 9 and returns to the A/D conversion process described above. Next, if there is an overcurrent, the heat storage flag H is set first, and the CPU register or
Using the RAM 115, a predetermined number of heat storage bits is added every predetermined unit time. The predetermined number of heat storage bits is selected to realize a time-limited operation along the characteristic curve shown in FIG. Next, an operation is performed to determine whether the number of bits added as described above has reached a value corresponding to a predetermined time period. As a result, if the number of bits added has not reached the value corresponding to the predetermined time limit, the process deviates from the main flow in FIG. 9 and returns to the A/D conversion process described above.
Next, if the above-mentioned added bit number reaches a value corresponding to a predetermined time period, the I/O port 116
Trigger the thyristor 120 via the output device 8
Drive 0.

Next, a time limit reset method (cooling routine) will be explained. As mentioned above, if the A/D converted data falls below a predetermined level when the heat storage flag H is set and the time-limited time measurement operation is in progress, the routine for determining whether or not there is an overcurrent is executed. Then, an operation is performed to determine whether or not the heat storage flag H indicating the state at the stage immediately before the relevant stage is set. As a result, the heat storage flag H
If not set, the process returns to the A/D conversion process. Next, if the heat storage flag H is set, a predetermined number of heat radiation bits is subtracted every predetermined unit time from the number of bits added and counted in the heat storage routine as described above. If the bit count value becomes 0 as a result of this subtraction, the heat storage flag H is reset and the process returns to the A/D conversion process. Also, if the bit count value is not completely reset, the heat storage flag H is not reset and the A/
Return to the D conversion process. As described above, optimum thermal properties are obtained. Note that it goes without saying that the addition and subtraction of heat storage and heat radiation can be performed in the opposite manner to the above to achieve the same function.

Microcomputer 11 in the above embodiment
If the function of 0 is to be realized by an analog circuit, it is theoretically possible to achieve this by, for example, configuring a normal integrating circuit to control the charging/discharging time constant.

In this embodiment, as understood from FIG.
In a region where the fault current of the electric circuit is relatively small, a detection operation is performed based on the effective value or average value of the current of each phase and in accordance with the operating characteristics over a relatively long period of time, so that the electric circuit and load can be optimally protected. On the other hand, in areas where the fault current is relatively large, a faster detection operation is performed in accordance with the operating characteristics in a relatively short period of time, taking into account the fusing characteristics of fuses installed above the electrical circuit, and appropriate protection of the electrical circuit is carried out. It can be done. Furthermore,
When a large current that rapidly increases, such as a short circuit current, flows, an instantaneous response can be taken.

In the above-described embodiment, an alternator is used as the current sensor means, but instead of this, it is also possible to use a Hall element, a magnetoresistive element, or a combination of these and an amplifier. Further, as a means for obtaining the absolute value of the detected current, a known means using an operational amplifier can be applied. It is also possible to arbitrarily adopt a configuration in which the output signals of the first time limit generating means and the second time limit generating means described above are used separately to determine the cause of the operation.

[Effects of the Invention] In summary, the device of the present invention can deal with relatively small fault currents flowing during overload, etc. by using effective values or average values measured for each phase. Even when the fault current is distorted, an appropriate and accurate detection operation takes into account the amount of heat accumulated in the line or load excessively generated due to overcurrent. On the other hand, for large overcurrents such as short-circuit currents that require emergency shutoff, the maximum value is directly detected without going through a circuit with a long time constant such as waveform processing, and based on this detected value (waveform processing, etc.) Detection operations for circuit breakage, etc. are performed immediately (without causing delay time).

[Brief explanation of drawings]

1 and 2 are block diagrams showing conventional static overcurrent detection devices, FIGS. 3 and 4 are signal waveform diagrams for explaining the operation of the static overcurrent detection device, and FIG. 5 is a block diagram showing a conventional static overcurrent detection device. A characteristic diagram showing the heat resistance characteristics of the electric circuit and the inverse time characteristics of the static overcurrent detection device,
FIG. 6 is a block diagram showing a static overcurrent detection device as an embodiment of the present invention, FIG. 7 is a block diagram showing the configuration of a microcomputer applied to the static overcurrent detection device of FIG. 6, and FIG. Figure 8 is a characteristic diagram showing the fusing characteristics of the electric circuit and the upper fuse, as well as the detection characteristics of the static overcurrent detection device of the present invention, and Figure 9 is a flowchart of the basic operation of the microcomputer in the static overcurrent detection device of the present invention. It is. 10... AC line, 21, 22, 23... Current transformer, 31, 32, 33... Full wave rectifier circuit, 40,
41, 42, 43... Burden circuit, 50... Level discrimination circuit, 60... Time limit generation circuit, 70... Output circuit, 80... Output device, 90... Waveform conversion circuit, 100... Analog multiplexer A /D
Conversion circuit, 110...Microcomputer, 1
20...Thyristor, 130...OR circuit, 14
0... Zener diode, 150... Time limit generation circuit.

Claims (1)

[Scope of Claims] 1. Means provided corresponding to each phase of a multi-phase AC circuit and outputting a rectified output for each phase; (a) means for effective or averaging the rectified output for each phase; , a first output signal corresponding to the effective value or average value of the current for each phase, and (a) performing a voltage OR operation of each of the rectified outputs to correspond to the maximum value of the current for each phase. But the voltage
a second output signal that is an OR output; current sensor means for outputting a second output signal; first level determination means for determining the level of the first output signal of the current sensor means; and an output signal of the first level determination means. a first time limit generation means that starts a predetermined time limit operation based on the first time limit generation means, a first output means that operates based on an output signal of the first time limit generation means and generates a signal for protecting the electric circuit, and the current sensor means. second level determining means for determining the level of a second output signal of the second level determining means; second time limit generating means for starting an instantaneous operation based on the output signal of the second level determining means; A static overcurrent detection device comprising: second output means that operates based on the output signal of the means and promptly issues a signal for protecting the electric circuit. 2. At least one of the first and second time limit generation means includes a reset means, and the reset means performs a predetermined heat dissipation process when the input signal to the corresponding one of the time limit generation means falls below a predetermined level. The static overcurrent detection device according to claim 1, wherein the static overcurrent detection device is configured to execute a reset operation by determining whether or not heat dissipation is completed based on the characteristics. 3. The static overcurrent detection device according to claim 1, wherein at least the first level determining means and the first time limit generating means are constituted by a microcomputer. 4. The second level determination means and the second time limit generation means are configured and combined without the signal processing of a microcomputer, and the output side of the second time limit generation means is directly connected to the second output means. The static overcurrent detection device according to claim 3, which is connected to the static overcurrent detection device.