JPH0359656B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a static overcurrent detection device for detecting a fault current in an AC circuit in order to optimally protect and monitor an AC circuit.

[Prior art]

Conventional devices of this type include a device that detects the maximum value of the current in each phase as shown in Figure 1, and a device that detects the effective value or average value of the current in each phase as shown in Figure 2. The equipment was hot.

In the configuration of the conventional maximum value detection type device shown in FIG.
Current transformer 2 as current sensor means for each phase of T
1, 22, and 23 are provided, respectively.
When a fault current flows through 0, each current transformer 21, 22,
Full-wave rectifier circuit 31, 3 provided on the secondary side of 23
2 and 33 are connected in series with the same polarity, and the maximum value of the fault current is converted into a direct current and detected by the maximum value detection circuit 30. Full wave rectifier circuit 31, 32, 3
The output signal waveform according to No. 3 is shown in FIG. A burden circuit 40 is connected to the output side of the maximum value detection circuit 30. This burden circuit 40 includes current transformers 21, 22,
It converts the output current of 23 into a voltage signal and also serves as a level adjustment circuit (for example, a circuit in the form of a potentiometer with an appropriate voltage division ratio) for obtaining an output signal within a predetermined level range. The output voltage waveform of the burden circuit 40 is shown by a solid line in FIG. a level discrimination circuit 50 connected to the output side of the load circuit 40;
It is determined whether the output signal level of the burden circuit 40 is below a predetermined value. A time limit generation circuit 60 is connected which performs a predetermined time limit operation depending on the input signal level. The level discrimination circuit 50 is the burden circuit 40
When it is determined that the output signal level of is equal to or higher than a predetermined value, a signal is issued to the time limit generating circuit 60. The time limit generation circuit 60 receives the input signal level (i.e., the burden circuit 4
A predetermined time-limited operation is performed according to the output signal level (0 output signal level). Generally, the relationship between the input signal level and the generation time limit has an inverse time limit characteristic as shown in FIG. 5, which takes into account the heat resistance of the distribution line (electric circuit) to be protected. When the time limit based on the predetermined time characteristic has elapsed after the time limit generation circuit 60 starts the time limit operation as described above, the time limit generation circuit 60 provides an output signal to the output circuit 70. Output circuit 70 responds to this signal and drives output device 80.

As described above, the device shown in FIG. 1 detects the presence of a fault current in a certain phase without determining which phase it is.
Generally, the voltage induced in the load circuit 40 connected to the output side of the maximum value detection circuit 30 as described above has a waveform as shown in FIG. Due to the configuration of the maximum value detection circuit 30, the voltage waveform induced in the burden circuit 40 necessarily differs depending on the magnitude of the current in each phase. Furthermore, with the circuit configuration described above, it is essentially impossible to convert the waveform into a signal corresponding to an effective value or an average value, and only the peak of the maximum value is detected. That is, the configuration of the apparatus shown in FIG. 1 is essentially of the peak detection type. For this reason, it is not possible to perform accurate fault current detection by performing waveform conversion to obtain the average value or effective value of the current for each phase of the electrical circuit.

Therefore, the current for each phase is converted to voltage, and when an overcurrent occurs in even one phase, a detection signal is extracted only from the output from the phase where the overcurrent occurred. Therefore, a detection circuit for each phase as shown in FIG. 2 was devised.

Next, a conventional device having an effective value or average value detection type configuration for each phase shown in FIG. 2 will be explained. In FIG. 2, parts corresponding to those in FIG. 1 are indicated using the same reference numerals. When a fault current flows through the AC line 10, the current transformers 21, 22, and 23 of each phase detect the fault current at their own current transformation ratios and induce an output current on the secondary side. Each of these output currents is converted into a direct current by full-wave rectifier circuits 31, 32, and 33, respectively.
This DC full wave rectifier circuit 31, 32, 33
The output current of each corresponding load circuit 41, 42, 4
3, respectively. At this time, the burden circuit 41,
The signal voltage waveform induced in 42 and 43 has a shape as shown in FIG. Each load circuit 41, 42, 43
The output signals of each phase are converted by the waveform conversion circuit 90 into signals corresponding to their effective values or average values. The output signal of the waveform conversion circuit 90 is input to the level discrimination circuit 50 for each phase. When the level determination circuit 50 determines that the input signal level is equal to or higher than a predetermined value, it issues a signal to the time limit generation circuit 60. The time limit generating circuit 60 starts a predetermined time limit operation according to the input signal level (that is, the input signal level of the level discriminating circuit 50) from the time it receives the signal generated by the level discriminating circuit 50. The relationship between this input signal level and the generation time limit has an inverse time limit characteristic as shown in FIG. 5, which takes into consideration the heat resistance of the distribution line (electrical circuit) to be protected, as explained for the device in FIG. 1. It's set. When the time limit based on the predetermined time characteristic has elapsed after the time limit generation circuit 60 starts the time limit operation as described above, the time limit generation circuit 60 starts the output circuit 7.
Give the output signal to 0. Output circuit 70 responds to this signal and drives output device 80.

In the device shown in FIG. 2, the fault currents of each phase are converted into waveforms into effective values or average values, and are detected accurately. On the other hand, since the fault current is detected via the waveform conversion circuit 90, there is a delay in response. This is because the waveform conversion circuit 90 essentially has to include an integral element, so it has a response characteristic with a relatively long time constant. Therefore, the device shown in FIG. 2 is not suitable for detecting large currents that increase instantaneously, such as short-circuit currents.

[Problems to be Solved by the Invention] The first conventional example has the drawback that accurate thermal detection cannot be performed in principle when a distorted current including a current other than the commercial frequency is flowing in an AC line. It was hot.

The second conventional example has a drawback that instantaneous overcurrent cannot be detected because the time constant is long.

[Summary of the Invention] The present invention aims to provide a novel device of this type that solves the problems of the conventional devices as described above. That is, when the magnitude of the overcurrent is within a predetermined range, the overcurrent of each phase is converted into a signal corresponding to their effective value or average value using the same method as in the second conventional example. Then, overcurrent is detected relatively sensitively based on the maximum value of those signals. On the other hand, if an overcurrent that greatly exceeds a predetermined range occurs in any phase, such as a short-circuit current, etc., the short-circuit current or the like is detected in response to the maximum value immediately.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be clarified by describing embodiments of the present invention in detail below using the drawings.

FIG. 6 is a block diagram showing a static overcurrent detection device as an embodiment of the present invention. In FIG. 6, current transformers 21, 22, 23 for detecting current are provided for each phase of a plurality of phases (in this example, three layers R, S, and T) of the electrical circuit.
are provided for each. Each current transformer 21, 2
Full-wave rectifier circuits 31, 32, and 33 are connected to the secondary sides of 2 and 23, respectively, for obtaining the absolute value of the secondary output. Each full wave rectifier circuit 31, 32, 33
Burden circuits 41, 42, and 43 are connected to the output side of each. The load circuits 41, 42, and 43 convert the output currents of the current transformers 21, 22, and 23 into voltage signals, and also serve as level adjustment circuits for obtaining output signals within a predetermined level range. The first output terminals (output terminals of level-adjusted signals) of each of the burden circuits 41, 42, 43 are connected to the corresponding waveform conversion circuits 91, 92, 93, respectively. The waveform conversion circuits 91, 92, 93 are for obtaining the effective value or average value of the output signal induced in each burden circuit 41, 42, 43. Each output signal of the waveform conversion circuits 91, 92, 93 is outputted by an OR circuit 160 as a first maximum value detection means, which is composed of corresponding diodes 161, 162, 163.
It is designed to be entered in Each of the second output terminals of the load circuits 41, 42, 43 is connected to each input of an OR circuit 130 as a maximum value detection means for obtaining a second output signal of the current sensor means consisting of diodes 131, 132, 133, respectively. connected to the terminal. In addition, each of the burden circuits 41, 4
The ends of terminals 2 and 43 on the opposite side from the second output terminal are connected to a common potential point (ground point). Here, the rectifiers 21, 22, 23, the full wave rectifier circuit 3
1, 32, 33, burden circuits 41, 42, 43, waveform conversion circuits 91, 92, 93, and OR circuit 1
30 (131+132+133) is AC line 10
This constitutes a current sensor means 200 for detecting the current. The OR circuit 130 outputs a signal corresponding to the maximum value of the current flowing through the AC line 10. OR
The output side of the circuit 130 is connected to a time limit generating circuit 150 as a second time limit generating means via a Zener diode 140 as a second level determining means. The output terminal of the time generator circuit 150 is connected to the gate of the thyristor 120. Also,
An A/D conversion circuit 1 receives the maximum output signal of each of the waveform conversion circuits 91, 92, and 93 through the OR circuit 160 and converts it into a digital signal.
00 is set. Each output of the A/D conversion circuit 100 is input to a microcomputer 110. Microcomputer 1
The configuration is such that ten output signals are applied to the gate of the thyristor 120. Thyristor 12
An output device 80 having an output terminal 81 is connected in series with 0. Note that the first and second output means may be provided separately for the first and second time limit generating means described above, but in this example, these output means are provided in a single output device 80 as described above. It is summarized.

The configuration of the microcomputer 110 is
The following is an overview based on the block diagram in Figure. In FIG. 7, the microcomputer 110 includes a CPU 111
The data bus 112 and address bus 113 are connected to a ROM 114, a RAM 115, and an I/O port 116, and a portion of the data bus 112 and address bus 113 are connected to the A/D conversion circuit 100. . Generally ROM114
includes a program for executing predetermined signal processing, and the CPU 111 executes the program in synchronization with a predetermined clock signal. Further, the RAM 115 functions as a register necessary for signal processing.

The signal processing process in the above-mentioned microcomputer 110 is shown in the main flowchart of FIG. This flowchart includes at least a first level determining means 1 of the input signal as a basic function.
001 and a first time limit generation means 1002 that executes a predetermined time limit operation based on the determined value. Furthermore, in this flowchart, when the input signal to at least one of the first time limit generating means 1002 or the second time limit generating means 150 (FIG. 6) becomes below a predetermined level, a predetermined heat dissipation characteristic (electrical circuit and the heat dissipation characteristics of the load).

The operation of the apparatus of the present invention configured as described above will be explained below.

When a fault current flows through the AC line 10, the current transformers 21, 22, and 23 of each phase detect the fault current at their own current transformation ratios and induce an output current on the secondary side. Each of these output currents is connected to the full-wave rectifier circuit 3.
1, 32, and 33 convert it into a direct current. The output currents of the full-wave rectifier circuits 31, 32, and 33 converted into direct current are supplied to the corresponding burden circuits 41, 42, and 43, respectively. At this time, burden circuits 41, 42, 43
The signal voltage waveform induced in this case has a shape as shown in FIG. The output signals of the burden circuits 41, 42, 43 are converted into signals corresponding to their effective values or average values by waveform conversion circuits 91, 92, 93 for each phase. The maximum value of the effective value or average value output of the waveform conversion circuits 91, 92, and 93 is inputted to the A/D conversion circuit 100 via the OR circuit 160. The A/D conversion circuit 100 converts the input signal into a digital signal. These digital signals are supplied to microcomputer 110. The microcomputer 110 executes level determination of these digital input signals according to a predetermined program. Further, based on the result of this level determination, a predetermined time-limited operation is performed and an output signal is generated from the output port 116.
That is, the microcomputer 110 functions as a first level determining means and a first time limit generating means. In this case, the time limit operation is performed, for example, along the inverse time limit characteristic for long time limits in the characteristic curve of FIG. The output signal emitted from the output port 116 of the microcomputer 110 is transmitted to the thyristor 12.
0 gate. Thyristor 120 is triggered by this signal and turns on to drive output device 80. From the output terminal 81 of the output device 80, an output signal for displaying a fault current, protecting a circuit, etc. is obtained.

On the other hand, the voltage signal corresponding to the fault current induced in the burden circuits 41, 42, 43 is transmitted to the OR circuit 130 consisting of diodes 131, 132, 133.
is input. The output side of the OR circuit 130 is a Zener diode 14 as a second level discrimination circuit.
Since the output level of the OR circuit 130 exceeds the Zener voltage of the Zener diode 140, a signal is input to the time generator circuit 150 via the zener diode 140. The time limit generation circuit 150 performs a predetermined time limit operation based on this signal and triggers the gate of the thyristor 120. In this case, the time limit operation is performed, for example, along the short time limit inverse time limit characteristic and the instantaneous characteristic in the characteristic curve of FIG. Thyristor 120 is triggered and turned on to drive output device 80 as described above. In this case, as described above, an output signal for displaying a fault current or protecting a circuit can be obtained from the output terminal 81 of the output device 80. It is also recommended to use an open-circuit element with low power consumption as the output device 80. In the above, we have detailed an example in which a diode is used as an OR circuit, but in order to effectively form an OR circuit using a part of a microcomputer (low power consumption such as C-MOS) It goes without saying that the structure may be formed by a shaped element.

The signal processing process in the above-mentioned microcomputer 110 will be explained in detail along the main flowchart of FIG.

When the microcomputer 110 is activated and becomes operational, the program starts, initializes the system (i.e., sets I/O ports, sets flags, resets, etc.), and enters the main processing flow for overcurrent detection. . Next, the A/D conversion circuit 100 is controlled, and each waveform conversion circuit 91, 9
Converts the effective value or average maximum value signal of the current corresponding to each phase outputted from 2 and 93 into a digital signal, and converts the signal into a digital signal.
115 (A/D conversion processing). Next, regarding the input signal data written to the RAM 115 as described above, an operation is performed to determine whether or not the value is an overcurrent value. As a result, if there is no overcurrent, the process exits from the heat storage routine shown in FIG. 9 and returns to the A/D conversion process described above. Next, if there is an overcurrent, the heat storage flag H is first set, and a register in the CPU or RAM 115 is used to execute a time measurement operation for a time limit according to the level of the input signal at a predetermined time interval. The number of heat storage bits is added. The predetermined number of heat storage bits is selected to realize a time-limited operation along the characteristic curve shown in FIG. Next, an operation is performed to determine whether the number of bits added as described above has reached a value corresponding to a predetermined time period. As a result, if the number of bits added has not reached the value corresponding to the predetermined time limit, the process deviates from the main flow in FIG. 9 and returns to the A/D conversion process described above. Next, when the above-mentioned added bit number reaches a value corresponding to a predetermined time period, the thyristor 1 is input via the I/O port 116.
20 to drive the output device 80.

Next, a time limit reset method (cooling routine) will be explained. As mentioned above, if the maximum value of the A/D converted data falls below a predetermined level when the heat storage flag H is set and the time-limited timing operation is in progress, it is determined whether there is an overcurrent or not. The CPU 10 departs from the determination routine and performs an operation to determine whether or not the heat storage flag H indicating the state at the stage immediately before the relevant stage is set. As a result, if the heat storage flag H is not set, the process returns to the A/D conversion process. Next, if the heat storage flag H is set, a predetermined number of heat radiation bits is subtracted every predetermined unit time from the number of bits added and counted in the heat storage routine as described above. If the bit count value becomes 0 as a result of this subtraction, the heat storage flag H is reset and the process returns to the A/D conversion process. Further, when the bit count value is not completely reset, the heat storage flag H is not reset and the process returns to the A/D conversion process. As described above, optimum thermal properties are obtained.
Note that it goes without saying that the addition and subtraction of heat storage and heat radiation can be performed in the opposite manner to the above to achieve the same function.

Microcomputer 11 in the above embodiment
If the function of 0 is to be realized by an analog circuit, it is theoretically possible to achieve this by, for example, configuring a normal integrating circuit to control the charging/discharging time constant.

In this embodiment, as understood from FIG.
In a region where the fault current of the electric circuit is relatively small, a detection operation is performed based on the effective value or average value of the current of each phase and in accordance with the operating characteristics over a relatively long period of time, so that the electric circuit and load can be optimally protected. On the other hand, in areas where the fault current is relatively large, a faster detection operation is performed in accordance with the operating characteristics in a relatively short period of time, taking into account the fusing characteristics of fuses installed above the electrical circuit, and appropriate protection of the electrical circuit is carried out. It can be done. Furthermore,
When a large current that rapidly increases, such as a short circuit current, flows, it is possible to react instantly and reliably.

In the above-described embodiment, a current transformer is used as the current sensor means, but instead of this, a Hall element, a magnetoresistive element, or a combination of these and an amplifier may be used. Further, as a means for obtaining the absolute value of the detected current, a known means using an operational amplifier can be applied. It is also possible to arbitrarily adopt a configuration in which the output signals of the first time limit generating means and the second time limit generating means described above are used separately to determine the cause of the operation.

[Effects of the Invention] In summary, in the device of the present invention, for relatively small fault currents flowing during overload, etc., the current flow is determined based on the maximum value of the effective value or average value of the current flowing in each phase. Even when a distorted fault current is flowing in only one of the phases, an appropriate and accurate detection operation is performed taking into account the excessive amount of heat accumulated in the line or load due to overcurrent. On the other hand, for large overcurrents such as short-circuit currents that require emergency shutoff, the maximum value is directly detected without going through a circuit with a long time constant such as waveform processing, and based on this detected value (waveform processing, etc.) Detection operations for circuit breakage, etc. can be performed promptly without causing any delay time due to this.

[Brief explanation of drawings]

1 and 2 are block diagrams showing conventional static overcurrent detection devices, FIGS. 3 and 4 are signal waveform diagrams for explaining the operation of the static overcurrent detection device, and FIG. 5 is a block diagram showing a conventional static overcurrent detection device. A characteristic diagram showing the heat resistance characteristics of the electric circuit and the inverse time characteristics of the static overcurrent detection device,
FIG. 6 is a block diagram showing a static overcurrent detection device as an embodiment of the present invention, FIG. 7 is a block diagram showing the configuration of a microcomputer applied to the static overcurrent detection device of FIG. 6, and FIG. Figure 8 is a characteristic diagram showing the heat resistance characteristics of the electric circuit and load as well as the detection characteristics of the static overcurrent detection device of the present invention, and Figure 9 is a flowchart of the basic operation of the microcomputer in the static overcurrent detection device of the present invention. It is. 10... AC line, 21, 22, 23... Current transformer, 31, 32, 33... Full wave rectifier circuit, 40,
41, 42, 43... Burden circuit, 50... Level discrimination circuit, 60... Time limit generation circuit, 70... Output circuit, 80... Output device, 91, 92, 93...
Waveform conversion circuit, 100...analog multiplexer/A/D conversion circuit, 110...microcomputer, 120...thyristor, 130...OR
Circuit, 140... Zener diode, 150...
...Time limit generation circuit, 160...OR circuit.

Claims (1)

[Scope of Claims] 1. Means provided corresponding to each phase of a multi-phase AC circuit and outputting a rectified output for each phase; (a) means for effective or averaging the rectified output for each phase; , a first output signal corresponding to the effective value or average value of the current for each phase, and (a) performing a voltage OR operation of each of the rectified outputs to correspond to the maximum value of the current for each phase. But the voltage
a second output signal that is an OR output; current sensor means for outputting a second output signal; first maximum value detection means for detecting a maximum level of the first output signal of the current sensor means; and the first maximum value. a first level generation means for determining the output level of the detection means; a first time generation means for performing a predetermined time limit operation based on the output signal of the first level determination means; an output of the first time generation means; a first output means that operates based on the signal and emits a signal for protection of the electric circuit; a second level determination means that determines the level of the second output signal of the current sensor means; A second time limit generation means that performs an instantaneous operation based on an output signal; and a second output means that operates based on an output signal of the second time limit generation means and promptly issues a signal for protecting the electric circuit. Static overcurrent detection device. 2 The first maximum value detection means is a diode OR
A static overcurrent detection device according to claim 1, which is constituted by a circuit. 3. At least one of the first and second time limit generation means includes a reset means, and the reset means performs a predetermined heat dissipation operation when the input signal to the corresponding one of the time limit generation means becomes below a predetermined level. The static overcurrent detection device according to claim 1, wherein the static overcurrent detection device is configured to execute a reset operation by determining whether or not heat dissipation is completed based on the characteristics. 4. The static overcurrent detection device according to claim 1, wherein at least the first level determining means and the first time limit generating means are constituted by a microcomputer. 5. The second level determining means and the second time limit generating means are configured and combined without the signal processing of a microcomputer, and the output of the second time limit generating means is directly connected to the output means. A static overcurrent detection device according to claim 4.