JPH0364959B2 - - Google Patents

Description

[Detailed description of the invention]

[Object of the Invention] (Industrial Application Field) The present invention relates to an address selection circuit suitable for selecting addresses of semiconductor memories using insulated gate field effect transistors (including MOS transistors). (Prior Art) Conventionally, as an address selection circuit for a semiconductor memory, a first decoder circuit, a second decoder circuit, and a buffer circuit connected to these first and second decoder circuits are provided to facilitate miniaturization of the device. The measurement technique is known. For example, the international conference "IEEE International Solid-State Circuits" held on February 10, 1977
Conference” proceedings “DIGEST OF
The circuit diagram published on page 13 of ``TECHNICAL PAPERS'' is shown in Figure 1. This address selection circuit includes a first decoder circuit 1 to which a 5-bit address signal 3 is input;
It consists of a second decoder circuit to which a bit address signal 4 is input, and a buffer circuit connected to these first and second decoder circuits. As is clear from FIG. 1, the buffer circuit is composed of transistors T5, T6, and T7, including the buffer source follower transistor T5. The address selection here is transistor T5
The output of the first decoder circuit (main decoder; T1 to T4, T8) is input to the gate of , the ROW ENABLE signal is input to the drain of transistor T5, and the gate of transistor T7 is input to
This is performed using the ROW TRAP signal and the output of the second decoder circuit (sub-decoder circuit: 10F4SELETION) which is input to the drain of the transistor T7. (Problems to be Solved by the Invention) However, in the conventional address selection circuit shown in FIG. Since it is necessary to generate the signal, a problem arises in that the signal generating circuit becomes complicated and large. Also, ROW ENABLE signal and ROW TRAP
Since the signal is ultimately used to cause the operation of the address selection circuit and buffer circuit,
After the outputs of the first decoder circuit and the second decoder circuit change (that is, "1"/"0" at the gate of transistor T5 is determined, and "1"/"0" at the gate of transistor T6 is determined) (after determining the value), it is necessary to input it to the buffer circuit. Therefore, a problem arises in that it takes a very long time from when the address signal is changed until the buffer circuit actually operates. [Structure of the Invention] (Means for Solving the Problems) The address selection circuit of the present invention includes at least first and second decoder circuits and a buffer circuit connected to these, and has address inputs A ₁ - A _o
(where n is a natural number), i (i is a natural number and i<n) selects the output logic level of the first decoder circuit, and selects the output logic level of the second decoder circuit using n−i, The signal that ultimately controls the selection operation of the buffer circuit is the output signal of the first and second decoder circuits whose output changes slower. Further, with the above circuit configuration, the output terminal of the buffer circuit is connected to the first or second voltage supply terminal depending on whether the address is selected or not selected. (Function) In the address selection circuit of the present invention, the selection operation of the buffer circuit is started by the output of the slower one of the first and second decoder circuits, and the selection operation of the buffer circuit is started depending on whether the address is in the selected state or in the non-selected state. , the output terminal of the output of the buffer circuit is connected to the first or second voltage supply terminal. (Example) An example of the present invention will be described below with reference to FIG. In the figure, 21 is a first decoder circuit, 22 is a second decoder circuit, and 23 is a buffer circuit.
In the decoder 21, the D-type load transistor 24 is
E-type transistors 26 ₁ to 26 _i are connected in parallel between the output terminal 25 and, for example, ground, the gate of the transistor 24 is connected to the output terminal 25, and the transistors 26 ₁ to 26 i are connected between the output terminal 25 and the power supply VC. Address inputs A ₁ to _{A i} are supplied to the gates of 26 _i . In the decoder 22, a D-type load transistor 27 is connected between the output terminal 28 and the power supply VC, E-type transistors 26 _i+1 to 26 _o are connected between the output terminal 28 and, for example, ground, and the gate of the transistor 27 is connected between the output terminal 28 and the power supply VC. It is connected to the output terminal 28 and supplies address inputs A _i+1 to A _o to the gates of the transistors 26 i ₊₁ to 26 _o . In addition, a D-type transistor 29 is connected between the power supply VC and ground.
and an E-type transistor 30, the gate of transistor 29 is connected to inverter output terminal 31, and the gate of transistor 30 is connected to terminal 28. Moreover, in the buffer circuit 23,
An I-type transistor 33 and a D-type transistor 34 are connected in series between the power supply VC and the output terminal 32, and an E-type transistor 35 is connected between the output terminals 31 and 32. Further, an I-type transistor 37 and a D-type transistor 38 are connected in series between the power supply VC and the output terminal 36, and an E-type transistor 39 is connected between the output terminal 36 and the ground. The gates of the transistors 35 and 37 are connected to the output terminal 25, the gate of the transistor 38 is connected to the output terminal 28, and the gate of the transistor 39 is connected to the output terminal 28.
The gate of is connected to the output terminal 32. The output end 36 is connected, for example, to one row line of the cell array. Next, the operation of the circuit shown in FIG. 2 will be explained. In this circuit, the buffer 23 can be selected in four ways as shown below, depending on the selection/non-selection combination of the decoders 21 and 22. (1) When both decoders 21 and 22 are selected: Since both terminals 25 and 28 are "1" and terminal 31 is "0", terminal 32 is "0". Therefore, the output 36 is connected to the power supply via transistors 37 and 38.
When connected to VC, it becomes "1" and becomes selected state. (2) When the decoder 21 is selected and the decoder 22 is not selected: the terminal 25 is "1", the terminal 28 is "0", the terminal 31 is "1", and the transistor 35 is cut off, so the terminal 32 is “1”
Therefore, the output terminal 36 becomes "0" and becomes a non-selected state. (3) When the decoder 21 is not selected and the decoder 22 is selected: the terminal 25 becomes "0", the terminal 28 becomes "1", and the terminal 31 becomes "0", and the transistor 35 is cut off, so the terminal 32 becomes "0". 1”,
Therefore, the output terminal 36 becomes "0" and becomes a non-selected state. (4) When decoders 21 and 22 are both unselected: Both terminals 25 and 28 are “0” and terminal 31 is “1”
Therefore, the terminal 32 is "1", the transistor 37,
38 is turned off, the output terminal 36 becomes "0" and becomes a non-selected state. The above operations can be summarized as shown in the table below.

[Table] However, during power down (when the chip is not selected and the power is minimized), all address inputs A ₁ to _{A o} (including positive signals and inverted signals) are set to “0”,
When the signal CL is set to "0", the terminals 25 and 28 are both "1", the terminal 31 is "0", the terminal 32 is "0", and therefore the output terminal 36 is "1", and this selection circuit Current consumption is only the leakage amount from the I-type transistor 33 and the current flowing through the D-type transistor 29. If it is desired to power down the transistor 29 as well, an I-type transistor such as the transistor 33 may be inserted between the drain of the transistor 29 and the power supply VC. In Figure 3, the number of addresses in Figure 2 is n = 6 and i = 4.
This is a specific example of the case. In this case, the number of first decoders 21 is 2 ⁴ = 16, the number of second decoders 22 is 2 ² = 4, and the number of buffer circuits 23 and their output terminals (row lines) is 2 ⁶ = 64. , in Figure 3, the first
One decoder 21 is shown. Here, a plurality of decoders 22 and buffers 23 are used, but since they have corresponding configurations, the same reference numerals will be used for corresponding parts, only the attachments will be changed as appropriate, and redundant explanation will be omitted. What is different from the case in FIG. 2 is that the transistors 34 ₁ to 34 ₄ of the buffers 23 ₁ to 23 ₄
The drains of all transistors 33 are commonly connected to the source of the transistor 33, but this is more convenient in terms of layout and has exactly the same meaning. Further, an example of an operating waveform diagram in this circuit is shown in FIG. For this circuit, address input A ₁ , ₁ ~
Buffers 23 ₁ , 23 2 , . . . are selected by selecting signals A _i , _i and A _i+1 , _{i+ 1} to _{A o} , _o . Here, if we consider the case where the buffer circuit 23 is selected, as is clear from FIG. 3, the decoder 21
Since the decoder 22 is directly controlled by address input, the change in output is determined by the timing of address input. Actually, since a timing shift occurs in the address input, a timing difference occurs between the outputs of the decoder 21 and the decoder 22. Therefore, the buffer circuit 23 directly controlled by this decoder 21 and decoder 22
The speed at which is selected is determined by the output of decoder 21 or decoder 22, whichever is slower. Generally, in a fine, high-density memory, a large amount of power is consumed in the decoder section, and pattern layout is difficult. The number of first decoders is 16, which is 1/4 of the number.
In addition to being able to reduce power, the reduction in the number of elements also improves pattern layout. Furthermore, since the second decoders 22 ₁ to 22 ₄ can be appropriately laid out in the gaps around the periphery of the cell array, the decoder block can be formed small, which is useful for reducing the chip size. In this embodiment, the number of second decoders is 4.
However, this number is determined based on power and layout considerations, and is not particularly limited to the above number. FIG. 5 shows another embodiment of the present invention, which includes:
This figure shows that even if the positive output and the inverted output of the second decoder 22 are obtained by separate NOR circuits, the meaning is exactly the same. FIG. 6 shows yet another embodiment of the present invention, in which the output terminal (row line)
This is an example where 36 is "0". That is, an I-type transistor 51 whose gate input is the signal CL is inserted between the drain of the load transistor 24' of the first decoder 21' and the power supply VC, and the buffer 2
The drain of the load transistor 34' of the inverter 3' is directly connected to the power supply VC. The read operation of this circuit is exactly the same as that shown in FIG. When powering down, all addresses A ₁ to A _i are set to “1”, all addresses A _i+1 to _{A o} are set to “0”,
When the signal CL is set to "0", the terminal 25 becomes "0", the terminals 32 and 28 become "1", and the output terminal 36 becomes "0". However, in this case, the speed is slightly slower than in the case of FIG. Note that the present invention is not limited to the above-described embodiments, and for example, the buffer circuit selected by the first and second decoders may be selected by two or more decoders. In addition, in the embodiment, the side using address inputs A ₁ to _{A i} is the first decoder,
The side using A _i+1 to _{A o} was used as the second decoder, but
The relationship may be the opposite. Also, when selecting an address
Although all 2 ⁿ addresses are selected from A ₁ to _{A o} , the present invention can be applied even when the number of addresses is not exactly 2 ⁿ (less than 2 ⁿ ). In addition to circuit elements such as load elements D-type transistors,
Various applications are possible, such as being configured with an E-type transistor or an I-type transistor. As described above, according to the present invention, the number of circuits and elements of a decoder can be reduced, so that it is possible to provide an address selection circuit that enables lower power consumption and higher density pattern layout. Furthermore, according to the present invention, if the address signal changes, the change is directly transmitted to the buffer circuit, so once the last address input is determined, the output of the buffer circuit can be determined in a very short time, allowing for high-speed address selection. The action can be achieved.

[Brief explanation of drawings]

Fig. 1 is a conventional address selection circuit diagram, Fig. 2 is a circuit diagram of an embodiment of the present invention, Fig. 3 is a circuit diagram showing a specific example of the same circuit in actual use, and Fig. 4 is a signal waveform diagram showing the operation of the same circuit, FIG.
FIG. 6 is a circuit diagram showing another embodiment of the present invention. 21...First decoder circuit, 22...Second decoder circuit, 23...Buffer circuit, 36...
Address selection circuit output terminal.

Claims (1)

[Claims] 1. In an address selection circuit that selects addresses within 2 ⁿ (n is a natural number) from address inputs A ₁ to A _o , at least a first decoder circuit, a second decoder circuit, and the first and second decoder circuits. a buffer circuit connected to the first,
A second decoder circuit is provided between each first voltage supply terminal and a second voltage supply terminal, and the first decoder circuit outputs a logic level by i (i is a natural number, i<n) address inputs. Select the second
The decoder circuit selects a combination of a plurality of output logics using n−i address inputs, and the signal that ultimately controls the selection operation of the buffer circuit is the first one.
This is the output signal of the decoder circuit and the second decoder circuit whose output changes slowly. In the address selection state, the output terminal of this buffer circuit and the first voltage supply terminal are connected, and in the address non-selection state, the output signal is the output signal of the one whose output changes slowly. An address selection circuit characterized in that an output terminal of this buffer circuit and a second voltage supply terminal are connected.