JPH0522319B2 - - Google Patents

Description

[Detailed description of the invention]

[Object of the Invention] (Industrial Application Field) The present invention relates to an address selection circuit suitable for selecting addresses of semiconductor memories using insulated gate field effect transistors (including MOS transistors). (Prior Art) Conventionally, as an address selection circuit for a semiconductor memory, a first decoder circuit, a second decoder circuit, and a buffer circuit connected to these first and second decoder circuits are provided to facilitate miniaturization of the device. The measurement technique is known. For example, the international conference "IEEE International Solid-State Circuits" held on February 10, 1977
Conference” proceedings “DIGEST
Figure 1 shows the circuit diagram listed in Section 13 of ``OFTECHNICAL PAPERS''. This address selection circuit includes a first decoder circuit 1 to which a 5-bit address signal 3 is input;
It consists of a second decoder circuit to which a bit address signal 4 is input, and a buffer circuit connected to these first and second decoder circuits. (Problem to be Solved by the Invention) However, in such a row selection circuit, when the sub-decoder (1 OF 4 SELECTION) is in a non-selected state, the transistor T6 becomes non-conductive, and the row line (ROW SELECT) is grounded. It will end up in a floating state. In such a floating state, it is very difficult to maintain a constant potential because the row lines are not connected to the power supply (ground) terminal. In particular, when the potential of other wirings provided near the row line changes, the potential of the row line also tends to change due to capacitive coupling, which causes a problem of malfunction when the row line is not selected. In order to solve the above problems, the present invention aims to prevent malfunctions when addresses are not selected. [Structure of the Invention] (Means for Solving the Problems) The address selection circuit of the present invention includes a first decoder circuit to which i address signals are input, and a first decoder circuit to which n−i address signals are input.
a second decoder circuit that inputs address signals; and an address selection circuit when the first decoder circuit is in a non-selected state and when the first decoder circuit is in a selected state and the second decoder circuit is in a non-selected state. The output terminal is equipped with a grounding means for setting the output end to the ground level. (Function) The semiconductor memory device of the present invention is provided with a first decoder circuit to which i addresses are input and a second decoder circuit to which n−i addresses are input, and address inputs A ₁ to A _o In an address selection circuit that selects up to 2 ⁿ addresses, the output terminal of the address selection circuit is reliably brought to the ground potential when an address is not selected. (Example) An example of the present invention will be described below with reference to FIG. In the figure, 21 is a first decoder circuit, 22 is a second decoder circuit, and 23 is a buffer circuit.
Furthermore, the buffer circuit 23 has an address selection circuit output terminal set to a ground level when the first decoder circuit is in a non-selected state and when the first decoder circuit is in a selected state and the second decoder circuit is in a non-selected state. and grounding means. Buffer circuit 23
In this case, an I-type transistor 33 and a D-type transistor 34 are connected in series between the power supply VC and the output terminal 32, and an E-type transistor 3 is connected between the output terminals 31 and 32.
Connect 5. Further, between the power supply VC and the output terminal 36, an I type transistor 37 and a D type transistor 3 are connected.
8 are connected in series, and an E-type transistor 39 is connected between the output terminal 36 and ground. transistor 35,
The gate of transistor 37 is connected to output 25 , the gate of transistor 38 is connected to output 28 , and the gate of transistor 39 is connected to output 32 . The output end 36 is connected, for example, to one row line of the cell array. Next, the operation of the circuit shown in FIG. 2 will be explained. In this circuit, the buffer 23 can be selected in four ways as shown below, depending on the selection/non-selection combination of the decoders 21 and 22. (1) When both decoders 21 and 22 are selected: Since both terminals 25 and 28 are "1" and terminal 31 is "0", terminal 32 is "0". Therefore, the output 36 is connected to the power supply via transistors 37 and 38.
When connected to VC, it becomes "1" and becomes selected state. (2) When the decoder 21 is selected and the decoder 22 is not selected: the terminal 25 is "1", the terminal 28 is "0", the terminal 31 is "1", and the transistor 35 is cut off, so the terminal 32 is “1”
Therefore, the output terminal 36 becomes "0" and becomes a non-selected state. (3) When the decoder 21 is not selected and the decoder 22 is selected: the terminal 25 becomes "0", the terminal 28 becomes "1", and the terminal 31 becomes "0", and the transistor 35 is cut off, so the terminal 32 becomes "0". 1”,
Therefore, the output terminal 36 becomes "0" and becomes a non-selected state. (4) When both decoders 21 and 22 are not selected: both terminals 25 and 28 are “0”, and terminal 31 is “1”
Therefore, the terminal 32 is "1", the transistor 37,
38 is turned off, the output terminal 36 becomes "0" and becomes a non-selected state. The above operations can be summarized as shown in the table below.

[Table] However, when powering down (when the chip is not selected and the power is minimized), all address inputs A ₁ to _{A o} (including positive signals and inverted signals) are set to “0”,
When the signal CL is set to "0", the terminals 25 and 28 are both "1", the terminal 31 is "0", the terminal 32 is "0", and therefore the output terminal 36 is "1", and this selection circuit Current consumption is only the leakage amount from the I-type transistor 33 and the current flowing through the D-type transistor 29. If it is desired to power down the transistor 29 as well, an I-type transistor such as the transistor 33 may be inserted between the drain of the transistor 29 and the power supply VC. In Figure 3, the number of addresses in Figure 2 is n = 6 and i = 4.
This is a specific example of the case. In this case, the number of first decoders 21 is 2 ⁴ = 16, the number of second decoders 22 is 2 ² = 4, and the number of buffer circuits 23 and their output terminals (row lines) is 2 ⁶ = 64. , in Figure 3, the first
One decoder 22 is shown. Here, a plurality of decoders 22 and buffers 23 are used, but since they have corresponding configurations, the same reference numerals will be used for corresponding parts, only the attachments will be changed as appropriate, and redundant explanation will be omitted. The difference in the case of Figure 2 is that
Transistors 34 ₁ to 3 of buffers 23 ₁ to 23 ₄
The drains of all transistors ₄₄ are commonly connected to the source of the transistor 33, but this is more convenient in terms of layout and has exactly the same meaning. Further, an example of an operating waveform diagram in this circuit is shown in FIG. In this circuit, address input A ₁ ,
The buffers 23 ₁ , 23 2 , . . . are selected by selecting the signals A ₁ to _{A i} , _i and A _i+ 1 , _{i+ 1} to _{A o} , _o . Generally, in a fine, high-density memory, a large amount of power is consumed in the decoder section, and pattern layout is difficult. The number of first decoders is 16, which is 1/4 of the number.
In addition to being able to reduce power, the reduction in the number of elements also improves pattern layout. Furthermore, since the second decoders 22 ₁ to 22 ₄ can be appropriately laid out in gaps in the periphery outside the cell array, the decoder block can be formed small, which is useful for reducing the chip size. Note that in this embodiment, the number of second decoders is only four, but this is determined based on power and layout considerations, and is not particularly limited to the above number. FIG. 5 shows another embodiment of the present invention, which includes:
This figure shows that even if the positive output and the inverted output of the second decoder 22 are obtained by separate NOR circuits, the meaning is exactly the same. FIG. 6 shows yet another embodiment of the present invention, in which the output terminal (row line)
This is an example where 36 is "0". That is, an I-type transistor 51 whose gate inputs the signal CL is inserted between the drain of the load transistor 24' of the first decoder 21' and the power supply VC, and the buffer 23'
The drain of the load transistor 34' of the inverter is directly connected to the power supply VC. The read operation of this circuit is exactly the same as that shown in FIG. When powering down, all addresses A ₁ to A _i are set to “1”, all addresses A _i+1 to _{A o} are set to “0”,
When the signal CL is set to "0", the terminal 25 becomes "0", the terminals 32 and 28 become "1", and the output terminal 36 becomes "0". However, in this case, the speed is slightly slower than in the case of FIG. Note that the present invention is not limited to the above-described embodiments; for example, the buffer circuit selected by the first and second decoders may be selected by two or more decoders. In addition, in the embodiment, the side using address inputs A ₁ to _{A i} is the first decoder,
The side using A _i+1 to _{A o} was used as the second decoder, but
The relationship may be the opposite. Also, when selecting an address
Although all ²² addresses are selected from _A1 to _Ao , the present invention can be applied even when the number of addresses is not exactly ²ⁿ (less than ²ⁿ ). In addition, various applications are possible, such as circuit elements such as load elements, which may be composed not only of D-type transistors but also E-type transistors and I-type transistors. [Effects of the Invention] As explained above, according to the present invention, a first decoder circuit that inputs i addresses and a second decoder circuit that inputs n−i addresses are provided, and the address input A In an address selection circuit that selects up to 2 ⁿ addresses from ₁ to A _o , when an address is not selected, malfunctions do not occur due to instability of the potential of the corresponding word line.

[Brief explanation of the drawing]

Fig. 1 is a conventional address selection circuit diagram, Fig. 2 is a circuit diagram of an embodiment of the present invention, Fig. 3 is a circuit diagram showing a specific example of the same circuit in actual use, and Fig. 4 is a signal waveform diagram showing the operation of the same circuit, FIG.
FIG. 6 is a circuit diagram showing another embodiment of the present invention. DESCRIPTION OF SYMBOLS 11...Grounding means, 21...First decoder circuit, 22...Second decoder circuit, 23...Buffer circuit, 36...Address selection circuit output terminal.

Claims (1)

[Claims] 1. An address selection circuit that selects up to 2 ⁿ addresses using address inputs A ₁ to An, which selects a selected state or a non-selected state based on i (i is a natural number and i<n) address inputs. a first decoder circuit that selects one of the states; a second decoder circuit that selects either the selected state or the non-selected state based on n−i address inputs; and a buffer circuit controlled by the output of the second decoder circuit, and the buffer circuit is configured to operate when the first decoder circuit is in a non-selected state and when the first decoder circuit is in a selected state. and an address selection device characterized in that it includes grounding means for connecting an output end of the address selection circuit to a node set to a ground level through substantially one transistor when the second decoder circuit is in a non-selected state. circuit.