JPH0367335B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for forming a pattern with gentle steps.

(b) Background of technology Multilayer integrated circuits include those formed on semiconductor single crystal substrates such as ICs, those formed on magnetic garnet crystal substrates such as magnetic bubble memory elements, and those formed on magnetic garnet crystal substrates such as hybrid ICs. Some are formed on a substrate, and in both cases, a circuit pattern is formed in layers on the substrate.

The present invention relates to a method for forming a lower layer pattern that alleviates the effect of a step difference that occurs when circuit patterns are placed above and below a thin insulating layer.

(c) Prior Art and Problems In most cases, fine patterns formed on substrates are made by photolithography using thin film formation technology and photoetching technology. In addition, insulating layers to insulate multilayered fine patterns are made using vacuum evaporation, CVD (chemical vapor deposition), spin coating, etc., but the insulating layers are thin. A step is formed, and therefore, the pattern formed on the step is likely to be disconnected and change in characteristics.

In the following, a semiconductor IC and a bubble memory chip will be explained as examples.

In the formation of semiconductor ICs, a large number of elements formed on the same substrate are connected to each other by wiring, and the conductor wiring for this purpose is formed in many patterns in the vertical and horizontal directions, and is interconnected through an insulating layer. The upper and lower patterns are connected to each other through contact holes provided in the insulating layer. Here, metals such as gold (Au) and aluminum (Al) and silicides such as M ₀ (molybdenum) and dungsten (W) are used as materials for forming the conductor pattern, and materials for forming the insulating layer include Silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), etc. are used.

Now, _SiO2 -based insulators are most often used to form insulating layers, and CVD, plasma CVD, or
The RF sputtering method is used, and the CVD method uses a gas phase reaction between silane (SiH ₄ ) and nitrogen monoxide (N ₂ O), and the RF sputtering method uses a quartz plate (SiO ₂ ) as a target and injects argon into it. A thin film of SiO ₂ is formed by colliding with ions (Ar ⁺ ).

Figure 1 shows a state in which an SiO ₂ insulating film 3 is provided by the CVD method in order to provide a conductor pattern by crossing over a conductor pattern 2 made of Al that connects semiconductor elements formed on a Si substrate. However, in addition to producing a similar step in the insulating film on the conductor pattern 2, an overhang 4 tends to occur, and if a conductor pattern is formed on this, an incomplete connection is likely to occur at the step or the overhang 4.

FIG. 2 shows an example of a magnetic bubble memory chip, in which a magnetic garnet crystal film 5 is coated with a thickness of approximately 1000 mm.
There is a SiO ₂ insulating film 6 with a thickness of [Å], and a conductor pattern 7 and a pattern 8 are laminated thereon.

That is, a conductor pattern 7 made of Al/Cu alloy is formed to a thickness of approximately 4000 Å to form a gate circuit, and a polyimide resin is coated on this first layer circuit to a thickness of approximately 4000 Å by spin coating. ] to form an insulating layer 9, on which a driving pattern 8 made of permalloy is formed to a thickness of approximately 4000 Å.

Now, the magnetic bubble memory is based on the phenomenon in which a magnetic bubble is attracted to the magnetic pole of the drive pattern 8 that is magnetized by a planar magnetic field, moves to the drive pattern 8 following the rotation of the planar magnetic field, and the signal that flows through the conductor pattern 7. This is a memory that utilizes interaction with an induced magnetic field caused by pulses, but when the drive pattern 8 exists with steps as shown in Fig. 2, if an in-plane magnetic field as shown is applied, the drive pattern In addition to the magnetic pole induced in the end face portion 10 of 8, the magnetic pole is also induced in the stepped portion 11, which causes a reduction in the operating margin and causes malfunction.

As described above, when forming a multilayer integrated circuit, it is necessary to eliminate steps as much as possible because the presence of steps has an adverse effect not only on the manufacturing yield but also on the characteristics. Therefore, when dry etching is used to form a pattern, methods such as taper etching, which is non-directional etching, are used to create a taper in the step part, but in this case, it becomes impossible to form a fine pattern, and it becomes difficult to form a conductive pattern. This has the disadvantage that the effective cross-sectional area is reduced, making it impossible to flow a large current.

(d) Object of the Invention An object of the present invention is to provide a pattern forming method that eliminates the influence of steps by tapering portions where the occurrence of steps is averse when forming a multilayer integrated circuit.

(e) Structure of the Invention The object of the present invention is to use a mask in which a plurality of narrow dummy patterns are provided in parallel in proximity to the pattern position when forming a lower layer pattern having a portion where the level difference needs to be reduced. This can be achieved by performing selective exposure to form a resist pattern and dry etching this.

(f) Embodiments of the Invention In the present invention, when forming a pattern that requires the reduction of steps, a plurality of narrow dummy patterns are provided in advance on the mask used to form the pattern, and the wraparound effect of diffracted light generated at these portions is reduced. It is used.
FIG. 3 is a plan view showing part of a mask pattern used in an embodiment of the present invention.

That is, in the case of this example, mask pattern 1 forming a conductor pattern made of Al/Cu alloy
A narrow dummy mask pattern 14 is provided adjacent to a position 13 where the step difference needs to be alleviated in a part of the mask pattern 2.

Here, in the case of this embodiment, three dummy mask patterns 14 are provided, each pattern width is 1 [μm], and the interval between the conductor pattern 12 and the first dummy pattern 15 is 1 [μm]. 1.5 [μm] and 2 [μm] in order. Now,
Conventional exposure and development are performed using such a mask.

FIG. 4 shows the cross-sectional shape after development, showing the Al/Cu alloy thin film 1 formed on the SiO ₂ insulating film 6.
There is a positive type photoresist 17 on top of the photoresist 17, which is exposed to light using the mask shown in FIG. There is a detour,
Therefore, the photoresist 17 below the dummy mask pattern position is also exposed, and undulations 18 as shown in the figure are formed.

Next, when dry etching such as ion milling is applied, the etching rate is different between the photoresist 17 and the Al/Cu alloy. with taper 19
After forming an Al/Cu alloy pattern, the remaining photoresist 17 can be removed with a solvent.

The present invention combines the diffraction or wraparound effect of light in a grating with dry etching, and in addition to the ion milling used in the examples, it also uses not only the pattern forming material but also the resist film during etching, such as gas plasma etching. In the etching process where etching is performed at the same time,
This method is effective.

Note that the pattern position where the level difference should be alleviated does not have to be a straight line as illustrated in Figure 3, but may be placed parallel to the main pattern, and the type of resist used can be either positive or negative. Similarly, a pattern with a tapered cross section can be created using a material.

(g) Effects of the Invention According to the embodiments of the present invention, steps can be made tapered at pattern intersections of integrated circuits such as semiconductor ICs and magnetic bubble memories, and problems caused by disconnections and other steps can be eliminated. .

[Brief explanation of drawings]

Figure 1 shows the cross-sectional structure when an insulating layer is formed using the CVD method in the manufacture of semiconductor ICs, Figure 2 is a cross-sectional view showing the relationship between the conductor pattern and the drive pattern of a magnetic bubble memory chip, and Figure 3 is the main part of the book. A part of the mask pattern according to the invention, FIG. 4 is a sectional view of the resist film after development, and FIG. 5 is a sectional view after dry etching. In the figure, 12 is a mask pattern, 13 is a position where step reduction is required, 14 is a dummy mask pattern, 17 is photoresist, and 19 is a taper.

Claims (1)

[Claims] 1. Coating a resist on a substrate to be processed with a thin film, selectively exposing the resist to create a resist pattern, dry etching the thin film using the resist pattern as a mask, and forming a pattern made of the thin film. A plurality of dummy patterns are provided adjacent to a mask pattern that selectively exposes the resist to form a gradual step difference, and have the same pattern width and a pattern interval that increases as the distance from the mask pattern increases, and exposes the resist to light. A pattern forming method characterized by performing exposure with a small amount of light in the dummy pattern portion due to a wraparound effect due to light diffraction in the dummy pattern portion.