JPH0367376B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a clock circuit for a variable delay circuit of a confidential communication device for maintaining the privacy of telephone calls in wired or wireless communications. .

(b) Prior Art In wired or wireless communication, there is an inherent problem that if a suitable receiving device is used, the contents of the communication can be intercepted by anyone, and the confidentiality of the communication is impaired.
One way to solve this problem is to scramble the audio signal and send it out so that even if it is received by a third party, the contents cannot be known.The circuit that plays back this processed signal (descrambler) A so-called scrambling technique has been used in the past, which allows only a recipient with a processing circuit (processing circuit) to restore the audio signal. Conventional secret communication methods include, for example, the Journal of the Institute of Electronics and Communication Engineers (August 1982) "Secret Communication Technology" (P832-P834) and the Technical Report of the Institute of Electronics and Communication Engineers.
Various methods are introduced in CS80-149 (November 1980) "About the secret method".

Since audio information is composed of spectra and their temporal changes, the intelligibility of the audio can be reduced by scrambling processing that changes the spectral configuration. From this point of view, scrambling methods that have been put to practical use include the spectrum inversion method and the frequency division permutation method.

For example, Japanese Patent Publication No. 58-8621 (H04K1/04) ``Secret conversation method with frequency correction function'' and Japanese Patent Publication No. 58-148541
(H04K1/04) "Secret speech circuit" is related to the spectrum inversion secret speech method, and also
06) After dividing the “secret device” into a predetermined spectrum,
Regarding methods of signal processing, the Institute of Electronics and Communication Engineers Technical Report CS-80-149 describes methods for improving each method, regarding methods of converting audio signals into digital signals and then performing frequency axis conversion processing using FFT processing. This is what I am proposing. However, the spectral inversion method cannot provide a sufficient number of combinations (number of keys) for secret stories. The latter two methods have a large number of keys, but require a large number of filters and an FFT processing circuit, resulting in a large circuit size and high cost.
There were also problems such as high power consumption.

From these points of view, the applicant has previously proposed a scrambling method that has a large number of keys, has excellent confidential communication performance, and has a simple circuit configuration.
No. ``Confidential communication method and device'' (September 1982)
Patent Application No. 184916 ``Clock circuit for confidential communication system'' (filed on October 20, 1982)
1970-19702 "Secret Communication Device" (October 1988)
(filed on the 20th of May). This uses a variable delay circuit to periodically change the clock frequency that controls the delay time, repeatedly compresses and expands the time axis, scrambles the audio signal, and sends it out.
This method performs descrambling processing on the receiving side.

In this method, in order to periodically change the clock frequency of the variable delay circuit, a first variable frequency divider circuit is provided that variably divides the master clock (hereinafter referred to as MCI for the purpose of explanation below). The frequency dividing number of the variable frequency dividing circuit is determined according to the output state of the frequency dividing circuit that divides the output of the variable frequency dividing circuit. (The clock for the variable delay circuit is obtained from the first variable frequency divider circuit.) Furthermore, in order to change the key code, it is necessary to change the master clock (MC1). Although it is possible to construct the same clock circuit as previously used and change the crystal oscillator of the clock circuit, this method is inconvenient because the user cannot easily change the key code.
Therefore, a second master clock (hereinafter referred to as (MC2) to distinguish it from the master clock (MC1)), which has a higher oscillation frequency than the master clock (MC1), is connected to a second variable frequency divider circuit, and the frequency division number is set using a key code. It is sufficient to divide the frequency and use the first master clock (MC1) as the first variable delay circuit. However, with this configuration, the master clock becomes high (8 to 16 MHz), and when such a clock circuit is integrated into an IC, there are problems in terms of power consumption and IC manufacturing technology.

(c) Problems to be Solved by the Invention As mentioned above, the present invention has the function of setting the frequency division number of the second variable delay circuit using a key code, but also has the ability to lower the master clock frequency (MC2). This provides a clock circuit that can

(d) Means for Solving the Problems The present invention provides a clock circuit that combines the functions of the first variable frequency divider circuit and the second variable frequency divider circuit, and uses a relatively low speed master clock to read key codes. A clock circuit of a variable delay circuit that can vary the delay time is constructed.

(e) Effects and Examples Next, the circuit of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram illustrating the principle of the circuit of the present invention, where A indicates the transmitting side and B indicates the receiving side. First, in Figure 1A, 1 is an audio input terminal, 2 is an audio input terminal, and 2 is an audio input terminal.
It is LPF. Reference numeral 3 denotes a delay circuit (memory circuit) having N delay stages, which samples and stores the audio according to the clock of the clock frequency control circuit (CP1) 4, and at the same time samples and stores the audio samples sampled and stored before the N sample time. This is a variable delay circuit that constantly stores N sampling values and sequentially outputs the values. After passing through the LPF 5, the output of the delay circuit is added to the output of the synchronization signal circuit 6 by a synthesis circuit 7, and then sent to a wired or wireless transmission system 9 via a transmission circuit 8 that performs modulation and amplification for transmission. will be sent to.

On the receiving side in FIG.
After demodulating with 0, the received audio is sampled and stored via the LPF 11 according to the clock of the clock frequency control circuit (CP2) 4', and at the same time
The sampling values sampled and stored before the sampling time are stored in an N sample storage circuit 3' which sequentially outputs them via the LPF 12. Synchronization between the sending side and the receiving side is achieved by separating the synchronous signal sent from the synchronous signal generation circuit 6 on the sending side from the received signal by the synchronous separation circuit of the synchronous signal circuit 6' on the receiving side, and using this separated synchronous signal. This is done by completely synchronizing the receiver's clock with that of the transmitter.

Next, basic circuits on the transmitting side and receiving side of the present invention are shown in FIGS. 2 and 3, respectively. This basic configuration is substantially the same on both the transmitting and receiving sides. That is, a delay circuit 3 such as a BBD that inputs and outputs audio signals;
3', clock frequency control circuits 4, 4' for controlling the frequencies of clock pulses 13, 13', and synchronizing signal circuits 6, 6'. More specifically, the clock frequency control circuits 4, 4' are as follows:
master clock frequency oscillation circuits 15, 15';
variable frequency divider circuits 16, 16' that frequency divide the output;
Counter circuits 17, 17' that count clock pulses to delay circuits 3, 3' such as BBD, and logic circuits 18, 18 that control the frequency division number of the frequency divider circuits 16, 16' based on the output signals of the counters. ′. Also, the synchronization signal circuit 6 on the transmitting side in FIG.
consists of a gate signal generation circuit 19, a carrier wave generation circuit 20 for synchronization, and a gate control circuit 21,
The synchronization signal circuit 6' on the reception side shown in FIG. 3 consists of a synchronization separation circuit 21, a synchronization trigger generation circuit 22, and a preset value control circuit 23.

The basic principle of the confidential communication circuit of the present invention, for example, using a sine wave signal as an input signal, is a process of periodically shifting the frequency of the input sine wave signal up and down as shown in FIG. This changes the spectral structure of the audio signal and reduces its intelligibility. More specifically, in FIG. 2, by changing the frequency division number of the variable frequency divider circuit 16 in the clock frequency control circuit 4,
By changing the clock frequency to BBD3 and making the frequency of the clock pulse when the audio signal is input to the BBD different from the clock frequency when outputting after the delay, the frequency of the output audio signal can be restored to the original frequency. This method attempts to scramble the audio by changing the oscilloscope.

On the other hand, on the receiving side (Fig. 3), in a circuit having approximately the same configuration as the transmitting side (Fig. 2), the receiving side is
By changing the clock frequency to BBD 3', the frequency of the received scrambled audio is converted again to exactly the original frequency, thereby performing a restoring operation.

Next, the above-mentioned operation will be explained in more detail with reference to FIGS. 2 and 3.

The audio signal is sent to the delay circuits 3, 3' with the clock 13,
13', and is further transferred to the next stage of the memory cell in the delay circuit like a bucket brigade, and is output after inputting clocks corresponding to the number of delay stages. Here, if the clock frequency when the audio signal is input is fa, and the clock frequency when the delayed signal is output is fb, then the audio signal at the time of output is converted to fb/fa times the frequency and sent out. Therefore, scrambling can be performed by changing the clock frequency.

Here, if the clock frequency when the audio signal is input to the transmission delay circuit 3 is _f1 , and the clock frequency when the signal is output after delay is _f2 , then the clock frequency when input to the receiving side delay circuit is _f2 . Furthermore, if the clock frequency when outputting from the receiving side after delay is f ₃ , then in order to restore and output the original audio signal from the receiving side delay circuit, f ₂ /f ₁ ×f ₃ /f ₂ In other words, the clock frequency may be changed by waiting a period equal to the sum of the delay times on the transmitting side and the receiving side so that f ₃ =f ₁ . The clock frequency control circuits 4, 4' in FIGS. 2 and 3
is a circuit that controls audio frequency conversion as described above.

Next, the clock frequency control circuits 4, 4' of the present invention
The specific configuration of is shown in FIG. In Figure 5,
15, 15' are master clock generation circuits;
Generate a constant frequency clock source (preferably around 500KHz to 1MHz) using a crystal oscillator or the like.
24 is a 5-bit preset counter (first counter), a switch 25 is connected to the preset input, the master clock 15 is connected to the T input, and the output of a D flip-flop 26, which will be described later, is connected to the preset input.
Connect to LD input. The outputs of each stage (Q _A to Q _E ) of the preset counter 24 are supplied to the first logic circuit 27 . The preset counter 24
Each time a pulse is input to the LD input, it is initialized to the value set by the switch 25, and advances in accordance with the master clock.

The first logic circuit 27 is a frequency division output (Q _H , Q _I , Q _J ) of a predetermined stage of a second frequency divider circuit (counter) 29 which will be described later.
and each frequency-divided output of the preset counter 24, and when the preset counter 24 reaches the value set by the output of the second counter 29, it outputs a logic level "1". D flip-flop 26
latches the output of the first logic circuit 27 to the Q output at the falling edge of the master clock.
Therefore, the master clock is logically inverted by the inverter 30 and inputted to the T input terminal. The Q output of the D flip-flop 26 is the output of the preset counter 24.
It is supplied to the divide-by-2 circuit 28 together with the LD input terminal.
The divide-by-2 circuit 28 divides the Q output of the D flip-flop 26 by 2, and simultaneously sends the clock 13 or 13' to the variable delay circuit 3 or 3'.
A clock is sent to the clock input terminal T of 9. Second
Counter 29 divides the clock entering the T input.

With this configuration, the clock frequency applied to the variable delay circuits 3 and 3' can be controlled by the switch 25 and the outputs (Q _H , Q _I , Q _J ) of the second frequency division counter 29. Figure 6 shows this time chart, and Figure 7 shows this time chart.
The figure and FIG. 8 show an embodiment of the first logic circuit 27.

In FIG. 6, CK is the master clock output from the master clock circuit 15 in FIG. 5, Q _A ,
Q _B , Q _C , Q _D , and Q _E are the divided outputs of the preset counter 24. The setting status of switch 25 is 2 ³ 8
As shown in _the figure, the value at which the preset counter 24 is initialized (initialized when the load pulse LP is input to the LD input) is set to K ₀ to K ₇ . It can be set to a value of ₇ . In addition, the divided output of the second counter 29 (Q _H , Q _I , Q _J )
When the value of is (0, 0, 0), X ₀ , (1, 0, 0)
X ₁ when (0, 1, 0), X ₂ when (1, 1,
0), X ₃ , (0, 0, 1), X ₄ ,...
(1, 1, 1), X ₀ to X ₇ are made to correspond.

This correspondence can be achieved by configuring the first logic circuit as shown in FIGS. 7 and 8. In Figure 7, 31,3
2 and 33 are exclusive OR inverting gates, respectively, which output logic "1" when the logic levels of the two inputs are "1" and "1" or "0" and "0". Output. 34 is an AND gate. Therefore, Q _E is “1” and Q _A and Q _H ,
It outputs "1" when Q _B and Q _I and Q _C and Q _J are at the same logic level. That is, Q _H , Q _I , Q _J are (0,
An LC output can be generated at the position shown in FIG. 6, such as X ₀ when the output is 0, 0) and X ₁ when the output is (1, 0, 0). The example (A-1) is for X ₀ and the example (A-3) is for X ₁ . Figure 8 is similar to Figure 7.
OR gate 41 instead of Exclusive Nor gate,
42 and 43, and functions in the same manner as in FIG.

Now, (Q _H , Q _I , Q _J ) are (0, 0, 0) and (A
When the output of the first logic gate 27 becomes "1" at the position _X0 as shown in (A-1), the D flip-flop latches it at the inverted phase (ie, falling edge) of the master clock (A-2). Therefore, the flip-flop output (load pulse LP) is the 6th
The logic becomes "1" at the position shown in the crosshatch section (A-2) in the figure. When the switch 25 is set to K ₀ , the value of the preset counter 24 is initialized to 0 at the center of this crosshatch.
This part becomes the logic "1" part on the left. In this case, the LP interval is the interval at which 17 master clocks CK are counted. (Q _H , Q _I , Q _J ) is (1, 0,
0) and X ₁ is set, (A
-3), L _C and L _P occur at the positions shown in (A-4). The case where the switch 25 is set to K ₀ is shown by a solid line, and the case where the switch 25 is set to K ₁ is shown by a broken line. K ₀ , X ₁
When is set, L _P is generated periodically at an interval that counts 18 master clocks.

Table 1 shows the period of LP in units of master clock CK. When the switch 25 sets _K0 , the LP changes sequentially from a period of counting 17 master clocks CK to a period of counting 24, depending on the states of _QH , _QI , and _QJ . As shown in Table 1, depending on the setting state of the switch 25, the periodic series in which the LP transitions can be selected.

In FIG. 5, a circuit has been described in which the load pulse is divided by the second frequency dividing circuit 29, but instead of the load pulse, each stage of the preset counter 24, for example (Q _E ) (Q _D ) (Q _C )... can be frequency-divided by the second frequency dividing circuit 29 to achieve the same function.

(F) Effects of the Invention As described above, the circuit of the present invention is configured so that the preset value of the preset counter can be set by a switch, and the sequence in which the frequency of the load pulse (LP) changes can be selected. Therefore, by dividing this load pulse (LP) (to make the duty 50),
If the clock of the variable delay circuit is supplied, there is no need to make the master clock relatively high, and it is possible to provide a confidential circuit that can change the key code with a simple operation such as a switch. This has the effect of reducing the power consumption of such a confidential circuit and making it easier to incorporate it into an IC.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing the principle of the present invention.
FIG. 2 is a block diagram of the circuit on the transmitting side of the confidential communication device of the present invention, FIG. 3 is a block diagram of the circuit on the receiving side of the same device, FIG. 4 is a characteristic diagram of the scramble signal waveform processed by the device of the present invention, and FIG. FIG. 6 is a block diagram showing an embodiment of the clock frequency control circuit, FIG. 6 is a time chart of the clock frequency control circuit, and FIGS. 7 and 8 are embodiments of the first logic circuit. Explanation of main drawing numbers, 1...input terminal, 3, 3'...
...variable delay circuit, 4, 4'... clock frequency control circuit, 6, 6'... synchronization signal circuit, 7... synthesis circuit, 9... transmission system, 13... clock pulse,
14... Output terminal, 15, 15'... Master clock frequency oscillation circuit, 16, 16'... Variable frequency dividing circuit, 17, 17'... Counter circuit, 18,
18'...Logic circuit, 19...Gate signal generation circuit, 20...Synchronization carrier generation circuit, 21...Synchronization separation circuit, 22...Synchronization trigger generation circuit, 2
3... Preset value control circuit, 24... Preset counter, 25... Switch, 26... D flip-flop, 27... First logic circuit, 28...
2 frequency divider circuit, 29...2nd frequency divider circuit, 31,3
2, 33...Exclusive Nor gate, 34...
AND gate, 41, 42, 43...OR gate.

【table】

Claims (1)

[Scope of Claims] 1. A secret communication device comprising a variable delay circuit for sequentially sampling and storing signals according to clock pulses, and outputting the signals, and a clock frequency control circuit for controlling the frequency of the clock pulses, comprising: (a) (b) the output of the first input designating means, a master clock, and a load pulse are input, and each time the load pulse is input, the output of the first input designation means corresponds to the designated state of the first input designation means; (c) a second counter that divides the load pulse or a desired stage output of the first counter; (d) the second counter output; a load pulse generation circuit that receives the output of the first counter and generates the load pulse in relation to the time when the first counter advances to the state set by the output of the second counter; A clock circuit for a variable delay circuit of a secure communication device, characterized in that a sampling clock for the variable delay circuit is obtained from a load pulse, a desired stage output of the first counter, or a frequency-divided output thereof. 2 The load pulse generation circuit performs a logical operation such as an exclusive OR or a logical sum between the desired stage output of the first counter and the corresponding output of the second counter, so that the first counter becomes the output of the second counter. a first logic circuit that outputs a predetermined logic level when the first counter advances to a state set by the first logic circuit; 2. A clock circuit for a variable delay circuit of a secure communication device according to claim 1, wherein the clock circuit comprises a latch circuit in which a latch circuit is latched, and the output of the latch circuit is used as the load pulse.