JPH055209B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a confidential communication device for ensuring confidentiality of telephone calls in wireless communications.

(B) Prior art In normal wireless communication, when Party A and Party B are talking, if third party C receives a signal in the carrier frequency range used for communication between Party A and Party B, Party A and Party B There is a problem in that the confidentiality of calls is lost because the contents of calls between users can be intercepted.

An effective method for guaranteeing this confidentiality is to send a scrambled audio signal and then restore it on the receiving side. According to this method, the contents of the call will not be understood by a third party who does not have a restoration circuit in the receiving unit or who has a different key code because the received audio remains scrambled. Confidentiality can be maintained.

As one type of secret circuit, a circuit element with a built-in balance modulator (balanced modulation type) is generally commercially available. This method uses the audio signal as
For example, after modulating with a 5KHz carrier wave, only the lower sideband is extracted by filter processing and sent out. In this case, the frequency of the audio signal is inverted with respect to the original signal. That is, the audio frequency is f
Then, f'=5-f (KHz). To restore, simply perform the reverse operation, and the audio frequency will be inverted again, so it will return to its original state. In this case, even if the carrier frequency of the balance modulator is slightly changed, the pitch of the reproduced sound is only slightly shifted from the original sound, and there is no problem with intelligibility. This means that in this method, only one key code for secret information can be obtained. Therefore, it has the disadvantage that the effect of maintaining confidentiality cannot be exhibited for those equipped with the same type of scrambling circuit.

(c) Purpose It is an object of the present invention to provide a secure communication device that is provided with a large number of key codes in response to the requirement for guaranteeing confidentiality.

(d) Configuration In order to achieve the above-mentioned object, the present invention includes the following circuits on the transmitting side and the receiving side, respectively.
That is, the confidential communication device of the present invention is comprised of a variable delay circuit, a frequency dividing circuit, a counter circuit, and a logic circuit.

(E) Embodiment The present invention basically comprises a transmitter that scrambles an audio signal and a receiver that restores the scrambled audio signal.

Next, the apparatus of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram illustrating the principle of the apparatus of the present invention, in which A indicates the transmitting side and B indicates the receiving side. First, in Figure 1A, 1 is an audio input terminal, 2 is an audio input terminal, and 2 is an audio input terminal.
It is LPF. 3 is a delay circuit (memory circuit) having ^2N delay stages, and a clock circuit (CP ₁ ) 4
This is a variable delay circuit that samples and stores the audio signal in accordance with the clock of ^2N , and at the same time constantly stores ^2N sampling values, which sequentially outputs the sampling values sampled and stored before the 2N sampling time. After the output of the delay circuit passes through LPF5,
A transmitter circuit 8 which adds the output of the synchronization signal circuit 6 and an adder circuit 7, and then modulates and amplifies it for transmission.
The signal is then sent to a wired or wireless transmission system 9.

On the receiving side in FIG. 1B, the received signal that has passed through the transmission system 9 is demodulated by a receiving circuit 10 including an amplification and demodulation circuit, and then sent to the clock of a clock circuit (CP ₂ ) 12 via an LPF 11. Therefore, at the same time as the received voice is sampled and stored, it is stored in the ^2N sample variable delay circuit 14 which sequentially outputs the sampled values sampled and stored before the ^2N sample time through the LPF 13. Synchronization between the transmitting side and the receiving side is performed by a synchronization separation circuit 15 which separates the synchronizing signal sent from the synchronizing signal generating circuit 6 on the transmitting side from the received signal, thereby completely synchronizing the clock on the receiving side with that on the transmitting side. It will be done.

Next, the basic circuit configuration of the present invention is shown in FIG. This basic configuration is the same on both the transmitting and receiving sides. That is, it is composed of a delay circuit 3 such as a BBD that inputs and outputs audio signals, and a clock frequency control circuit 4 that controls the frequency of the clock pulse 21.
The clock frequency control circuit further includes a master clock frequency oscillation circuit 17, a frequency division circuit 18 that divides the output of the master clock frequency oscillation circuit 17, a clock pulse counter circuit 19 that counts clock pulses to a delay circuit 3 such as a BBD, and a clock pulse counter circuit 19 that counts clock pulses to a delay circuit 3 such as a BBD. The frequency dividing circuit 18 is composed of a logic circuit 20 for controlling the frequency dividing number of the frequency dividing circuit 18 based on the output signal of the frequency dividing circuit 18.

The basic operation of the circuit shown in FIG. 2 is as follows. That is, by changing the frequency dividing number of the frequency dividing circuit 18 according to changes in the output signal of the counter 19, the clock frequency 21 to the delay circuit (BBD) 3 is changed, and the clock pulse when the audio signal is input to the BBD is changed. By making the frequency (f ₁ ) of 21 different from the clock frequency (f ₂ ) at the time of outputting the delayed audio signal, the frequency of the output audio signal at the output end of the BBD 3 is set to (f ₂ /f ₁ ) Doubling and changing the frequency of the output audio signal with respect to the original one,
This is to scramble the audio.

On the other hand, on the receiving side B, in a circuit having the same configuration as the sending side A, the received scramble is The structure is such that the restoration operation is performed by converting the audio frequency again so that it returns to the original frequency.

Furthermore, the present invention is configured so that a large number of key codes can be obtained by setting the logic circuit 20 that controls the frequency and frequency division number of the master clock 17.

In the method of the present invention, the cycle of clock frequency change is the time required for the counter 19 to count the clock pulses 21 by the sum of the number of delay stages of the variable delay circuit 3 on the transmitting side A and the number of delay stages of the variable delay circuit 14 on the receiving side B. It needs to have a cycle. In this case, for example, at the clock pulse frequency (f ₁ ), the variable delay circuit 3 on the transmitting side
Since the clock pulse frequency is the same (f ₁ ) when the input audio signal is output from the receiving side variable delay circuit 14 after delay, there is no frequency conversion of the audio signal in the overall transmitting/receiving system, and the audio signal is completely will be restored.

The above restoration operation assumes that the oscillation frequency of the master clock oscillator 17 is the same on both the transmitting and receiving sides and that the frequency changes are synchronized.
Next, the operation will be explained in the case where, for example, the master clock frequency is different between the transmitting side and the receiving side.
In that case, the cycle time of the clock frequency change on the receiving side is different from that on the transmitting side, so the clock frequency when the audio signal is output from the receiving side variable delay circuit 14 after being delayed is the same as the clock frequency on the transmitting side. The signal is
Since the clock frequency is different from that used when inputting to BBD3, the original audio is not restored and is output as scrambled audio. This indicates that the difference in the frequency of the master clock oscillator can be used as a key code for the secret communication system. The present invention is configured so that the number of key codes can be multiplied by setting the master clock frequency.

Now, in the method of the present invention, the reproduced sound quality and scrambling effect during restoration are greatly influenced by the change characteristics of the clock frequency. Therefore, in the configuration shown in FIG. 2, the logical configuration for controlling the frequency division number is an important key point.

Regarding the scrambling effect, it is desirable that the ratio α = fmax / fmin of the maximum frequency (max) and minimum frequency (fmin) in the clock frequency change characteristics is large, and in experiments, a value of 1.5 or more is recommended for practical use. The results show that it is effective.

In addition, since the method of the present invention is a time axis conversion method for audio signals, the required transmission band between the transmitting side and the receiving side is approximately α times the bandwidth on both the high and low frequency sides compared to the case without time axis conversion. A wide width is required. On the other hand, in order to synchronize the change characteristics of the clock frequency between the transmitting side and the receiving side, the transmitting side A sends out a synchronization control signal by superimposing it on a scrambled signal.
A method is used in which the synchronization signal is separated by filter processing on the receiving side B, but in this case, the band that can be used for transmitting the audio signal is subject to restrictions. Since the frequency of the scrambled signal changes between 1/α and α with respect to the original audio signal, if the transmission system band is narrow, audio signal components may be lost in the low and high frequencies. , the playback quality deteriorates during restoration. Experiments have shown that it is necessary to suppress the value of α to 1.8 to 2.0 or less.

In addition, as shown in FIG. 3 as possible values of the clock frequency, the method of alternately repeating two frequencies (fa) and (fb) simplifies the configuration of the logic circuit 20 and ensures perfect synchronization between the transmitting and receiving sides. It is very effective if you can handle it. However, in experiments, some synchronization errors occur due to variations in the characteristics of the synchronization signal detection circuit and phase shifts due to constraints on the frequency characteristics of the transmission system.

In the binary frequency switching method as shown in Figure 3,
When this synchronization shift occurs, the degree of frequency conversion shift is large, resulting in a large deterioration of reproduced sound quality. On the other hand, in the case of a characteristic in which the clock frequency repeatedly rises and falls continuously as shown in FIG. 4, there is little deterioration in sound quality when synchronization occurs. One way to obtain a continuous clock frequency as shown in Figure 4 is to input a triangular wave signal to a voltage controlled oscillator (VCO). Adjustment is troublesome. In this respect, it is effective to change the clock frequency by digitally controlling the frequency division number using a logic circuit configuration. Furthermore, experiments have shown that 16 to 32 stages of the clock frequency to be varied is sufficient for practical use.

The present invention takes the above points into consideration and provides a logic circuit configuration for obtaining effective clock frequency change characteristics, and the specific circuit configuration will be explained in detail below.

FIG. 5 shows a specific example of a logic circuit used in the present invention. In the figure, for convenience of explanation, a case will be described in which the number of delay stages of the variable delay circuits 3 and 14 used on the transmitting side and the receiving side are both ^2N . In this case, the signal component input to the variable delay circuit 3 is output from the variable delay circuit 3 after a time delay corresponding to ^2N clock pulses 21. The control counter 19 used in the example of FIG. 5 is a 2 ^N -ary counter, and the highest counter output (Q ₁ ) outputs "1" and "0" values every 2 ^N clock pulses to the variable delay circuit. Repeat switching to . Here, N is a much larger number than n.

Next, the frequency dividing circuit 18 also basically consists of a frequency dividing counter 18. In the example of FIG. 5, the output (Mn) of the microplexer 22 included in the logic circuit 4 [(S ₁ )(S ₄ )...(Sn) in the drawing, however, (S ₂ )(S ₃ ) is the inverted output of (M ₁ )] and the output of each stage of the frequency division counter 18 (P ₁ ) (P ₂ )...(Pn)
and the OR circuit (23 _-1 ) (23 _-2 )...(23−
n) and OR logic output (R ₁ ) (R ₂ )...
(Rn), and further these outputs (R ₁ ) (R ₂ )...
(Rn) is applied to the AND circuit 24 to obtain an AND logic output, and this output is used to control the frequency division counter 1.
Reset 8. In this case, the multiplexer 22 is selected to output [A] when the output of the highest stage output (Q ₁ ) is "0" and output [B] when it is "1". Moreover, its logical configuration is as follows.

(a) When Q ₁ = 0, S ₁ = Q ₂ , S ₂ = S ₃ = ₂ , Sk =
Qk _-1 , (k≧4) (b) When Q ₁ = 1, S ₁ = ₂ , S ₂ = S ₃ = Q ₂ , Sk =
Qk _-1 , (k≧4) Furthermore, in this case, depending on the type of counter, it is necessary to further insert an inverter circuit to supply a signal to the reset terminal of the counter 18.

FIG. 6 shows a logic diagram when the logical configuration of FIG. 5 is used. As an example, the case where nmax=6 for Pn is shown. In FIG. 6, the frequency division number repeats rising and falling in the range of values from 24 to 39, and a change in clock frequency similar to the characteristic shown in FIG. 4 is obtained. α=fmax/fmin is approximately 1.63 times, and a fairly effective scrambling effect can be obtained. There are also 16 possible frequencies, so even if a slight synchronization error occurs, there is little deterioration in playback quality during restoration. Although the case where nmax=6 has been described above, it goes without saying that the same effect can be obtained when nmax>6.

As mentioned above, in the method of the present invention, key codes can be multiplied by setting the frequency of the master clock oscillator 17. The results show that it is sufficient to change the value by approximately 1.05 times. According to this result, approximately 15 key chords can be obtained per octave. Further, when a BBD element is used as an example of the variable delay circuit 3, since the clock frequency range of the BBD is approximately 10 to 100 KHz for commercially available BBDs, a clock frequency of approximately 2.5 octaves can be obtained.

Therefore, it can be said that the confidential circuit system of the present invention is a device that can obtain a practically sufficient key code.

In the above explanation, in order to simplify the explanation, the BBD variable delay circuits 3 and 14 on the transmitting side and the receiving side are used.
Since we have explained an example in which the number of delay stages is 2 ^N , the repetition frequency of the clock pulses applied to the delay circuits 3 and 14 is 2 ^N +2 ^N = 2 ^N+1 in the counter circuit 19 as shown in FIG. However, if the number of delay stages of the variable delay circuit 14 on the receiving side is 2 ^M , the repetition frequency of the frequency control voltage is such that the counter circuit counts (2 ^M + 2 ^N ) pulses. It is sufficient to set the period to be counted.

(f) Effect As described above, the present invention provides a secret communication circuit that can obtain a large number of key codes, and if a radio equipped with this system is used, the contents of the call will not be intercepted even if received by a third party. This has a great practical effect in ensuring the privacy of calls.

Furthermore, the present invention provides a circuit configuration in which the clock frequency repeatedly rises and falls repeatedly, which has the effect of reducing deterioration in sound quality when synchronization shifts occur.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing the principle of the present invention.
FIG. 2 is a block circuit diagram of the main part of the confidential circuit in the present invention, FIGS. 3 and 4 are diagrams showing the frequency change characteristics of conventional clock pulses, and FIG. 5 is a diagram of the logic circuit used in the device of the present invention. Embodiment FIG. 6 is a logic diagram when the logic circuit of FIG. 5 is used. Explanation of figure numbers, 3, 14... BBD delay circuit, 1
7... Master clock oscillation circuit, 18... Frequency dividing circuit, 19... Control counter, 20... Logic circuit, 21... Clock pulse, 22... Multiplexer, 23... OR circuit, 24... AND circuit .

Claims (1)

[Scope of Claims] 1 (a) a variable delay circuit for signals that sequentially samples and stores signals in accordance with clock pulses and simultaneously outputs them; (b) a master clock frequency oscillation circuit that supplies the clock pulses; (c ) a frequency divider circuit that divides the output frequency of the oscillation circuit; (d) a clock pulse counter circuit that counts clock pulses supplied to the variable delay circuit; and (e) an output signal of the clock pulse counter circuit. A logic circuit for controlling the frequency division number of the frequency divider circuit is provided on the transmitting side and the receiving side of the communication system, and the sum of the number of delay stages of the variable delay circuits on the transmitting side and the receiving side is 2 ^N+1 (however, N is an integer), and
The clock pulse counter circuit is composed of 2 ^N- ary counters, and the output of the circuit is input from the upper level (Q ₁ ).
(Q ₂ )...(Q _N ), furthermore, the frequency dividing circuit is configured with a frequency dividing counter, and the outputs of the counter are (P ₁ ) (P ₂ )...(Pn) from the upper order, and the logic circuit The output of the multiplexer of (S ₁ ) (S ₂ )…(Sn)
When, the frequency division number of the frequency division counter is controlled using the signal (Re) of the following logic as the reset signal of the frequency division counter, Re=(P ₁ +S ₁ )・(P ₂ +S ₂ )...(Pn+Sn) Here, Sk (k = 1 to n) is (a) When Q ₁ = 0, S ₁ = Q ₂ , S ₂ = S ₃ = ₂ , Sk = Qk _-1 , ( (b) When Q ₁ = 1, S ₁ = ₂ , S ₂ = S ₃ = Q ₂ , Sk = _-1 (If,
k≧4) A time period during which the clock pulse counter circuit counts the clock pulses supplied to the variable delay circuit by the sum of the number of delay stages of the variable delay circuit on the transmitting side and the number of delay stages of the variable delay circuit on the receiving side. By changing the frequency of the clock pulse supplied to the variable delay circuit, the time axis of the transmission signal is alternately compressed and expanded, thereby converting the frequency of the transmission signal and sending it from the transmitting side to the transmission system. , a confidential communication device characterized in that the original signal is regenerated on the receiving side. 2. (a) a variable delay circuit for sequentially sampling and storing signals in accordance with clock pulses, and outputting signals at the same time; (b) a master clock frequency oscillation circuit for supplying the clock pulses; and (c) an output of the oscillation circuit. (d) a clock pulse counter circuit that counts clock pulses supplied to the variable delay circuit; (e) a frequency divider circuit that divides the frequency by the output signal of the clock pulse counter circuit; A logic circuit for controlling the number of cycles is provided on the transmitting side and the receiving side of the communication system, and the sum of the number of delay stages of the variable delay circuits on the transmitting side and the receiving side is 2 ^{N + 1} (N is an integer), Also,
The clock pulse counter circuit is composed of 2 ^N- ary counters, and the output of the circuit is input from the upper level (Q ₁ ).
(Q ₂ )...(Q _N ), furthermore, the frequency dividing circuit is configured with a frequency dividing counter, and the outputs of the counter are (P ₁ ) (P ₂ )...(Pn) from the upper order, and the logic circuit is When the output of the multiplexer is (S ₁ ) (S ₂ )...(Sn), the frequency division number of the frequency division counter is set using the signal (Re) of the following logic as the reset signal of the frequency division counter. Re = (P ₁ + S ₁ )・(P ₂ +S ₂ )…・(Pn + Sn) Here, Sk (k = 1 to n) is (a) When Q ₁ = 0, S ₁ = Q ₂ , S ₂ = S ₃ = ₂ , Sk = Qk _-1 (however,
k≧4) (b) When Q ₁ = 1, S ₁ = ₂ , S ₂ = S ₃ = Q ₂ , Sk = _-1 (However,
k≧4) A time period during which the clock pulse counter circuit counts the clock pulses supplied to the variable delay circuit by the sum of the number of delay stages of the variable delay circuit on the transmitting side and the number of delay stages of the variable delay circuit on the receiving side. By changing the frequency of the clock pulse supplied to the variable delay circuit, the time axis of the transmission signal is alternately compressed and expanded, thereby converting the frequency of the transmission signal and sending it from the transmitting side to the transmission system. , by reproducing the original signal on the receiving side and changing the output frequency of the master clock frequency oscillation circuit or the logic configuration of the logic circuit, the frequency change of the clock pulse supplied to the variable delay circuit is controlled to a predetermined value. A secret communication device characterized by setting a characteristic and converting it into a key code.